SConscript revision 11974
1955SN/A# -*- mode:python -*- 2955SN/A 31762SN/A# Copyright (c) 2006 The Regents of The University of Michigan 4955SN/A# All rights reserved. 5955SN/A# 6955SN/A# Redistribution and use in source and binary forms, with or without 7955SN/A# modification, are permitted provided that the following conditions are 8955SN/A# met: redistributions of source code must retain the above copyright 9955SN/A# notice, this list of conditions and the following disclaimer; 10955SN/A# redistributions in binary form must reproduce the above copyright 11955SN/A# notice, this list of conditions and the following disclaimer in the 12955SN/A# documentation and/or other materials provided with the distribution; 13955SN/A# neither the name of the copyright holders nor the names of its 14955SN/A# contributors may be used to endorse or promote products derived from 15955SN/A# this software without specific prior written permission. 16955SN/A# 17955SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18955SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19955SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20955SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21955SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22955SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23955SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24955SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25955SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26955SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27955SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu# 292665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 30955SN/A 31955SN/AImport('*') 32955SN/A 331608SN/Aif env['TARGET_ISA'] == 'null': 34955SN/A SimObject('IntrControl.py') 35955SN/A Source('intr_control_noisa.cc') 36955SN/A Return() 37955SN/A 38955SN/A# Only build the protocol buffer instructions tracer if we have protobuf support 39955SN/Aif env['HAVE_PROTOBUF'] and env['TARGET_ISA'] != 'x86': 40955SN/A SimObject('InstPBTrace.py') 41955SN/A Source('inst_pb_trace.cc') 42955SN/A 43955SN/ASimObject('CheckerCPU.py') 44955SN/A 45955SN/ASimObject('BaseCPU.py') 46955SN/ASimObject('CPUTracers.py') 47955SN/ASimObject('FuncUnit.py') 482023SN/ASimObject('IntrControl.py') 49955SN/ASimObject('TimingExpr.py') 50955SN/A 51955SN/ASource('activity.cc') 52955SN/ASource('base.cc') 53955SN/ASource('cpuevent.cc') 54955SN/ASource('exetrace.cc') 55955SN/ASource('exec_context.cc') 56955SN/ASource('func_unit.cc') 57955SN/ASource('inteltrace.cc') 581031SN/ASource('intr_control.cc') 59955SN/ASource('nativetrace.cc') 601388SN/ASource('pc_event.cc') 61955SN/ASource('profile.cc') 62955SN/ASource('quiesce_event.cc') 631296SN/ASource('reg_class.cc') 64955SN/ASource('static_inst.cc') 65955SN/ASource('simple_thread.cc') 66955SN/ASource('thread_context.cc') 67955SN/ASource('thread_state.cc') 68955SN/ASource('timing_expr.cc') 69955SN/A 70955SN/ASimObject('DummyChecker.py') 71955SN/ASimObject('StaticInstFlags.py') 72955SN/ASource('checker/cpu.cc') 73955SN/ASource('dummy_checker.cc') 74955SN/ADebugFlag('Checker') 75955SN/A 76955SN/ADebugFlag('Activity') 77955SN/ADebugFlag('Commit') 78955SN/ADebugFlag('Context') 79955SN/ADebugFlag('Decode') 80955SN/ADebugFlag('DynInst') 81955SN/ADebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)') 82955SN/ADebugFlag('ExecCPSeq', 'Format: Instruction sequence number') 832325SN/ADebugFlag('ExecEffAddr', 'Format: Include effective address') 841717SN/ADebugFlag('ExecFaulting', 'Trace faulting instructions') 852652Ssaidi@eecs.umich.eduDebugFlag('ExecFetchSeq', 'Format: Fetch sequence number') 86955SN/ADebugFlag('ExecOpClass', 'Format: Include operand class') 872736Sktlim@umich.eduDebugFlag('ExecRegDelta') 882410SN/ADebugFlag('ExecResult', 'Format: Include results from execution') 89955SN/ADebugFlag('ExecSymbol', 'Format: Try to include symbol names') 902290SN/ADebugFlag('ExecThread', 'Format: Include thread ID in trace') 91955SN/ADebugFlag('ExecTicks', 'Format: Include tick count') 922683Sktlim@umich.eduDebugFlag('ExecMicro', 'Filter: Include microops') 932683Sktlim@umich.eduDebugFlag('ExecMacro', 'Filter: Include macroops') 942669Sktlim@umich.eduDebugFlag('ExecUser', 'Filter: Trace user mode instructions') 952568SN/ADebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions') 962568SN/ADebugFlag('ExecAsid', 'Format: Include ASID in trace') 973012Ssaidi@eecs.umich.eduDebugFlag('ExecFlags', 'Format: Include instruction flags in trace') 982462SN/ADebugFlag('Fetch') 992568SN/ADebugFlag('IntrControl') 1002395SN/ADebugFlag('O3PipeView') 1012405SN/ADebugFlag('PCEvent') 1022914Ssaidi@eecs.umich.eduDebugFlag('Quiesce') 103955SN/ADebugFlag('Mwait') 1042811Srdreslin@umich.edu 1052811Srdreslin@umich.eduCompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr', 1062811Srdreslin@umich.edu 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta', 1072811Srdreslin@umich.edu 'ExecResult', 'ExecSymbol', 'ExecThread', 1082811Srdreslin@umich.edu 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel', 1092811Srdreslin@umich.edu 'ExecAsid', 'ExecFlags' ]) 1102811Srdreslin@umich.eduCompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 1112811Srdreslin@umich.edu 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecMacro', 1122811Srdreslin@umich.edu 'ExecFaulting', 'ExecUser', 'ExecKernel' ]) 1132811Srdreslin@umich.eduCompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', 1142811Srdreslin@umich.edu 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecMacro', 'ExecFaulting', 1152811Srdreslin@umich.edu 'ExecUser', 'ExecKernel' ]) 1162811Srdreslin@umich.edu