BaseCPU.py revision 9650:d79319eb68d5
14604Sgblack@eecs.umich.edu# Copyright (c) 2012 ARM Limited 24604Sgblack@eecs.umich.edu# All rights reserved. 34604Sgblack@eecs.umich.edu# 44604Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 54604Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 64604Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 74604Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 84604Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 94604Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 104604Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 114604Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 124604Sgblack@eecs.umich.edu# 134604Sgblack@eecs.umich.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 144604Sgblack@eecs.umich.edu# Copyright (c) 2011 Regents of the University of California 154604Sgblack@eecs.umich.edu# All rights reserved. 164604Sgblack@eecs.umich.edu# 174604Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 184604Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 194604Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 204604Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 214604Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 224604Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 234604Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 244604Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 254604Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 264604Sgblack@eecs.umich.edu# this software without specific prior written permission. 274604Sgblack@eecs.umich.edu# 284604Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294604Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304604Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314604Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324604Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334604Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344604Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354604Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364604Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374604Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384604Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394604Sgblack@eecs.umich.edu# 404604Sgblack@eecs.umich.edu# Authors: Nathan Binkert 414604Sgblack@eecs.umich.edu# Rick Strong 424604Sgblack@eecs.umich.edu# Andreas Hansson 434604Sgblack@eecs.umich.edu 444604Sgblack@eecs.umich.eduimport sys 454604Sgblack@eecs.umich.edu 464604Sgblack@eecs.umich.edufrom m5.defines import buildEnv 474604Sgblack@eecs.umich.edufrom m5.params import * 484604Sgblack@eecs.umich.edufrom m5.proxy import * 494604Sgblack@eecs.umich.edu 504604Sgblack@eecs.umich.edufrom Bus import CoherentBus 514604Sgblack@eecs.umich.edufrom InstTracer import InstTracer 524604Sgblack@eecs.umich.edufrom ExeTracer import ExeTracer 534604Sgblack@eecs.umich.edufrom MemObject import MemObject 544604Sgblack@eecs.umich.edufrom BranchPredictor import BranchPredictor 554604Sgblack@eecs.umich.edu 564604Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 574604Sgblack@eecs.umich.edu 585616Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 595616Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 604604Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 614604Sgblack@eecs.umich.edu from AlphaISA import AlphaISA 624604Sgblack@eecs.umich.edu isa_class = AlphaISA 634604Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'sparc': 644604Sgblack@eecs.umich.edu from SparcTLB import SparcTLB 654604Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 664604Sgblack@eecs.umich.edu from SparcISA import SparcISA 674604Sgblack@eecs.umich.edu isa_class = SparcISA 684604Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'x86': 694604Sgblack@eecs.umich.edu from X86TLB import X86TLB 704604Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 714712Sgblack@eecs.umich.edu from X86ISA import X86ISA 724712Sgblack@eecs.umich.edu isa_class = X86ISA 734604Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'mips': 744604Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 754604Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 764604Sgblack@eecs.umich.edu from MipsISA import MipsISA 774604Sgblack@eecs.umich.edu isa_class = MipsISA 784848Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'arm': 794604Sgblack@eecs.umich.edu from ArmTLB import ArmTLB 804604Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 814604Sgblack@eecs.umich.edu from ArmISA import ArmISA 826071Sgblack@eecs.umich.edu isa_class = ArmISA 836071Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'power': 846071Sgblack@eecs.umich.edu from PowerTLB import PowerTLB 856071Sgblack@eecs.umich.edu from PowerInterrupts import PowerInterrupts 866071Sgblack@eecs.umich.edu from PowerISA import PowerISA 876071Sgblack@eecs.umich.edu isa_class = PowerISA 886071Sgblack@eecs.umich.edu 896071Sgblack@eecs.umich.educlass BaseCPU(MemObject): 906071Sgblack@eecs.umich.edu type = 'BaseCPU' 916071Sgblack@eecs.umich.edu abstract = True 926071Sgblack@eecs.umich.edu cxx_header = "cpu/base.hh" 936071Sgblack@eecs.umich.edu 946071Sgblack@eecs.umich.edu @classmethod 956071Sgblack@eecs.umich.edu def export_methods(cls, code): 966071Sgblack@eecs.umich.edu code(''' 976071Sgblack@eecs.umich.edu void switchOut(); 986071Sgblack@eecs.umich.edu void takeOverFrom(BaseCPU *cpu); 996071Sgblack@eecs.umich.edu bool switchedOut(); 1006071Sgblack@eecs.umich.edu void flushTLBs(); 1016071Sgblack@eecs.umich.edu Counter totalInsts(); 1026071Sgblack@eecs.umich.edu''') 1036071Sgblack@eecs.umich.edu 1046071Sgblack@eecs.umich.edu @classmethod 1056071Sgblack@eecs.umich.edu def memory_mode(cls): 1066071Sgblack@eecs.umich.edu """Which memory mode does this CPU require?""" 1076071Sgblack@eecs.umich.edu return 'invalid' 1084604Sgblack@eecs.umich.edu 1094604Sgblack@eecs.umich.edu @classmethod 1104712Sgblack@eecs.umich.edu def require_caches(cls): 1114604Sgblack@eecs.umich.edu """Does the CPU model require caches? 1124712Sgblack@eecs.umich.edu 1134712Sgblack@eecs.umich.edu Some CPU models might make assumptions that require them to 1144848Sgblack@eecs.umich.edu have caches. 1154604Sgblack@eecs.umich.edu """ 1164604Sgblack@eecs.umich.edu return False 1174604Sgblack@eecs.umich.edu 1184863Sgblack@eecs.umich.edu @classmethod 1194863Sgblack@eecs.umich.edu def support_take_over(cls): 1204863Sgblack@eecs.umich.edu """Does the CPU model support CPU takeOverFrom?""" 1216437Sgblack@eecs.umich.edu return False 1224863Sgblack@eecs.umich.edu 1234863Sgblack@eecs.umich.edu def takeOverFrom(self, old_cpu): 1244863Sgblack@eecs.umich.edu self._ccObject.takeOverFrom(old_cpu._ccObject) 1254863Sgblack@eecs.umich.edu 1264863Sgblack@eecs.umich.edu 1274863Sgblack@eecs.umich.edu system = Param.System(Parent.any, "system object") 1284863Sgblack@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 1294863Sgblack@eecs.umich.edu numThreads = Param.Unsigned(1, "number of HW thread contexts") 1304604Sgblack@eecs.umich.edu 1314604Sgblack@eecs.umich.edu function_trace = Param.Bool(False, "Enable function trace") 1325966Sgblack@eecs.umich.edu function_trace_start = Param.Tick(0, "Tick to start function trace") 1335966Sgblack@eecs.umich.edu 1345966Sgblack@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1355966Sgblack@eecs.umich.edu 1365966Sgblack@eecs.umich.edu do_checkpoint_insts = Param.Bool(True, 1375966Sgblack@eecs.umich.edu "enable checkpoint pseudo instructions") 1385966Sgblack@eecs.umich.edu do_statistics_insts = Param.Bool(True, 1395966Sgblack@eecs.umich.edu "enable statistics pseudo instructions") 140 141 profile = Param.Latency('0ns', "trace the kernel stack") 142 do_quiesce = Param.Bool(True, "enable quiesce instructions") 143 144 workload = VectorParam.Process([], "processes to run") 145 146 if buildEnv['TARGET_ISA'] == 'sparc': 147 dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 148 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 149 interrupts = Param.SparcInterrupts( 150 NULL, "Interrupt Controller") 151 isa = VectorParam.SparcISA([ isa_class() ], "ISA instance") 152 elif buildEnv['TARGET_ISA'] == 'alpha': 153 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 154 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 155 interrupts = Param.AlphaInterrupts( 156 NULL, "Interrupt Controller") 157 isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance") 158 elif buildEnv['TARGET_ISA'] == 'x86': 159 dtb = Param.X86TLB(X86TLB(), "Data TLB") 160 itb = Param.X86TLB(X86TLB(), "Instruction TLB") 161 interrupts = Param.X86LocalApic(NULL, "Interrupt Controller") 162 isa = VectorParam.X86ISA([ isa_class() ], "ISA instance") 163 elif buildEnv['TARGET_ISA'] == 'mips': 164 dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 165 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 166 interrupts = Param.MipsInterrupts( 167 NULL, "Interrupt Controller") 168 isa = VectorParam.MipsISA([ isa_class() ], "ISA instance") 169 elif buildEnv['TARGET_ISA'] == 'arm': 170 dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 171 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 172 interrupts = Param.ArmInterrupts( 173 NULL, "Interrupt Controller") 174 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance") 175 elif buildEnv['TARGET_ISA'] == 'power': 176 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 177 dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 178 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 179 interrupts = Param.PowerInterrupts( 180 NULL, "Interrupt Controller") 181 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance") 182 else: 183 print "Don't know what TLB to use for ISA %s" % \ 184 buildEnv['TARGET_ISA'] 185 sys.exit(1) 186 187 max_insts_all_threads = Param.Counter(0, 188 "terminate when all threads have reached this inst count") 189 max_insts_any_thread = Param.Counter(0, 190 "terminate when any thread reaches this inst count") 191 simpoint_start_insts = VectorParam.Counter([], 192 "starting instruction counts of simpoints") 193 max_loads_all_threads = Param.Counter(0, 194 "terminate when all threads have reached this load count") 195 max_loads_any_thread = Param.Counter(0, 196 "terminate when any thread reaches this load count") 197 progress_interval = Param.Frequency('0Hz', 198 "frequency to print out the progress message") 199 200 switched_out = Param.Bool(False, 201 "Leave the CPU switched out after startup (used when switching " \ 202 "between CPU models)") 203 204 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 205 206 icache_port = MasterPort("Instruction Port") 207 dcache_port = MasterPort("Data Port") 208 _cached_ports = ['icache_port', 'dcache_port'] 209 210 branchPred = Param.BranchPredictor(NULL, "Branch Predictor") 211 212 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 213 _cached_ports += ["itb.walker.port", "dtb.walker.port"] 214 215 _uncached_slave_ports = [] 216 _uncached_master_ports = [] 217 if buildEnv['TARGET_ISA'] == 'x86': 218 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] 219 _uncached_master_ports += ["interrupts.int_master"] 220 221 def createInterruptController(self): 222 if buildEnv['TARGET_ISA'] == 'sparc': 223 self.interrupts = SparcInterrupts() 224 elif buildEnv['TARGET_ISA'] == 'alpha': 225 self.interrupts = AlphaInterrupts() 226 elif buildEnv['TARGET_ISA'] == 'x86': 227 self.interrupts = X86LocalApic(clock = Parent.clock * 16, 228 pio_addr=0x2000000000000000) 229 _localApic = self.interrupts 230 elif buildEnv['TARGET_ISA'] == 'mips': 231 self.interrupts = MipsInterrupts() 232 elif buildEnv['TARGET_ISA'] == 'arm': 233 self.interrupts = ArmInterrupts() 234 elif buildEnv['TARGET_ISA'] == 'power': 235 self.interrupts = PowerInterrupts() 236 else: 237 print "Don't know what Interrupt Controller to use for ISA %s" % \ 238 buildEnv['TARGET_ISA'] 239 sys.exit(1) 240 241 def connectCachedPorts(self, bus): 242 for p in self._cached_ports: 243 exec('self.%s = bus.slave' % p) 244 245 def connectUncachedPorts(self, bus): 246 for p in self._uncached_slave_ports: 247 exec('self.%s = bus.master' % p) 248 for p in self._uncached_master_ports: 249 exec('self.%s = bus.slave' % p) 250 251 def connectAllPorts(self, cached_bus, uncached_bus = None): 252 self.connectCachedPorts(cached_bus) 253 if not uncached_bus: 254 uncached_bus = cached_bus 255 self.connectUncachedPorts(uncached_bus) 256 257 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 258 self.icache = ic 259 self.dcache = dc 260 self.icache_port = ic.cpu_side 261 self.dcache_port = dc.cpu_side 262 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 263 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 264 if iwc and dwc: 265 self.itb_walker_cache = iwc 266 self.dtb_walker_cache = dwc 267 self.itb.walker.port = iwc.cpu_side 268 self.dtb.walker.port = dwc.cpu_side 269 self._cached_ports += ["itb_walker_cache.mem_side", \ 270 "dtb_walker_cache.mem_side"] 271 else: 272 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 273 274 # Checker doesn't need its own tlb caches because it does 275 # functional accesses only 276 if self.checker != NULL: 277 self._cached_ports += ["checker.itb.walker.port", \ 278 "checker.dtb.walker.port"] 279 280 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 281 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 282 # Override the default bus clock of 1 GHz and uses the CPU 283 # clock for the L1-to-L2 bus, and also set a width of 32 bytes 284 # (256-bits), which is four times that of the default bus. 285 self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32) 286 self.connectCachedPorts(self.toL2Bus) 287 self.l2cache = l2c 288 self.toL2Bus.master = self.l2cache.cpu_side 289 self._cached_ports = ['l2cache.mem_side'] 290 291 def createThreads(self): 292 self.isa = [ isa_class() for i in xrange(self.numThreads) ] 293 if self.checker != NULL: 294 self.checker.createThreads() 295 296 def addCheckerCpu(self): 297 pass 298