BaseCPU.py revision 9650 
1# Copyright (c) 2012 ARM Limited
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13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
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39#
40# Authors: Nathan Binkert
41#          Rick Strong
42#          Andreas Hansson
43
44import sys
45
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54from BranchPredictor import BranchPredictor
55
56default_tracer = ExeTracer()
57
58if buildEnv['TARGET_ISA'] == 'alpha':
59    from AlphaTLB import AlphaDTB, AlphaITB
60    from AlphaInterrupts import AlphaInterrupts
61    from AlphaISA import AlphaISA
62    isa_class = AlphaISA
63elif buildEnv['TARGET_ISA'] == 'sparc':
64    from SparcTLB import SparcTLB
65    from SparcInterrupts import SparcInterrupts
66    from SparcISA import SparcISA
67    isa_class = SparcISA
68elif buildEnv['TARGET_ISA'] == 'x86':
69    from X86TLB import X86TLB
70    from X86LocalApic import X86LocalApic
71    from X86ISA import X86ISA
72    isa_class = X86ISA
73elif buildEnv['TARGET_ISA'] == 'mips':
74    from MipsTLB import MipsTLB
75    from MipsInterrupts import MipsInterrupts
76    from MipsISA import MipsISA
77    isa_class = MipsISA
78elif buildEnv['TARGET_ISA'] == 'arm':
79    from ArmTLB import ArmTLB
80    from ArmInterrupts import ArmInterrupts
81    from ArmISA import ArmISA
82    isa_class = ArmISA
83elif buildEnv['TARGET_ISA'] == 'power':
84    from PowerTLB import PowerTLB
85    from PowerInterrupts import PowerInterrupts
86    from PowerISA import PowerISA
87    isa_class = PowerISA
88
89class BaseCPU(MemObject):
90    type = 'BaseCPU'
91    abstract = True
92    cxx_header = "cpu/base.hh"
93
94    @classmethod
95    def export_methods(cls, code):
96        code('''
97    void switchOut();
98    void takeOverFrom(BaseCPU *cpu);
99    bool switchedOut();
100    void flushTLBs();
101    Counter totalInsts();
102''')
103
104    @classmethod
105    def memory_mode(cls):
106        """Which memory mode does this CPU require?"""
107        return 'invalid'
108
109    @classmethod
110    def require_caches(cls):
111        """Does the CPU model require caches?
112
113        Some CPU models might make assumptions that require them to
114        have caches.
115        """
116        return False
117
118    @classmethod
119    def support_take_over(cls):
120        """Does the CPU model support CPU takeOverFrom?"""
121        return False
122
123    def takeOverFrom(self, old_cpu):
124        self._ccObject.takeOverFrom(old_cpu._ccObject)
125
126
127    system = Param.System(Parent.any, "system object")
128    cpu_id = Param.Int(-1, "CPU identifier")
129    numThreads = Param.Unsigned(1, "number of HW thread contexts")
130
131    function_trace = Param.Bool(False, "Enable function trace")
132    function_trace_start = Param.Tick(0, "Tick to start function trace")
133
134    checker = Param.BaseCPU(NULL, "checker CPU")
135
136    do_checkpoint_insts = Param.Bool(True,
137        "enable checkpoint pseudo instructions")
138    do_statistics_insts = Param.Bool(True,
139        "enable statistics pseudo instructions")
140
141    profile = Param.Latency('0ns', "trace the kernel stack")
142    do_quiesce = Param.Bool(True, "enable quiesce instructions")
143
144    workload = VectorParam.Process([], "processes to run")
145
146    if buildEnv['TARGET_ISA'] == 'sparc':
147        dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
148        itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
149        interrupts = Param.SparcInterrupts(
150                NULL, "Interrupt Controller")
151        isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
152    elif buildEnv['TARGET_ISA'] == 'alpha':
153        dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
154        itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
155        interrupts = Param.AlphaInterrupts(
156                NULL, "Interrupt Controller")
157        isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
158    elif buildEnv['TARGET_ISA'] == 'x86':
159        dtb = Param.X86TLB(X86TLB(), "Data TLB")
160        itb = Param.X86TLB(X86TLB(), "Instruction TLB")
161        interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
162        isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
163    elif buildEnv['TARGET_ISA'] == 'mips':
164        dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
165        itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
166        interrupts = Param.MipsInterrupts(
167                NULL, "Interrupt Controller")
168        isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
169    elif buildEnv['TARGET_ISA'] == 'arm':
170        dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
171        itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
172        interrupts = Param.ArmInterrupts(
173                NULL, "Interrupt Controller")
174        isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
175    elif buildEnv['TARGET_ISA'] == 'power':
176        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
177        dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
178        itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
179        interrupts = Param.PowerInterrupts(
180                NULL, "Interrupt Controller")
181        isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
182    else:
183        print "Don't know what TLB to use for ISA %s" % \
184            buildEnv['TARGET_ISA']
185        sys.exit(1)
186
187    max_insts_all_threads = Param.Counter(0,
188        "terminate when all threads have reached this inst count")
189    max_insts_any_thread = Param.Counter(0,
190        "terminate when any thread reaches this inst count")
191    simpoint_start_insts = VectorParam.Counter([],
192        "starting instruction counts of simpoints")
193    max_loads_all_threads = Param.Counter(0,
194        "terminate when all threads have reached this load count")
195    max_loads_any_thread = Param.Counter(0,
196        "terminate when any thread reaches this load count")
197    progress_interval = Param.Frequency('0Hz',
198        "frequency to print out the progress message")
199
200    switched_out = Param.Bool(False,
201        "Leave the CPU switched out after startup (used when switching " \
202        "between CPU models)")
203
204    tracer = Param.InstTracer(default_tracer, "Instruction tracer")
205
206    icache_port = MasterPort("Instruction Port")
207    dcache_port = MasterPort("Data Port")
208    _cached_ports = ['icache_port', 'dcache_port']
209
210    branchPred = Param.BranchPredictor(NULL, "Branch Predictor")
211
212    if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
213        _cached_ports += ["itb.walker.port", "dtb.walker.port"]
214
215    _uncached_slave_ports = []
216    _uncached_master_ports = []
217    if buildEnv['TARGET_ISA'] == 'x86':
218        _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
219        _uncached_master_ports += ["interrupts.int_master"]
220
221    def createInterruptController(self):
222        if buildEnv['TARGET_ISA'] == 'sparc':
223            self.interrupts = SparcInterrupts()
224        elif buildEnv['TARGET_ISA'] == 'alpha':
225            self.interrupts = AlphaInterrupts()
226        elif buildEnv['TARGET_ISA'] == 'x86':
227            self.interrupts = X86LocalApic(clock = Parent.clock * 16,
228                                           pio_addr=0x2000000000000000)
229            _localApic = self.interrupts
230        elif buildEnv['TARGET_ISA'] == 'mips':
231            self.interrupts = MipsInterrupts()
232        elif buildEnv['TARGET_ISA'] == 'arm':
233            self.interrupts = ArmInterrupts()
234        elif buildEnv['TARGET_ISA'] == 'power':
235            self.interrupts = PowerInterrupts()
236        else:
237            print "Don't know what Interrupt Controller to use for ISA %s" % \
238                buildEnv['TARGET_ISA']
239            sys.exit(1)
240
241    def connectCachedPorts(self, bus):
242        for p in self._cached_ports:
243            exec('self.%s = bus.slave' % p)
244
245    def connectUncachedPorts(self, bus):
246        for p in self._uncached_slave_ports:
247            exec('self.%s = bus.master' % p)
248        for p in self._uncached_master_ports:
249            exec('self.%s = bus.slave' % p)
250
251    def connectAllPorts(self, cached_bus, uncached_bus = None):
252        self.connectCachedPorts(cached_bus)
253        if not uncached_bus:
254            uncached_bus = cached_bus
255        self.connectUncachedPorts(uncached_bus)
256
257    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
258        self.icache = ic
259        self.dcache = dc
260        self.icache_port = ic.cpu_side
261        self.dcache_port = dc.cpu_side
262        self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
263        if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
264            if iwc and dwc:
265                self.itb_walker_cache = iwc
266                self.dtb_walker_cache = dwc
267                self.itb.walker.port = iwc.cpu_side
268                self.dtb.walker.port = dwc.cpu_side
269                self._cached_ports += ["itb_walker_cache.mem_side", \
270                                       "dtb_walker_cache.mem_side"]
271            else:
272                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
273
274            # Checker doesn't need its own tlb caches because it does
275            # functional accesses only
276            if self.checker != NULL:
277                self._cached_ports += ["checker.itb.walker.port", \
278                                       "checker.dtb.walker.port"]
279
280    def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
281        self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
282        # Override the default bus clock of 1 GHz and uses the CPU
283        # clock for the L1-to-L2 bus, and also set a width of 32 bytes
284        # (256-bits), which is four times that of the default bus.
285        self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
286        self.connectCachedPorts(self.toL2Bus)
287        self.l2cache = l2c
288        self.toL2Bus.master = self.l2cache.cpu_side
289        self._cached_ports = ['l2cache.mem_side']
290
291    def createThreads(self):
292        self.isa = [ isa_class() for i in xrange(self.numThreads) ]
293        if self.checker != NULL:
294            self.checker.createThreads()
295
296    def addCheckerCpu(self):
297        pass
298