BaseCPU.py revision 9430 
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
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7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
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11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
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18# modification, are permitted provided that the following conditions are
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28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41#          Rick Strong
42#          Andreas Hansson
43
44import sys
45
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54
55default_tracer = ExeTracer()
56
57if buildEnv['TARGET_ISA'] == 'alpha':
58    from AlphaTLB import AlphaDTB, AlphaITB
59    from AlphaInterrupts import AlphaInterrupts
60    from AlphaISA import AlphaISA
61    isa_class = AlphaISA
62elif buildEnv['TARGET_ISA'] == 'sparc':
63    from SparcTLB import SparcTLB
64    from SparcInterrupts import SparcInterrupts
65    from SparcISA import SparcISA
66    isa_class = SparcISA
67elif buildEnv['TARGET_ISA'] == 'x86':
68    from X86TLB import X86TLB
69    from X86LocalApic import X86LocalApic
70    from X86ISA import X86ISA
71    isa_class = X86ISA
72elif buildEnv['TARGET_ISA'] == 'mips':
73    from MipsTLB import MipsTLB
74    from MipsInterrupts import MipsInterrupts
75    from MipsISA import MipsISA
76    isa_class = MipsISA
77elif buildEnv['TARGET_ISA'] == 'arm':
78    from ArmTLB import ArmTLB
79    from ArmInterrupts import ArmInterrupts
80    from ArmISA import ArmISA
81    isa_class = ArmISA
82elif buildEnv['TARGET_ISA'] == 'power':
83    from PowerTLB import PowerTLB
84    from PowerInterrupts import PowerInterrupts
85    from PowerISA import PowerISA
86    isa_class = PowerISA
87
88class BaseCPU(MemObject):
89    type = 'BaseCPU'
90    abstract = True
91    cxx_header = "cpu/base.hh"
92
93    @classmethod
94    def export_methods(cls, code):
95        code('''
96    void switchOut();
97    void takeOverFrom(BaseCPU *cpu);
98    bool switchedOut();
99''')
100
101    def takeOverFrom(self, old_cpu):
102        self._ccObject.takeOverFrom(old_cpu._ccObject)
103
104
105    system = Param.System(Parent.any, "system object")
106    cpu_id = Param.Int(-1, "CPU identifier")
107    numThreads = Param.Unsigned(1, "number of HW thread contexts")
108
109    function_trace = Param.Bool(False, "Enable function trace")
110    function_trace_start = Param.Tick(0, "Tick to start function trace")
111
112    checker = Param.BaseCPU(NULL, "checker CPU")
113
114    do_checkpoint_insts = Param.Bool(True,
115        "enable checkpoint pseudo instructions")
116    do_statistics_insts = Param.Bool(True,
117        "enable statistics pseudo instructions")
118
119    profile = Param.Latency('0ns', "trace the kernel stack")
120    do_quiesce = Param.Bool(True, "enable quiesce instructions")
121
122    workload = VectorParam.Process([], "processes to run")
123
124    if buildEnv['TARGET_ISA'] == 'sparc':
125        dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
126        itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
127        interrupts = Param.SparcInterrupts(
128                NULL, "Interrupt Controller")
129        isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
130    elif buildEnv['TARGET_ISA'] == 'alpha':
131        dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
132        itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
133        interrupts = Param.AlphaInterrupts(
134                NULL, "Interrupt Controller")
135        isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
136    elif buildEnv['TARGET_ISA'] == 'x86':
137        dtb = Param.X86TLB(X86TLB(), "Data TLB")
138        itb = Param.X86TLB(X86TLB(), "Instruction TLB")
139        interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
140        isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
141    elif buildEnv['TARGET_ISA'] == 'mips':
142        dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
143        itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
144        interrupts = Param.MipsInterrupts(
145                NULL, "Interrupt Controller")
146        isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
147    elif buildEnv['TARGET_ISA'] == 'arm':
148        dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
149        itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
150        interrupts = Param.ArmInterrupts(
151                NULL, "Interrupt Controller")
152        isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
153    elif buildEnv['TARGET_ISA'] == 'power':
154        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
155        dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
156        itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
157        interrupts = Param.PowerInterrupts(
158                NULL, "Interrupt Controller")
159        isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
160    else:
161        print "Don't know what TLB to use for ISA %s" % \
162            buildEnv['TARGET_ISA']
163        sys.exit(1)
164
165    max_insts_all_threads = Param.Counter(0,
166        "terminate when all threads have reached this inst count")
167    max_insts_any_thread = Param.Counter(0,
168        "terminate when any thread reaches this inst count")
169    max_loads_all_threads = Param.Counter(0,
170        "terminate when all threads have reached this load count")
171    max_loads_any_thread = Param.Counter(0,
172        "terminate when any thread reaches this load count")
173    progress_interval = Param.Frequency('0Hz',
174        "frequency to print out the progress message")
175
176    defer_registration = Param.Bool(False,
177        "defer registration with system (for sampling)")
178
179    tracer = Param.InstTracer(default_tracer, "Instruction tracer")
180
181    icache_port = MasterPort("Instruction Port")
182    dcache_port = MasterPort("Data Port")
183    _cached_ports = ['icache_port', 'dcache_port']
184
185    if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
186        _cached_ports += ["itb.walker.port", "dtb.walker.port"]
187
188    _uncached_slave_ports = []
189    _uncached_master_ports = []
190    if buildEnv['TARGET_ISA'] == 'x86':
191        _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
192        _uncached_master_ports += ["interrupts.int_master"]
193
194    def createInterruptController(self):
195        if buildEnv['TARGET_ISA'] == 'sparc':
196            self.interrupts = SparcInterrupts()
197        elif buildEnv['TARGET_ISA'] == 'alpha':
198            self.interrupts = AlphaInterrupts()
199        elif buildEnv['TARGET_ISA'] == 'x86':
200            _localApic = X86LocalApic(pio_addr=0x2000000000000000)
201            self.interrupts = _localApic
202        elif buildEnv['TARGET_ISA'] == 'mips':
203            self.interrupts = MipsInterrupts()
204        elif buildEnv['TARGET_ISA'] == 'arm':
205            self.interrupts = ArmInterrupts()
206        elif buildEnv['TARGET_ISA'] == 'power':
207            self.interrupts = PowerInterrupts()
208        else:
209            print "Don't know what Interrupt Controller to use for ISA %s" % \
210                buildEnv['TARGET_ISA']
211            sys.exit(1)
212
213    def connectCachedPorts(self, bus):
214        for p in self._cached_ports:
215            exec('self.%s = bus.slave' % p)
216
217    def connectUncachedPorts(self, bus):
218        for p in self._uncached_slave_ports:
219            exec('self.%s = bus.master' % p)
220        for p in self._uncached_master_ports:
221            exec('self.%s = bus.slave' % p)
222
223    def connectAllPorts(self, cached_bus, uncached_bus = None):
224        self.connectCachedPorts(cached_bus)
225        if not uncached_bus:
226            uncached_bus = cached_bus
227        self.connectUncachedPorts(uncached_bus)
228
229    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
230        self.icache = ic
231        self.dcache = dc
232        self.icache_port = ic.cpu_side
233        self.dcache_port = dc.cpu_side
234        self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
235        if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
236            if iwc and dwc:
237                self.itb_walker_cache = iwc
238                self.dtb_walker_cache = dwc
239                self.itb.walker.port = iwc.cpu_side
240                self.dtb.walker.port = dwc.cpu_side
241                self._cached_ports += ["itb_walker_cache.mem_side", \
242                                       "dtb_walker_cache.mem_side"]
243            else:
244                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
245
246            # Checker doesn't need its own tlb caches because it does
247            # functional accesses only
248            if self.checker != NULL:
249                self._cached_ports += ["checker.itb.walker.port", \
250                                       "checker.dtb.walker.port"]
251
252    def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
253        self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
254        # Override the default bus clock of 1 GHz and uses the CPU
255        # clock for the L1-to-L2 bus, and also set a width of 32 bytes
256        # (256-bits), which is four times that of the default bus.
257        self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
258        self.connectCachedPorts(self.toL2Bus)
259        self.l2cache = l2c
260        self.toL2Bus.master = self.l2cache.cpu_side
261        self._cached_ports = ['l2cache.mem_side']
262
263    def createThreads(self):
264        self.isa = [ isa_class() for i in xrange(self.numThreads) ]
265        if self.checker != NULL:
266            self.checker.createThreads()
267
268    def addCheckerCpu(self):
269        pass
270