BaseCPU.py revision 8863:50ce4deacda9 
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
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8# licensed hereunder.  You may use the software subject to the license
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11# modified or unmodified, in source code or in binary form.
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13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
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18# modification, are permitted provided that the following conditions are
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28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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39#
40# Authors: Nathan Binkert
41#          Rick Strong
42#          Andreas Hansson
43
44import sys
45
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import Bus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54
55default_tracer = ExeTracer()
56
57if buildEnv['TARGET_ISA'] == 'alpha':
58    from AlphaTLB import AlphaDTB, AlphaITB
59    from AlphaInterrupts import AlphaInterrupts
60elif buildEnv['TARGET_ISA'] == 'sparc':
61    from SparcTLB import SparcTLB
62    from SparcInterrupts import SparcInterrupts
63elif buildEnv['TARGET_ISA'] == 'x86':
64    from X86TLB import X86TLB
65    from X86LocalApic import X86LocalApic
66elif buildEnv['TARGET_ISA'] == 'mips':
67    from MipsTLB import MipsTLB
68    from MipsInterrupts import MipsInterrupts
69elif buildEnv['TARGET_ISA'] == 'arm':
70    from ArmTLB import ArmTLB
71    from ArmInterrupts import ArmInterrupts
72elif buildEnv['TARGET_ISA'] == 'power':
73    from PowerTLB import PowerTLB
74    from PowerInterrupts import PowerInterrupts
75
76class BaseCPU(MemObject):
77    type = 'BaseCPU'
78    abstract = True
79
80    system = Param.System(Parent.any, "system object")
81    cpu_id = Param.Int(-1, "CPU identifier")
82    numThreads = Param.Unsigned(1, "number of HW thread contexts")
83
84    function_trace = Param.Bool(False, "Enable function trace")
85    function_trace_start = Param.Tick(0, "Cycle to start function trace")
86
87    checker = Param.BaseCPU(NULL, "checker CPU")
88
89    do_checkpoint_insts = Param.Bool(True,
90        "enable checkpoint pseudo instructions")
91    do_statistics_insts = Param.Bool(True,
92        "enable statistics pseudo instructions")
93
94    profile = Param.Latency('0ns', "trace the kernel stack")
95    do_quiesce = Param.Bool(True, "enable quiesce instructions")
96
97    workload = VectorParam.Process([], "processes to run")
98
99    if buildEnv['TARGET_ISA'] == 'sparc':
100        dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
101        itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
102        interrupts = Param.SparcInterrupts(
103                NULL, "Interrupt Controller")
104    elif buildEnv['TARGET_ISA'] == 'alpha':
105        dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
106        itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
107        interrupts = Param.AlphaInterrupts(
108                NULL, "Interrupt Controller")
109    elif buildEnv['TARGET_ISA'] == 'x86':
110        dtb = Param.X86TLB(X86TLB(), "Data TLB")
111        itb = Param.X86TLB(X86TLB(), "Instruction TLB")
112        interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
113    elif buildEnv['TARGET_ISA'] == 'mips':
114        dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
115        itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
116        interrupts = Param.MipsInterrupts(
117                NULL, "Interrupt Controller")
118    elif buildEnv['TARGET_ISA'] == 'arm':
119        dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
120        itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
121        interrupts = Param.ArmInterrupts(
122                NULL, "Interrupt Controller")
123    elif buildEnv['TARGET_ISA'] == 'power':
124        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
125        dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
126        itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
127        interrupts = Param.PowerInterrupts(
128                NULL, "Interrupt Controller")
129    else:
130        print "Don't know what TLB to use for ISA %s" % \
131            buildEnv['TARGET_ISA']
132        sys.exit(1)
133
134    max_insts_all_threads = Param.Counter(0,
135        "terminate when all threads have reached this inst count")
136    max_insts_any_thread = Param.Counter(0,
137        "terminate when any thread reaches this inst count")
138    max_loads_all_threads = Param.Counter(0,
139        "terminate when all threads have reached this load count")
140    max_loads_any_thread = Param.Counter(0,
141        "terminate when any thread reaches this load count")
142    progress_interval = Param.Tick(0,
143        "interval to print out the progress message")
144
145    defer_registration = Param.Bool(False,
146        "defer registration with system (for sampling)")
147
148    clock = Param.Clock('1t', "clock speed")
149    phase = Param.Latency('0ns', "clock phase")
150
151    tracer = Param.InstTracer(default_tracer, "Instruction tracer")
152
153    icache_port = MasterPort("Instruction Port")
154    dcache_port = MasterPort("Data Port")
155    _cached_ports = ['icache_port', 'dcache_port']
156
157    if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
158        _cached_ports += ["itb.walker.port", "dtb.walker.port"]
159
160    _uncached_slave_ports = []
161    _uncached_master_ports = []
162    if buildEnv['TARGET_ISA'] == 'x86':
163        _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
164        _uncached_master_ports += ["interrupts.int_master"]
165
166    def createInterruptController(self):
167        if buildEnv['TARGET_ISA'] == 'sparc':
168            self.interrupts = SparcInterrupts()
169        elif buildEnv['TARGET_ISA'] == 'alpha':
170            self.interrupts = AlphaInterrupts()
171        elif buildEnv['TARGET_ISA'] == 'x86':
172            _localApic = X86LocalApic(pio_addr=0x2000000000000000)
173            self.interrupts = _localApic
174        elif buildEnv['TARGET_ISA'] == 'mips':
175            self.interrupts = MipsInterrupts()
176        elif buildEnv['TARGET_ISA'] == 'arm':
177            self.interrupts = ArmInterrupts()
178        elif buildEnv['TARGET_ISA'] == 'power':
179            self.interrupts = PowerInterrupts()
180        else:
181            print "Don't know what Interrupt Controller to use for ISA %s" % \
182                buildEnv['TARGET_ISA']
183            sys.exit(1)
184
185    def connectCachedPorts(self, bus):
186        for p in self._cached_ports:
187            exec('self.%s = bus.slave' % p)
188
189    def connectUncachedPorts(self, bus):
190        for p in self._uncached_slave_ports:
191            exec('self.%s = bus.master' % p)
192        for p in self._uncached_master_ports:
193            exec('self.%s = bus.slave' % p)
194
195    def connectAllPorts(self, cached_bus, uncached_bus = None):
196        self.connectCachedPorts(cached_bus)
197        if not uncached_bus:
198            uncached_bus = cached_bus
199        self.connectUncachedPorts(uncached_bus)
200
201    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
202        self.icache = ic
203        self.dcache = dc
204        self.icache_port = ic.cpu_side
205        self.dcache_port = dc.cpu_side
206        self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
207        if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
208            if iwc and dwc:
209                self.itb_walker_cache = iwc
210                self.dtb_walker_cache = dwc
211                self.itb.walker.port = iwc.cpu_side
212                self.dtb.walker.port = dwc.cpu_side
213                self._cached_ports += ["itb_walker_cache.mem_side", \
214                                       "dtb_walker_cache.mem_side"]
215            else:
216                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
217            # Checker doesn't need its own tlb caches because it does
218            # functional accesses only
219            if buildEnv['USE_CHECKER']:
220                self._cached_ports += ["checker.itb.walker.port", \
221                                       "checker.dtb.walker.port"]
222
223    def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
224        self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
225        self.toL2Bus = Bus()
226        self.connectCachedPorts(self.toL2Bus)
227        self.l2cache = l2c
228        self.toL2Bus.master = self.l2cache.cpu_side
229        self._cached_ports = ['l2cache.mem_side']
230