BaseCPU.py revision 8793:5f25086326ac
13101Sstever@eecs.umich.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 23101Sstever@eecs.umich.edu# Copyright (c) 2011 Regents of the University of California 33101Sstever@eecs.umich.edu# All rights reserved. 43101Sstever@eecs.umich.edu# 53101Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 63101Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 73101Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 83101Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 93101Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 103101Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 113101Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 123101Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 133101Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 143101Sstever@eecs.umich.edu# this software without specific prior written permission. 153101Sstever@eecs.umich.edu# 163101Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173101Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183101Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193101Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203101Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213101Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223101Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233101Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243101Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253101Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263101Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273101Sstever@eecs.umich.edu# 283101Sstever@eecs.umich.edu# Authors: Nathan Binkert 293101Sstever@eecs.umich.edu# Rick Strong 303101Sstever@eecs.umich.edu 313101Sstever@eecs.umich.eduimport sys 323101Sstever@eecs.umich.edu 333101Sstever@eecs.umich.edufrom m5.defines import buildEnv 343101Sstever@eecs.umich.edufrom m5.params import * 353101Sstever@eecs.umich.edufrom m5.proxy import * 363101Sstever@eecs.umich.edu 373101Sstever@eecs.umich.edufrom Bus import Bus 383101Sstever@eecs.umich.edufrom InstTracer import InstTracer 393101Sstever@eecs.umich.edufrom ExeTracer import ExeTracer 403101Sstever@eecs.umich.edufrom MemObject import MemObject 413101Sstever@eecs.umich.edu 423101Sstever@eecs.umich.edudefault_tracer = ExeTracer() 433101Sstever@eecs.umich.edu 443101Sstever@eecs.umich.eduif buildEnv['TARGET_ISA'] == 'alpha': 453101Sstever@eecs.umich.edu from AlphaTLB import AlphaDTB, AlphaITB 463101Sstever@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 473885Sbinkertn@umich.eduelif buildEnv['TARGET_ISA'] == 'sparc': 483885Sbinkertn@umich.edu from SparcTLB import SparcTLB 493885Sbinkertn@umich.edu from SparcInterrupts import SparcInterrupts 503885Sbinkertn@umich.eduelif buildEnv['TARGET_ISA'] == 'x86': 513885Sbinkertn@umich.edu from X86TLB import X86TLB 523885Sbinkertn@umich.edu from X86LocalApic import X86LocalApic 533101Sstever@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'mips': 543102Sstever@eecs.umich.edu from MipsTLB import MipsTLB 553101Sstever@eecs.umich.edu from MipsInterrupts import MipsInterrupts 563101Sstever@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'arm': 573101Sstever@eecs.umich.edu from ArmTLB import ArmTLB 583101Sstever@eecs.umich.edu from ArmInterrupts import ArmInterrupts 593101Sstever@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'power': 603101Sstever@eecs.umich.edu from PowerTLB import PowerTLB 613101Sstever@eecs.umich.edu from PowerInterrupts import PowerInterrupts 623101Sstever@eecs.umich.edu 633101Sstever@eecs.umich.educlass BaseCPU(MemObject): 643101Sstever@eecs.umich.edu type = 'BaseCPU' 653101Sstever@eecs.umich.edu abstract = True 663101Sstever@eecs.umich.edu 673101Sstever@eecs.umich.edu system = Param.System(Parent.any, "system object") 683101Sstever@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 693101Sstever@eecs.umich.edu numThreads = Param.Unsigned(1, "number of HW thread contexts") 703101Sstever@eecs.umich.edu 713101Sstever@eecs.umich.edu function_trace = Param.Bool(False, "Enable function trace") 723101Sstever@eecs.umich.edu function_trace_start = Param.Tick(0, "Cycle to start function trace") 733101Sstever@eecs.umich.edu 743101Sstever@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 753101Sstever@eecs.umich.edu 763101Sstever@eecs.umich.edu do_checkpoint_insts = Param.Bool(True, 773101Sstever@eecs.umich.edu "enable checkpoint pseudo instructions") 783101Sstever@eecs.umich.edu do_statistics_insts = Param.Bool(True, 793101Sstever@eecs.umich.edu "enable statistics pseudo instructions") 803101Sstever@eecs.umich.edu 813101Sstever@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 823101Sstever@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 833101Sstever@eecs.umich.edu 843101Sstever@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 853101Sstever@eecs.umich.edu 863101Sstever@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'sparc': 873101Sstever@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 883101Sstever@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 893101Sstever@eecs.umich.edu interrupts = Param.SparcInterrupts( 903101Sstever@eecs.umich.edu SparcInterrupts(), "Interrupt Controller") 913101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'alpha': 923101Sstever@eecs.umich.edu dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 933101Sstever@eecs.umich.edu itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 943101Sstever@eecs.umich.edu interrupts = Param.AlphaInterrupts( 953101Sstever@eecs.umich.edu AlphaInterrupts(), "Interrupt Controller") 963101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 973101Sstever@eecs.umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 983101Sstever@eecs.umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 993101Sstever@eecs.umich.edu _localApic = X86LocalApic(pio_addr=0x2000000000000000) 1003101Sstever@eecs.umich.edu interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller") 1013101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 1023101Sstever@eecs.umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1033101Sstever@eecs.umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1043101Sstever@eecs.umich.edu interrupts = Param.MipsInterrupts( 1053101Sstever@eecs.umich.edu MipsInterrupts(), "Interrupt Controller") 1063101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 1073101Sstever@eecs.umich.edu dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1083101Sstever@eecs.umich.edu itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1093102Sstever@eecs.umich.edu interrupts = Param.ArmInterrupts( 1103101Sstever@eecs.umich.edu ArmInterrupts(), "Interrupt Controller") 1113102Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'power': 1123101Sstever@eecs.umich.edu UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1133101Sstever@eecs.umich.edu dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1143101Sstever@eecs.umich.edu itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 1153102Sstever@eecs.umich.edu interrupts = Param.PowerInterrupts( 1163102Sstever@eecs.umich.edu PowerInterrupts(), "Interrupt Controller") 1173101Sstever@eecs.umich.edu else: 1183101Sstever@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 1193101Sstever@eecs.umich.edu buildEnv['TARGET_ISA'] 1203101Sstever@eecs.umich.edu sys.exit(1) 1213101Sstever@eecs.umich.edu 1223101Sstever@eecs.umich.edu max_insts_all_threads = Param.Counter(0, 1233101Sstever@eecs.umich.edu "terminate when all threads have reached this inst count") 1243101Sstever@eecs.umich.edu max_insts_any_thread = Param.Counter(0, 1253101Sstever@eecs.umich.edu "terminate when any thread reaches this inst count") 1263101Sstever@eecs.umich.edu max_loads_all_threads = Param.Counter(0, 1273101Sstever@eecs.umich.edu "terminate when all threads have reached this load count") 1283101Sstever@eecs.umich.edu max_loads_any_thread = Param.Counter(0, 1293101Sstever@eecs.umich.edu "terminate when any thread reaches this load count") 1303102Sstever@eecs.umich.edu progress_interval = Param.Tick(0, 1313101Sstever@eecs.umich.edu "interval to print out the progress message") 1323101Sstever@eecs.umich.edu 1333101Sstever@eecs.umich.edu defer_registration = Param.Bool(False, 1343101Sstever@eecs.umich.edu "defer registration with system (for sampling)") 1353101Sstever@eecs.umich.edu 1363101Sstever@eecs.umich.edu clock = Param.Clock('1t', "clock speed") 1373101Sstever@eecs.umich.edu phase = Param.Latency('0ns', "clock phase") 1383101Sstever@eecs.umich.edu 1393101Sstever@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 1403101Sstever@eecs.umich.edu 1413101Sstever@eecs.umich.edu _cached_ports = [] 1423101Sstever@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 1433101Sstever@eecs.umich.edu _cached_ports = ["itb.walker.port", "dtb.walker.port"] 1443101Sstever@eecs.umich.edu 1453101Sstever@eecs.umich.edu _uncached_ports = [] 1463101Sstever@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 1473101Sstever@eecs.umich.edu _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 1483101Sstever@eecs.umich.edu 1493101Sstever@eecs.umich.edu def connectCachedPorts(self, bus): 1503101Sstever@eecs.umich.edu for p in self._cached_ports: 1513101Sstever@eecs.umich.edu exec('self.%s = bus.port' % p) 1523101Sstever@eecs.umich.edu 1533101Sstever@eecs.umich.edu def connectUncachedPorts(self, bus): 1543101Sstever@eecs.umich.edu for p in self._uncached_ports: 1553101Sstever@eecs.umich.edu exec('self.%s = bus.port' % p) 1563101Sstever@eecs.umich.edu 1573101Sstever@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 1583101Sstever@eecs.umich.edu self.connectCachedPorts(cached_bus) 1593101Sstever@eecs.umich.edu if not uncached_bus: 1603101Sstever@eecs.umich.edu uncached_bus = cached_bus 1613101Sstever@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 1623101Sstever@eecs.umich.edu 1633101Sstever@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 1643101Sstever@eecs.umich.edu assert(len(self._cached_ports) < 7) 1653101Sstever@eecs.umich.edu self.icache = ic 1663101Sstever@eecs.umich.edu self.dcache = dc 1673101Sstever@eecs.umich.edu self.icache_port = ic.cpu_side 1683101Sstever@eecs.umich.edu self.dcache_port = dc.cpu_side 1693101Sstever@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 1703101Sstever@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86' and iwc and dwc: 1713101Sstever@eecs.umich.edu self.itb_walker_cache = iwc 1723101Sstever@eecs.umich.edu self.dtb_walker_cache = dwc 1733101Sstever@eecs.umich.edu self.itb.walker.port = iwc.cpu_side 1743101Sstever@eecs.umich.edu self.dtb.walker.port = dwc.cpu_side 1753101Sstever@eecs.umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 1763101Sstever@eecs.umich.edu "dtb_walker_cache.mem_side"] 1773101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 1783101Sstever@eecs.umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 1793101Sstever@eecs.umich.edu 1803101Sstever@eecs.umich.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 1813101Sstever@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 1823101Sstever@eecs.umich.edu self.toL2Bus = Bus() 1833101Sstever@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 1843101Sstever@eecs.umich.edu self.l2cache = l2c 1853101Sstever@eecs.umich.edu self.l2cache.cpu_side = self.toL2Bus.port 1863101Sstever@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 1873101Sstever@eecs.umich.edu