BaseCPU.py revision 8707:489489c67fd9
111527Sdavid.guillen@arm.com# Copyright (c) 2005-2008 The Regents of The University of Michigan 211527Sdavid.guillen@arm.com# Copyright (c) 2011 Regents of the University of California 311527Sdavid.guillen@arm.com# All rights reserved. 411527Sdavid.guillen@arm.com# 511527Sdavid.guillen@arm.com# Redistribution and use in source and binary forms, with or without 611527Sdavid.guillen@arm.com# modification, are permitted provided that the following conditions are 711527Sdavid.guillen@arm.com# met: redistributions of source code must retain the above copyright 811527Sdavid.guillen@arm.com# notice, this list of conditions and the following disclaimer; 911527Sdavid.guillen@arm.com# redistributions in binary form must reproduce the above copyright 1011527Sdavid.guillen@arm.com# notice, this list of conditions and the following disclaimer in the 1111527Sdavid.guillen@arm.com# documentation and/or other materials provided with the distribution; 1211527Sdavid.guillen@arm.com# neither the name of the copyright holders nor the names of its 1311527Sdavid.guillen@arm.com# contributors may be used to endorse or promote products derived from 1411527Sdavid.guillen@arm.com# this software without specific prior written permission. 1511527Sdavid.guillen@arm.com# 1611527Sdavid.guillen@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711527Sdavid.guillen@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811527Sdavid.guillen@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911527Sdavid.guillen@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011527Sdavid.guillen@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111527Sdavid.guillen@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211527Sdavid.guillen@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311527Sdavid.guillen@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411527Sdavid.guillen@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511527Sdavid.guillen@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611527Sdavid.guillen@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711527Sdavid.guillen@arm.com# 2811527Sdavid.guillen@arm.com# Authors: Nathan Binkert 2911527Sdavid.guillen@arm.com# Rick Strong 3011527Sdavid.guillen@arm.com 3111527Sdavid.guillen@arm.comimport sys 3211527Sdavid.guillen@arm.com 3311527Sdavid.guillen@arm.comfrom m5.defines import buildEnv 3411527Sdavid.guillen@arm.comfrom m5.params import * 3511527Sdavid.guillen@arm.comfrom m5.proxy import * 3611527Sdavid.guillen@arm.com 3711527Sdavid.guillen@arm.comfrom Bus import Bus 3811527Sdavid.guillen@arm.comfrom InstTracer import InstTracer 3911527Sdavid.guillen@arm.comfrom ExeTracer import ExeTracer 4011527Sdavid.guillen@arm.comfrom MemObject import MemObject 4111527Sdavid.guillen@arm.com 4211527Sdavid.guillen@arm.comdefault_tracer = ExeTracer() 4311527Sdavid.guillen@arm.com 4411527Sdavid.guillen@arm.comif buildEnv['TARGET_ISA'] == 'alpha': 4511527Sdavid.guillen@arm.com from AlphaTLB import AlphaDTB, AlphaITB 4611527Sdavid.guillen@arm.com if buildEnv['FULL_SYSTEM']: 4711527Sdavid.guillen@arm.com from AlphaInterrupts import AlphaInterrupts 4811800Sbrandon.potter@amd.comelif buildEnv['TARGET_ISA'] == 'sparc': 4911800Sbrandon.potter@amd.com from SparcTLB import SparcTLB 5011800Sbrandon.potter@amd.com if buildEnv['FULL_SYSTEM']: 5111800Sbrandon.potter@amd.com from SparcInterrupts import SparcInterrupts 5211527Sdavid.guillen@arm.comelif buildEnv['TARGET_ISA'] == 'x86': 5311527Sdavid.guillen@arm.com from X86TLB import X86TLB 5411527Sdavid.guillen@arm.com if buildEnv['FULL_SYSTEM']: 5511527Sdavid.guillen@arm.com from X86LocalApic import X86LocalApic 5611527Sdavid.guillen@arm.comelif buildEnv['TARGET_ISA'] == 'mips': 5711527Sdavid.guillen@arm.com from MipsTLB import MipsTLB 5811527Sdavid.guillen@arm.com if buildEnv['FULL_SYSTEM']: 5911527Sdavid.guillen@arm.com from MipsInterrupts import MipsInterrupts 6011527Sdavid.guillen@arm.comelif buildEnv['TARGET_ISA'] == 'arm': 6111527Sdavid.guillen@arm.com from ArmTLB import ArmTLB 6211527Sdavid.guillen@arm.com if buildEnv['FULL_SYSTEM']: 6311527Sdavid.guillen@arm.com from ArmInterrupts import ArmInterrupts 6411527Sdavid.guillen@arm.comelif buildEnv['TARGET_ISA'] == 'power': 6511527Sdavid.guillen@arm.com from PowerTLB import PowerTLB 6611527Sdavid.guillen@arm.com if buildEnv['FULL_SYSTEM']: 6711527Sdavid.guillen@arm.com from PowerInterrupts import PowerInterrupts 6811527Sdavid.guillen@arm.com 6911527Sdavid.guillen@arm.comclass BaseCPU(MemObject): 7011527Sdavid.guillen@arm.com type = 'BaseCPU' 7111527Sdavid.guillen@arm.com abstract = True 7211527Sdavid.guillen@arm.com 7311527Sdavid.guillen@arm.com system = Param.System(Parent.any, "system object") 7411527Sdavid.guillen@arm.com cpu_id = Param.Int(-1, "CPU identifier") 7511527Sdavid.guillen@arm.com numThreads = Param.Unsigned(1, "number of HW thread contexts") 7611527Sdavid.guillen@arm.com 7711527Sdavid.guillen@arm.com function_trace = Param.Bool(False, "Enable function trace") 7811527Sdavid.guillen@arm.com function_trace_start = Param.Tick(0, "Cycle to start function trace") 7911527Sdavid.guillen@arm.com 8011527Sdavid.guillen@arm.com checker = Param.BaseCPU(NULL, "checker CPU") 8111527Sdavid.guillen@arm.com 8211527Sdavid.guillen@arm.com do_checkpoint_insts = Param.Bool(True, 8311527Sdavid.guillen@arm.com "enable checkpoint pseudo instructions") 8411527Sdavid.guillen@arm.com do_statistics_insts = Param.Bool(True, 8511527Sdavid.guillen@arm.com "enable statistics pseudo instructions") 8611527Sdavid.guillen@arm.com 8711527Sdavid.guillen@arm.com if buildEnv['FULL_SYSTEM']: 8811527Sdavid.guillen@arm.com profile = Param.Latency('0ns', "trace the kernel stack") 8911527Sdavid.guillen@arm.com do_quiesce = Param.Bool(True, "enable quiesce instructions") 9011527Sdavid.guillen@arm.com else: 9111527Sdavid.guillen@arm.com workload = VectorParam.Process("processes to run") 9211527Sdavid.guillen@arm.com 9311527Sdavid.guillen@arm.com if buildEnv['TARGET_ISA'] == 'sparc': 9411527Sdavid.guillen@arm.com dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 9511527Sdavid.guillen@arm.com itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 9611527Sdavid.guillen@arm.com if buildEnv['FULL_SYSTEM']: 9711527Sdavid.guillen@arm.com interrupts = Param.SparcInterrupts( 9811527Sdavid.guillen@arm.com SparcInterrupts(), "Interrupt Controller") 9911527Sdavid.guillen@arm.com elif buildEnv['TARGET_ISA'] == 'alpha': 10011527Sdavid.guillen@arm.com dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 10111527Sdavid.guillen@arm.com itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 10211527Sdavid.guillen@arm.com if buildEnv['FULL_SYSTEM']: 10311527Sdavid.guillen@arm.com interrupts = Param.AlphaInterrupts( 10411527Sdavid.guillen@arm.com AlphaInterrupts(), "Interrupt Controller") 10511527Sdavid.guillen@arm.com elif buildEnv['TARGET_ISA'] == 'x86': 10611527Sdavid.guillen@arm.com dtb = Param.X86TLB(X86TLB(), "Data TLB") 10711527Sdavid.guillen@arm.com itb = Param.X86TLB(X86TLB(), "Instruction TLB") 10811527Sdavid.guillen@arm.com if buildEnv['FULL_SYSTEM']: 10911527Sdavid.guillen@arm.com _localApic = X86LocalApic(pio_addr=0x2000000000000000) 11011527Sdavid.guillen@arm.com interrupts = \ 11111527Sdavid.guillen@arm.com Param.X86LocalApic(_localApic, "Interrupt Controller") 11211527Sdavid.guillen@arm.com elif buildEnv['TARGET_ISA'] == 'mips': 11311527Sdavid.guillen@arm.com dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 114 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 115 if buildEnv['FULL_SYSTEM']: 116 interrupts = Param.MipsInterrupts( 117 MipsInterrupts(), "Interrupt Controller") 118 elif buildEnv['TARGET_ISA'] == 'arm': 119 dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 120 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 121 if buildEnv['FULL_SYSTEM']: 122 interrupts = Param.ArmInterrupts( 123 ArmInterrupts(), "Interrupt Controller") 124 elif buildEnv['TARGET_ISA'] == 'power': 125 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 126 dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 127 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 128 if buildEnv['FULL_SYSTEM']: 129 interrupts = Param.PowerInterrupts( 130 PowerInterrupts(), "Interrupt Controller") 131 else: 132 print "Don't know what TLB to use for ISA %s" % \ 133 buildEnv['TARGET_ISA'] 134 sys.exit(1) 135 136 max_insts_all_threads = Param.Counter(0, 137 "terminate when all threads have reached this inst count") 138 max_insts_any_thread = Param.Counter(0, 139 "terminate when any thread reaches this inst count") 140 max_loads_all_threads = Param.Counter(0, 141 "terminate when all threads have reached this load count") 142 max_loads_any_thread = Param.Counter(0, 143 "terminate when any thread reaches this load count") 144 progress_interval = Param.Tick(0, 145 "interval to print out the progress message") 146 147 defer_registration = Param.Bool(False, 148 "defer registration with system (for sampling)") 149 150 clock = Param.Clock('1t', "clock speed") 151 phase = Param.Latency('0ns', "clock phase") 152 153 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 154 155 icache_port = Port("Instruction Port") 156 dcache_port = Port("Data Port") 157 _cached_ports = ['icache_port', 'dcache_port'] 158 159 if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']: 160 _cached_ports += ["itb.walker.port", "dtb.walker.port"] 161 162 _uncached_ports = [] 163 if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: 164 _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 165 166 def connectCachedPorts(self, bus): 167 for p in self._cached_ports: 168 exec('self.%s = bus.port' % p) 169 170 def connectUncachedPorts(self, bus): 171 for p in self._uncached_ports: 172 exec('self.%s = bus.port' % p) 173 174 def connectAllPorts(self, cached_bus, uncached_bus = None): 175 self.connectCachedPorts(cached_bus) 176 if not uncached_bus: 177 uncached_bus = cached_bus 178 self.connectUncachedPorts(uncached_bus) 179 180 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 181 assert(len(self._cached_ports) < 7) 182 self.icache = ic 183 self.dcache = dc 184 self.icache_port = ic.cpu_side 185 self.dcache_port = dc.cpu_side 186 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 187 if buildEnv['FULL_SYSTEM']: 188 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 189 if iwc and dwc: 190 self.itb_walker_cache = iwc 191 self.dtb_walker_cache = dwc 192 self.itb.walker.port = iwc.cpu_side 193 self.dtb.walker.port = dwc.cpu_side 194 self._cached_ports += ["itb_walker_cache.mem_side", \ 195 "dtb_walker_cache.mem_side"] 196 else: 197 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 198 199 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 200 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 201 self.toL2Bus = Bus() 202 self.connectCachedPorts(self.toL2Bus) 203 self.l2cache = l2c 204 self.l2cache.cpu_side = self.toL2Bus.port 205 self._cached_ports = ['l2cache.mem_side'] 206