BaseCPU.py revision 5648:e8abda6e0980
14486Sbinkertn@umich.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 24486Sbinkertn@umich.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 54486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 64486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 74486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 84486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 114486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 124486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 134486Sbinkertn@umich.edu# this software without specific prior written permission. 144486Sbinkertn@umich.edu# 154486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# Authors: Nathan Binkert 284486Sbinkertn@umich.edu 296654Snate@binkert.orgfrom MemObject import MemObject 303102SN/Afrom m5.params import * 313102SN/Afrom m5.proxy import * 321681SN/Afrom m5 import build_env 333223SN/Afrom Bus import Bus 348887Sgeoffrey.blake@arm.comfrom InstTracer import InstTracer 354486Sbinkertn@umich.edufrom ExeTracer import ExeTracer 362817SN/Aimport sys 372817SN/A 382932SN/Adefault_tracer = ExeTracer() 391681SN/A 404597Sbinkertn@umich.eduif build_env['TARGET_ISA'] == 'alpha': 411681SN/A from AlphaTLB import AlphaDTB, AlphaITB 429184Sandreas.hansson@arm.com if build_env['FULL_SYSTEM']: 439184Sandreas.hansson@arm.com from AlphaInterrupts import AlphaInterrupts 449184Sandreas.hansson@arm.comelif build_env['TARGET_ISA'] == 'sparc': 459184Sandreas.hansson@arm.com from SparcTLB import SparcDTB, SparcITB 469184Sandreas.hansson@arm.com if build_env['FULL_SYSTEM']: 472932SN/A from SparcInterrupts import SparcInterrupts 482932SN/Aelif build_env['TARGET_ISA'] == 'x86': 499184Sandreas.hansson@arm.com from X86TLB import X86DTB, X86ITB 509184Sandreas.hansson@arm.com if build_env['FULL_SYSTEM']: 519184Sandreas.hansson@arm.com from X86LocalApic import X86LocalApic 529184Sandreas.hansson@arm.comelif build_env['TARGET_ISA'] == 'mips': 539184Sandreas.hansson@arm.com from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB 542932SN/A if build_env['FULL_SYSTEM']: 551681SN/A from MipsInterrupts import MipsInterrupts 569184Sandreas.hansson@arm.comelif build_env['TARGET_ISA'] == 'arm': 579184Sandreas.hansson@arm.com from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB 589184Sandreas.hansson@arm.com if build_env['FULL_SYSTEM']: 599184Sandreas.hansson@arm.com from ArmInterrupts import ArmInterrupts 602932SN/A 611681SN/Aclass BaseCPU(MemObject): 629184Sandreas.hansson@arm.com type = 'BaseCPU' 632932SN/A abstract = True 649184Sandreas.hansson@arm.com 652932SN/A system = Param.System(Parent.any, "system object") 669184Sandreas.hansson@arm.com cpu_id = Param.Int("CPU identifier") 672932SN/A numThreads = Param.Unsigned(1, "number of HW thread contexts") 682932SN/A 692932SN/A function_trace = Param.Bool(False, "Enable function trace") 702932SN/A function_trace_start = Param.Tick(0, "Cycle to start function trace") 712932SN/A 723223SN/A checker = Param.BaseCPU("checker CPU") 732932SN/A 749184Sandreas.hansson@arm.com if build_env['FULL_SYSTEM']: 751681SN/A profile = Param.Latency('0ns', "trace the kernel stack") 769184Sandreas.hansson@arm.com do_quiesce = Param.Bool(True, "enable quiesce instructions") 772932SN/A do_checkpoint_insts = Param.Bool(True, 782932SN/A "enable checkpoint pseudo instructions") 799184Sandreas.hansson@arm.com do_statistics_insts = Param.Bool(True, 809184Sandreas.hansson@arm.com "enable statistics pseudo instructions") 811681SN/A else: 822932SN/A workload = VectorParam.Process("processes to run") 832932SN/A 841681SN/A if build_env['TARGET_ISA'] == 'sparc': 852932SN/A dtb = Param.SparcDTB(SparcDTB(), "Data TLB") 862932SN/A itb = Param.SparcITB(SparcITB(), "Instruction TLB") 872932SN/A if build_env['FULL_SYSTEM']: 882932SN/A interrupts = Param.SparcInterrupts( 892932SN/A SparcInterrupts(), "Interrupt Controller") 902932SN/A elif build_env['TARGET_ISA'] == 'alpha': 912932SN/A dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") 923223SN/A itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") 932932SN/A if build_env['FULL_SYSTEM']: 942932SN/A interrupts = Param.AlphaInterrupts( 951681SN/A AlphaInterrupts(), "Interrupt Controller") 962932SN/A elif build_env['TARGET_ISA'] == 'x86': 972932SN/A dtb = Param.X86DTB(X86DTB(), "Data TLB") 982873SN/A itb = Param.X86ITB(X86ITB(), "Instruction TLB") 992932SN/A if build_env['FULL_SYSTEM']: 1001681SN/A _localApic = X86LocalApic(pio_addr=0xa000000000000000) 1012932SN/A interrupts = \ 1022932SN/A Param.X86LocalApic(_localApic, "Interrupt Controller") 1038199SAli.Saidi@ARM.com elif build_env['TARGET_ISA'] == 'mips': 1048199SAli.Saidi@ARM.com UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1058199SAli.Saidi@ARM.com dtb = Param.MipsDTB(MipsDTB(), "Data TLB") 1068519SAli.Saidi@ARM.com itb = Param.MipsITB(MipsITB(), "Instruction TLB") 1078519SAli.Saidi@ARM.com tlb = Param.MipsUTB(MipsUTB(), "Unified TLB") 1082932SN/A if build_env['FULL_SYSTEM']: 1092932SN/A interrupts = Param.MipsInterrupts( 1101681SN/A MipsInterrupts(), "Interrupt Controller") 1112932SN/A elif build_env['TARGET_ISA'] == 'arm': 1121681SN/A UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1132932SN/A dtb = Param.ArmDTB(ArmDTB(), "Data TLB") 1142932SN/A itb = Param.ArmITB(ArmITB(), "Instruction TLB") 1152932SN/A tlb = Param.ArmUTB(ArmUTB(), "Unified TLB") 1162932SN/A if build_env['FULL_SYSTEM']: 1172932SN/A interrupts = Param.ArmInterrupts( 1181681SN/A ArmInterrupts(), "Interrupt Controller") 1192932SN/A else: 1201681SN/A print "Don't know what TLB to use for ISA %s" % \ 1214597Sbinkertn@umich.edu build_env['TARGET_ISA'] 1224597Sbinkertn@umich.edu sys.exit(1) 1234597Sbinkertn@umich.edu 1244597Sbinkertn@umich.edu max_insts_all_threads = Param.Counter(0, 1254597Sbinkertn@umich.edu "terminate when all threads have reached this inst count") 1264597Sbinkertn@umich.edu max_insts_any_thread = Param.Counter(0, 1274597Sbinkertn@umich.edu "terminate when any thread reaches this inst count") 1284597Sbinkertn@umich.edu max_loads_all_threads = Param.Counter(0, 1294597Sbinkertn@umich.edu "terminate when all threads have reached this load count") 1304303SN/A max_loads_any_thread = Param.Counter(0, 1318727Snilay@cs.wisc.edu "terminate when any thread reaches this load count") 1328727Snilay@cs.wisc.edu progress_interval = Param.Tick(0, 1338887Sgeoffrey.blake@arm.com "interval to print out the progress message") 1348887Sgeoffrey.blake@arm.com 1358887Sgeoffrey.blake@arm.com defer_registration = Param.Bool(False, 1368887Sgeoffrey.blake@arm.com "defer registration with system (for sampling)") 1378887Sgeoffrey.blake@arm.com 1388887Sgeoffrey.blake@arm.com clock = Param.Clock('1t', "clock speed") 1398887Sgeoffrey.blake@arm.com phase = Param.Latency('0ns', "clock phase") 1408887Sgeoffrey.blake@arm.com 1418887Sgeoffrey.blake@arm.com tracer = Param.InstTracer(default_tracer, "Instruction tracer") 1428887Sgeoffrey.blake@arm.com 1438887Sgeoffrey.blake@arm.com _mem_ports = [] 1449132Satgutier@umich.edu if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: 1458887Sgeoffrey.blake@arm.com _mem_ports = ["itb.walker.port", 1468887Sgeoffrey.blake@arm.com "dtb.walker.port", 1478887Sgeoffrey.blake@arm.com "interrupts.pio"] 1488887Sgeoffrey.blake@arm.com 149 def connectMemPorts(self, bus): 150 for p in self._mem_ports: 151 if p != 'physmem_port': 152 exec('self.%s = bus.port' % p) 153 154 def addPrivateSplitL1Caches(self, ic, dc): 155 assert(len(self._mem_ports) < 6) 156 self.icache = ic 157 self.dcache = dc 158 self.icache_port = ic.cpu_side 159 self.dcache_port = dc.cpu_side 160 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 161 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: 162 self._mem_ports += ["itb.walker_port", "dtb.walker_port"] 163 164 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 165 self.addPrivateSplitL1Caches(ic, dc) 166 self.toL2Bus = Bus() 167 self.connectMemPorts(self.toL2Bus) 168 self.l2cache = l2c 169 self.l2cache.cpu_side = self.toL2Bus.port 170 self._mem_ports = ['l2cache.mem_side'] 171 172 if build_env['TARGET_ISA'] == 'mips': 173 CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") 174 CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") 175 CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") 176 CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") 177 CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") 178 CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") 179 CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company") 180 CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register") 181 CP0_Config_BE = Param.Unsigned(0,"Big Endian?") 182 CP0_Config_AT = Param.Unsigned(0,"No Description") 183 CP0_Config_AR = Param.Unsigned(0,"No Description") 184 CP0_Config_MT = Param.Unsigned(0,"No Description") 185 CP0_Config_VI = Param.Unsigned(0,"No Description") 186 CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?") 187 CP0_Config1_MMU = Param.Unsigned(0,"MMU Type") 188 CP0_Config1_IS = Param.Unsigned(0,"No Description") 189 CP0_Config1_IL = Param.Unsigned(0,"No Description") 190 CP0_Config1_IA = Param.Unsigned(0,"No Description") 191 CP0_Config1_DS = Param.Unsigned(0,"No Description") 192 CP0_Config1_DL = Param.Unsigned(0,"No Description") 193 CP0_Config1_DA = Param.Unsigned(0,"No Description") 194 CP0_Config1_C2 = Param.Bool(False,"No Description") 195 CP0_Config1_MD = Param.Bool(False,"No Description") 196 CP0_Config1_PC = Param.Bool(False,"No Description") 197 CP0_Config1_WR = Param.Bool(False,"No Description") 198 CP0_Config1_CA = Param.Bool(False,"No Description") 199 CP0_Config1_EP = Param.Bool(False,"No Description") 200 CP0_Config1_FP = Param.Bool(False,"FPU Implemented?") 201 CP0_Config2_M = Param.Bool(False,"Config3 Implemented?") 202 CP0_Config2_TU = Param.Unsigned(0,"No Description") 203 CP0_Config2_TS = Param.Unsigned(0,"No Description") 204 CP0_Config2_TL = Param.Unsigned(0,"No Description") 205 CP0_Config2_TA = Param.Unsigned(0,"No Description") 206 CP0_Config2_SU = Param.Unsigned(0,"No Description") 207 CP0_Config2_SS = Param.Unsigned(0,"No Description") 208 CP0_Config2_SL = Param.Unsigned(0,"No Description") 209 CP0_Config2_SA = Param.Unsigned(0,"No Description") 210 CP0_Config3_M = Param.Bool(False,"Config4 Implemented?") 211 CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?") 212 CP0_Config3_LPA = Param.Bool(False,"No Description") 213 CP0_Config3_VEIC = Param.Bool(False,"No Description") 214 CP0_Config3_VInt = Param.Bool(False,"No Description") 215 CP0_Config3_SP = Param.Bool(False,"No Description") 216 CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?") 217 CP0_Config3_SM = Param.Bool(False,"No Description") 218 CP0_Config3_TL = Param.Bool(False,"No Description") 219 CP0_WatchHi_M = Param.Bool(False,"No Description") 220 CP0_PerfCtr_M = Param.Bool(False,"No Description") 221 CP0_PerfCtr_W = Param.Bool(False,"No Description") 222 CP0_PRId = Param.Unsigned(0,"CP0 Status Register") 223 CP0_Config = Param.Unsigned(0,"CP0 Config Register") 224 CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register") 225 CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register") 226 CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register") 227