BaseCPU.py revision 5529 
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nathan Binkert
28
29from MemObject import MemObject
30from m5.params import *
31from m5.proxy import *
32from m5 import build_env
33from Bus import Bus
34from InstTracer import InstTracer
35from ExeTracer import ExeTracer
36import sys
37
38default_tracer = ExeTracer()
39
40if build_env['TARGET_ISA'] == 'alpha':
41    from AlphaTLB import AlphaDTB, AlphaITB
42elif build_env['TARGET_ISA'] == 'sparc':
43    from SparcTLB import SparcDTB, SparcITB
44elif build_env['TARGET_ISA'] == 'x86':
45    from X86TLB import X86DTB, X86ITB
46elif build_env['TARGET_ISA'] == 'mips':
47    from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
48elif build_env['TARGET_ISA'] == 'arm':
49    from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
50
51class BaseCPU(MemObject):
52    type = 'BaseCPU'
53    abstract = True
54
55    system = Param.System(Parent.any, "system object")
56    cpu_id = Param.Int("CPU identifier")
57    numThreads = Param.Unsigned(1, "number of HW thread contexts")
58
59    function_trace = Param.Bool(False, "Enable function trace")
60    function_trace_start = Param.Tick(0, "Cycle to start function trace")
61
62    checker = Param.BaseCPU("checker CPU")
63
64    if build_env['FULL_SYSTEM']:
65        profile = Param.Latency('0ns', "trace the kernel stack")
66        do_quiesce = Param.Bool(True, "enable quiesce instructions")
67        do_checkpoint_insts = Param.Bool(True,
68            "enable checkpoint pseudo instructions")
69        do_statistics_insts = Param.Bool(True,
70            "enable statistics pseudo instructions")
71    else:
72        workload = VectorParam.Process("processes to run")
73
74    if build_env['TARGET_ISA'] == 'sparc':
75        dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
76        itb = Param.SparcITB(SparcITB(), "Instruction TLB")
77    elif build_env['TARGET_ISA'] == 'alpha':
78        dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
79        itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
80    elif build_env['TARGET_ISA'] == 'x86':
81        dtb = Param.X86DTB(X86DTB(), "Data TLB")
82        itb = Param.X86ITB(X86ITB(), "Instruction TLB")
83    elif build_env['TARGET_ISA'] == 'mips':
84        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
85        dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
86        itb = Param.MipsITB(MipsITB(), "Instruction TLB")
87        tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
88    elif build_env['TARGET_ISA'] == 'arm':
89        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
90        dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
91        itb = Param.ArmITB(ArmITB(), "Instruction TLB")
92        tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")
93    else:
94        print "Don't know what TLB to use for ISA %s" % \
95            build_env['TARGET_ISA']
96        sys.exit(1)
97
98    max_insts_all_threads = Param.Counter(0,
99        "terminate when all threads have reached this inst count")
100    max_insts_any_thread = Param.Counter(0,
101        "terminate when any thread reaches this inst count")
102    max_loads_all_threads = Param.Counter(0,
103        "terminate when all threads have reached this load count")
104    max_loads_any_thread = Param.Counter(0,
105        "terminate when any thread reaches this load count")
106    progress_interval = Param.Tick(0,
107        "interval to print out the progress message")
108
109    defer_registration = Param.Bool(False,
110        "defer registration with system (for sampling)")
111
112    clock = Param.Clock('1t', "clock speed")
113    phase = Param.Latency('0ns', "clock phase")
114
115    tracer = Param.InstTracer(default_tracer, "Instruction tracer")
116
117    _mem_ports = []
118    if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
119        _mem_ports = ["itb.walker.port", "dtb.walker.port"]
120
121    def connectMemPorts(self, bus):
122        for p in self._mem_ports:
123            if p != 'physmem_port':
124                exec('self.%s = bus.port' % p)
125
126    def addPrivateSplitL1Caches(self, ic, dc):
127        assert(len(self._mem_ports) < 6)
128        self.icache = ic
129        self.dcache = dc
130        self.icache_port = ic.cpu_side
131        self.dcache_port = dc.cpu_side
132        self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
133        if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
134            self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
135
136    def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
137        self.addPrivateSplitL1Caches(ic, dc)
138        self.toL2Bus = Bus()
139        self.connectMemPorts(self.toL2Bus)
140        self.l2cache = l2c
141        self.l2cache.cpu_side = self.toL2Bus.port
142        self._mem_ports = ['l2cache.mem_side']
143
144    if build_env['TARGET_ISA'] == 'mips':
145        CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
146        CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
147        CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
148        CP0_EBase_CPUNum = Param.Unsigned(0,"No Description")
149        CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register")
150        CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register")
151        CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company")
152        CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register")
153        CP0_Config_BE = Param.Unsigned(0,"Big Endian?")
154        CP0_Config_AT = Param.Unsigned(0,"No Description")
155        CP0_Config_AR = Param.Unsigned(0,"No Description")
156        CP0_Config_MT = Param.Unsigned(0,"No Description")
157        CP0_Config_VI = Param.Unsigned(0,"No Description")
158        CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?")
159        CP0_Config1_MMU = Param.Unsigned(0,"MMU Type")
160        CP0_Config1_IS = Param.Unsigned(0,"No Description")
161        CP0_Config1_IL = Param.Unsigned(0,"No Description")
162        CP0_Config1_IA = Param.Unsigned(0,"No Description")
163        CP0_Config1_DS = Param.Unsigned(0,"No Description")
164        CP0_Config1_DL = Param.Unsigned(0,"No Description")
165        CP0_Config1_DA = Param.Unsigned(0,"No Description")
166        CP0_Config1_C2 = Param.Bool(False,"No Description")
167        CP0_Config1_MD = Param.Bool(False,"No Description")
168        CP0_Config1_PC = Param.Bool(False,"No Description")
169        CP0_Config1_WR = Param.Bool(False,"No Description")
170        CP0_Config1_CA = Param.Bool(False,"No Description")
171        CP0_Config1_EP = Param.Bool(False,"No Description")
172        CP0_Config1_FP = Param.Bool(False,"FPU Implemented?")
173        CP0_Config2_M = Param.Bool(False,"Config3 Implemented?")
174        CP0_Config2_TU = Param.Unsigned(0,"No Description")
175        CP0_Config2_TS = Param.Unsigned(0,"No Description")
176        CP0_Config2_TL = Param.Unsigned(0,"No Description")
177        CP0_Config2_TA = Param.Unsigned(0,"No Description")
178        CP0_Config2_SU = Param.Unsigned(0,"No Description")
179        CP0_Config2_SS = Param.Unsigned(0,"No Description")
180        CP0_Config2_SL = Param.Unsigned(0,"No Description")
181        CP0_Config2_SA = Param.Unsigned(0,"No Description")
182        CP0_Config3_M = Param.Bool(False,"Config4 Implemented?")
183        CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?")
184        CP0_Config3_LPA = Param.Bool(False,"No Description")
185        CP0_Config3_VEIC = Param.Bool(False,"No Description")
186        CP0_Config3_VInt = Param.Bool(False,"No Description")
187        CP0_Config3_SP = Param.Bool(False,"No Description")
188        CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?")
189        CP0_Config3_SM = Param.Bool(False,"No Description")
190        CP0_Config3_TL = Param.Bool(False,"No Description")
191        CP0_WatchHi_M = Param.Bool(False,"No Description")
192        CP0_PerfCtr_M = Param.Bool(False,"No Description")
193        CP0_PerfCtr_W = Param.Bool(False,"No Description")
194        CP0_PRId = Param.Unsigned(0,"CP0 Status Register")
195        CP0_Config = Param.Unsigned(0,"CP0 Config Register")
196        CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register")
197        CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register")
198        CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register")
199