BaseCPU.py revision 5245:d94bb8af9f76
1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 29from m5.SimObject import SimObject 30from m5.params import * 31from m5.proxy import * 32from m5 import build_env 33from Bus import Bus 34from InstTracer import InstTracer 35from ExeTracer import ExeTracer 36import sys 37 38default_tracer = ExeTracer() 39 40if build_env['TARGET_ISA'] == 'alpha': 41 from AlphaTLB import AlphaDTB, AlphaITB 42elif build_env['TARGET_ISA'] == 'sparc': 43 from SparcTLB import SparcDTB, SparcITB 44elif build_env['TARGET_ISA'] == 'x86': 45 from X86TLB import X86DTB, X86ITB 46elif build_env['TARGET_ISA'] == 'mips': 47 from MipsTLB import MipsDTB, MipsITB 48 49class BaseCPU(SimObject): 50 type = 'BaseCPU' 51 abstract = True 52 53 system = Param.System(Parent.any, "system object") 54 cpu_id = Param.Int("CPU identifier") 55 56 if build_env['FULL_SYSTEM']: 57 do_quiesce = Param.Bool(True, "enable quiesce instructions") 58 do_checkpoint_insts = Param.Bool(True, 59 "enable checkpoint pseudo instructions") 60 do_statistics_insts = Param.Bool(True, 61 "enable statistics pseudo instructions") 62 else: 63 workload = VectorParam.Process("processes to run") 64 65 if build_env['TARGET_ISA'] == 'sparc': 66 dtb = Param.SparcDTB(SparcDTB(), "Data TLB") 67 itb = Param.SparcITB(SparcITB(), "Instruction TLB") 68 elif build_env['TARGET_ISA'] == 'alpha': 69 dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") 70 itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") 71 elif build_env['TARGET_ISA'] == 'x86': 72 dtb = Param.X86DTB(X86DTB(), "Data TLB") 73 itb = Param.X86ITB(X86ITB(), "Instruction TLB") 74 elif build_env['TARGET_ISA'] == 'mips': 75 dtb = Param.MipsDTB(MipsDTB(), "Data TLB") 76 itb = Param.MipsITB(MipsITB(), "Instruction TLB") 77 else: 78 print "Don't know what TLB to use for ISA %s" % \ 79 build_env['TARGET_ISA'] 80 sys.exit(1) 81 82 max_insts_all_threads = Param.Counter(0, 83 "terminate when all threads have reached this inst count") 84 max_insts_any_thread = Param.Counter(0, 85 "terminate when any thread reaches this inst count") 86 max_loads_all_threads = Param.Counter(0, 87 "terminate when all threads have reached this load count") 88 max_loads_any_thread = Param.Counter(0, 89 "terminate when any thread reaches this load count") 90 progress_interval = Param.Tick(0, 91 "interval to print out the progress message") 92 93 defer_registration = Param.Bool(False, 94 "defer registration with system (for sampling)") 95 96 clock = Param.Clock('1t', "clock speed") 97 phase = Param.Latency('0ns', "clock phase") 98 99 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 100 101 _mem_ports = [] 102 103 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: 104 _mem_ports = ["itb.walker.port", "dtb.walker.port"] 105 106 def connectMemPorts(self, bus): 107 for p in self._mem_ports: 108 if p != 'physmem_port': 109 exec('self.%s = bus.port' % p) 110 111 def addPrivateSplitL1Caches(self, ic, dc): 112 assert(len(self._mem_ports) < 6) 113 self.icache = ic 114 self.dcache = dc 115 self.icache_port = ic.cpu_side 116 self.dcache_port = dc.cpu_side 117 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 118 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: 119 self._mem_ports += ["itb.walker_port", "dtb.walker_port"] 120 121 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 122 self.addPrivateSplitL1Caches(ic, dc) 123 self.toL2Bus = Bus() 124 self.connectMemPorts(self.toL2Bus) 125 self.l2cache = l2c 126 self.l2cache.cpu_side = self.toL2Bus.port 127 self._mem_ports = ['l2cache.mem_side'] 128