BaseCPU.py revision 3170
1from m5.SimObject import SimObject 2from m5.params import * 3from m5.proxy import * 4from m5 import build_env 5from AlphaTLB import AlphaDTB, AlphaITB 6from Bus import Bus 7 8class BaseCPU(SimObject): 9 type = 'BaseCPU' 10 abstract = True 11 mem = Param.MemObject("memory") 12 13 system = Param.System(Parent.any, "system object") 14 cpu_id = Param.Int("CPU identifier") 15 16 if build_env['FULL_SYSTEM']: 17 dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") 18 itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") 19 else: 20 workload = VectorParam.Process("processes to run") 21 22 max_insts_all_threads = Param.Counter(0, 23 "terminate when all threads have reached this inst count") 24 max_insts_any_thread = Param.Counter(0, 25 "terminate when any thread reaches this inst count") 26 max_loads_all_threads = Param.Counter(0, 27 "terminate when all threads have reached this load count") 28 max_loads_any_thread = Param.Counter(0, 29 "terminate when any thread reaches this load count") 30 progress_interval = Param.Tick(0, "interval to print out the progress message") 31 32 defer_registration = Param.Bool(False, 33 "defer registration with system (for sampling)") 34 35 clock = Param.Clock(Parent.clock, "clock speed") 36 37 _mem_ports = [] 38 39 def connectMemPorts(self, bus): 40 for p in self._mem_ports: 41 exec('self.%s = bus.port' % p) 42 43 def addPrivateSplitL1Caches(self, ic, dc): 44 assert(len(self._mem_ports) == 2) 45 self.icache = ic 46 self.dcache = dc 47 self.icache_port = ic.cpu_side 48 self.dcache_port = dc.cpu_side 49 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 50# self.mem = dc 51 52 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 53 self.addPrivateSplitL1Caches(ic, dc) 54 self.toL2Bus = Bus() 55 self.connectMemPorts(self.toL2Bus) 56 self.l2cache = l2c 57 self.l2cache.cpu_side = self.toL2Bus.port 58 self._mem_ports = ['l2cache.mem_side'] 59