BaseCPU.py revision 12325:48e41e644187
13101Sstever@eecs.umich.edu# Copyright (c) 2012-2013, 2015-2017 ARM Limited 23101Sstever@eecs.umich.edu# All rights reserved. 33101Sstever@eecs.umich.edu# 43101Sstever@eecs.umich.edu# The license below extends only to copyright in the software and shall 53101Sstever@eecs.umich.edu# not be construed as granting a license to any other intellectual 63101Sstever@eecs.umich.edu# property including but not limited to intellectual property relating 73101Sstever@eecs.umich.edu# to a hardware implementation of the functionality of the software 83101Sstever@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 93101Sstever@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 103101Sstever@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 113101Sstever@eecs.umich.edu# modified or unmodified, in source code or in binary form. 123101Sstever@eecs.umich.edu# 133101Sstever@eecs.umich.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 143101Sstever@eecs.umich.edu# Copyright (c) 2011 Regents of the University of California 153101Sstever@eecs.umich.edu# All rights reserved. 163101Sstever@eecs.umich.edu# 173101Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 183101Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 193101Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 203101Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 213101Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 223101Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 233101Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 243101Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 253101Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 263101Sstever@eecs.umich.edu# this software without specific prior written permission. 273101Sstever@eecs.umich.edu# 283101Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293101Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303101Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313101Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323101Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333101Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343101Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353101Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363101Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373101Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383101Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393101Sstever@eecs.umich.edu# 403101Sstever@eecs.umich.edu# Authors: Nathan Binkert 413101Sstever@eecs.umich.edu# Rick Strong 423101Sstever@eecs.umich.edu# Andreas Hansson 433101Sstever@eecs.umich.edu 443101Sstever@eecs.umich.eduimport sys 453101Sstever@eecs.umich.edu 463101Sstever@eecs.umich.edufrom m5.SimObject import * 473101Sstever@eecs.umich.edufrom m5.defines import buildEnv 483101Sstever@eecs.umich.edufrom m5.params import * 493102Sstever@eecs.umich.edufrom m5.proxy import * 503101Sstever@eecs.umich.edu 513101Sstever@eecs.umich.edufrom XBar import L2XBar 523101Sstever@eecs.umich.edufrom InstTracer import InstTracer 533101Sstever@eecs.umich.edufrom CPUTracers import ExeTracer 543101Sstever@eecs.umich.edufrom MemObject import MemObject 553101Sstever@eecs.umich.edufrom ClockDomain import * 563101Sstever@eecs.umich.edu 573101Sstever@eecs.umich.edudefault_tracer = ExeTracer() 583101Sstever@eecs.umich.edu 593101Sstever@eecs.umich.eduif buildEnv['TARGET_ISA'] == 'alpha': 603101Sstever@eecs.umich.edu from AlphaTLB import AlphaDTB, AlphaITB 613101Sstever@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 623101Sstever@eecs.umich.edu from AlphaISA import AlphaISA 633101Sstever@eecs.umich.edu default_isa_class = AlphaISA 643101Sstever@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'sparc': 653101Sstever@eecs.umich.edu from SparcTLB import SparcTLB 663101Sstever@eecs.umich.edu from SparcInterrupts import SparcInterrupts 673101Sstever@eecs.umich.edu from SparcISA import SparcISA 683101Sstever@eecs.umich.edu default_isa_class = SparcISA 693101Sstever@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'x86': 703101Sstever@eecs.umich.edu from X86TLB import X86TLB 713101Sstever@eecs.umich.edu from X86LocalApic import X86LocalApic 723101Sstever@eecs.umich.edu from X86ISA import X86ISA 733101Sstever@eecs.umich.edu default_isa_class = X86ISA 743101Sstever@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'mips': 753101Sstever@eecs.umich.edu from MipsTLB import MipsTLB 763101Sstever@eecs.umich.edu from MipsInterrupts import MipsInterrupts 773101Sstever@eecs.umich.edu from MipsISA import MipsISA 783101Sstever@eecs.umich.edu default_isa_class = MipsISA 793101Sstever@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'arm': 803101Sstever@eecs.umich.edu from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU 813101Sstever@eecs.umich.edu from ArmInterrupts import ArmInterrupts 823101Sstever@eecs.umich.edu from ArmISA import ArmISA 833101Sstever@eecs.umich.edu default_isa_class = ArmISA 843101Sstever@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'power': 853101Sstever@eecs.umich.edu from PowerTLB import PowerTLB 863101Sstever@eecs.umich.edu from PowerInterrupts import PowerInterrupts 873101Sstever@eecs.umich.edu from PowerISA import PowerISA 883101Sstever@eecs.umich.edu default_isa_class = PowerISA 893101Sstever@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'riscv': 903101Sstever@eecs.umich.edu from RiscvTLB import RiscvTLB 913101Sstever@eecs.umich.edu from RiscvInterrupts import RiscvInterrupts 923101Sstever@eecs.umich.edu from RiscvISA import RiscvISA 933101Sstever@eecs.umich.edu default_isa_class = RiscvISA 943101Sstever@eecs.umich.edu 953101Sstever@eecs.umich.educlass BaseCPU(MemObject): 963101Sstever@eecs.umich.edu type = 'BaseCPU' 973101Sstever@eecs.umich.edu abstract = True 983101Sstever@eecs.umich.edu cxx_header = "cpu/base.hh" 993101Sstever@eecs.umich.edu 1003101Sstever@eecs.umich.edu cxx_exports = [ 1013101Sstever@eecs.umich.edu PyBindMethod("switchOut"), 1023101Sstever@eecs.umich.edu PyBindMethod("takeOverFrom"), 1033101Sstever@eecs.umich.edu PyBindMethod("switchedOut"), 1043102Sstever@eecs.umich.edu PyBindMethod("flushTLBs"), 1053101Sstever@eecs.umich.edu PyBindMethod("totalInsts"), 1063102Sstever@eecs.umich.edu PyBindMethod("scheduleInstStop"), 1073101Sstever@eecs.umich.edu PyBindMethod("scheduleLoadStop"), 1083101Sstever@eecs.umich.edu PyBindMethod("getCurrentInstCount"), 1093101Sstever@eecs.umich.edu ] 1103102Sstever@eecs.umich.edu 1113102Sstever@eecs.umich.edu @classmethod 1123101Sstever@eecs.umich.edu def memory_mode(cls): 1133101Sstever@eecs.umich.edu """Which memory mode does this CPU require?""" 1143101Sstever@eecs.umich.edu return 'invalid' 1153101Sstever@eecs.umich.edu 1163101Sstever@eecs.umich.edu @classmethod 1173101Sstever@eecs.umich.edu def require_caches(cls): 1183101Sstever@eecs.umich.edu """Does the CPU model require caches? 1193101Sstever@eecs.umich.edu 1203101Sstever@eecs.umich.edu Some CPU models might make assumptions that require them to 1213101Sstever@eecs.umich.edu have caches. 1223101Sstever@eecs.umich.edu """ 1233101Sstever@eecs.umich.edu return False 1243101Sstever@eecs.umich.edu 1253102Sstever@eecs.umich.edu @classmethod 1263101Sstever@eecs.umich.edu def support_take_over(cls): 1273101Sstever@eecs.umich.edu """Does the CPU model support CPU takeOverFrom?""" 1283101Sstever@eecs.umich.edu return False 1293101Sstever@eecs.umich.edu 1303101Sstever@eecs.umich.edu def takeOverFrom(self, old_cpu): 1313101Sstever@eecs.umich.edu self._ccObject.takeOverFrom(old_cpu._ccObject) 1323101Sstever@eecs.umich.edu 1333101Sstever@eecs.umich.edu 1343101Sstever@eecs.umich.edu system = Param.System(Parent.any, "system object") 1353101Sstever@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 1363101Sstever@eecs.umich.edu socket_id = Param.Unsigned(0, "Physical Socket identifier") 1373101Sstever@eecs.umich.edu numThreads = Param.Unsigned(1, "number of HW thread contexts") 1383101Sstever@eecs.umich.edu pwr_gating_latency = Param.Cycles(300, 1393101Sstever@eecs.umich.edu "Latency to enter power gating state when all contexts are suspended") 1403101Sstever@eecs.umich.edu 1413101Sstever@eecs.umich.edu power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\ 1423101Sstever@eecs.umich.edu "to the OFF power state after all thread are disabled for "\ 1433101Sstever@eecs.umich.edu "pwr_gating_latency cycles") 1443101Sstever@eecs.umich.edu 1453101Sstever@eecs.umich.edu function_trace = Param.Bool(False, "Enable function trace") 1463101Sstever@eecs.umich.edu function_trace_start = Param.Tick(0, "Tick to start function trace") 1473101Sstever@eecs.umich.edu 1483101Sstever@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1493101Sstever@eecs.umich.edu 1503101Sstever@eecs.umich.edu syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry") 1513101Sstever@eecs.umich.edu 1523101Sstever@eecs.umich.edu do_checkpoint_insts = Param.Bool(True, 1533101Sstever@eecs.umich.edu "enable checkpoint pseudo instructions") 1543101Sstever@eecs.umich.edu do_statistics_insts = Param.Bool(True, 1553101Sstever@eecs.umich.edu "enable statistics pseudo instructions") 1563101Sstever@eecs.umich.edu 1573101Sstever@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 1583101Sstever@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 1593101Sstever@eecs.umich.edu 1603101Sstever@eecs.umich.edu wait_for_remote_gdb = Param.Bool(False, 1613101Sstever@eecs.umich.edu "Wait for a remote GDB connection"); 1623101Sstever@eecs.umich.edu 1633101Sstever@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 1643101Sstever@eecs.umich.edu 1653101Sstever@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'sparc': 1663101Sstever@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 1673101Sstever@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 1683101Sstever@eecs.umich.edu interrupts = VectorParam.SparcInterrupts( 1693101Sstever@eecs.umich.edu [], "Interrupt Controller") 1703101Sstever@eecs.umich.edu isa = VectorParam.SparcISA([], "ISA instance") 1713101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'alpha': 1723101Sstever@eecs.umich.edu dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 1733101Sstever@eecs.umich.edu itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 1743101Sstever@eecs.umich.edu interrupts = VectorParam.AlphaInterrupts( 1753101Sstever@eecs.umich.edu [], "Interrupt Controller") 1763101Sstever@eecs.umich.edu isa = VectorParam.AlphaISA([], "ISA instance") 1773101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 1783101Sstever@eecs.umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 1793101Sstever@eecs.umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 1803101Sstever@eecs.umich.edu interrupts = VectorParam.X86LocalApic([], "Interrupt Controller") 1813101Sstever@eecs.umich.edu isa = VectorParam.X86ISA([], "ISA instance") 1823101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 1833101Sstever@eecs.umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1843101Sstever@eecs.umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1853101Sstever@eecs.umich.edu interrupts = VectorParam.MipsInterrupts( 1863101Sstever@eecs.umich.edu [], "Interrupt Controller") 1873101Sstever@eecs.umich.edu isa = VectorParam.MipsISA([], "ISA instance") 1883101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 1893101Sstever@eecs.umich.edu dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1903101Sstever@eecs.umich.edu itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1913101Sstever@eecs.umich.edu istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") 1923101Sstever@eecs.umich.edu dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") 1933101Sstever@eecs.umich.edu interrupts = VectorParam.ArmInterrupts( 1943101Sstever@eecs.umich.edu [], "Interrupt Controller") 1953101Sstever@eecs.umich.edu isa = VectorParam.ArmISA([], "ISA instance") 1963101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'power': 1973101Sstever@eecs.umich.edu UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1983101Sstever@eecs.umich.edu dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1993101Sstever@eecs.umich.edu itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 2003101Sstever@eecs.umich.edu interrupts = VectorParam.PowerInterrupts( 2013101Sstever@eecs.umich.edu [], "Interrupt Controller") 2023101Sstever@eecs.umich.edu isa = VectorParam.PowerISA([], "ISA instance") 2033101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'riscv': 2043101Sstever@eecs.umich.edu dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB") 2053101Sstever@eecs.umich.edu itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB") 2063101Sstever@eecs.umich.edu interrupts = VectorParam.RiscvInterrupts( 2073101Sstever@eecs.umich.edu [], "Interrupt Controller") 2083101Sstever@eecs.umich.edu isa = VectorParam.RiscvISA([], "ISA instance") 2093101Sstever@eecs.umich.edu else: 2103101Sstever@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 2113101Sstever@eecs.umich.edu buildEnv['TARGET_ISA'] 2123101Sstever@eecs.umich.edu sys.exit(1) 2133101Sstever@eecs.umich.edu 2143101Sstever@eecs.umich.edu max_insts_all_threads = Param.Counter(0, 2153101Sstever@eecs.umich.edu "terminate when all threads have reached this inst count") 2163101Sstever@eecs.umich.edu max_insts_any_thread = Param.Counter(0, 2173101Sstever@eecs.umich.edu "terminate when any thread reaches this inst count") 2183101Sstever@eecs.umich.edu simpoint_start_insts = VectorParam.Counter([], 2193101Sstever@eecs.umich.edu "starting instruction counts of simpoints") 2203101Sstever@eecs.umich.edu max_loads_all_threads = Param.Counter(0, 2213101Sstever@eecs.umich.edu "terminate when all threads have reached this load count") 2223101Sstever@eecs.umich.edu max_loads_any_thread = Param.Counter(0, 2233101Sstever@eecs.umich.edu "terminate when any thread reaches this load count") 2243101Sstever@eecs.umich.edu progress_interval = Param.Frequency('0Hz', 2253101Sstever@eecs.umich.edu "frequency to print out the progress message") 2263101Sstever@eecs.umich.edu 2273101Sstever@eecs.umich.edu switched_out = Param.Bool(False, 2283101Sstever@eecs.umich.edu "Leave the CPU switched out after startup (used when switching " \ 2293101Sstever@eecs.umich.edu "between CPU models)") 2303101Sstever@eecs.umich.edu 2313101Sstever@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 2323101Sstever@eecs.umich.edu 2333101Sstever@eecs.umich.edu icache_port = MasterPort("Instruction Port") 2343101Sstever@eecs.umich.edu dcache_port = MasterPort("Data Port") 2353101Sstever@eecs.umich.edu _cached_ports = ['icache_port', 'dcache_port'] 2363101Sstever@eecs.umich.edu 2373101Sstever@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2383101Sstever@eecs.umich.edu _cached_ports += ["itb.walker.port", "dtb.walker.port"] 2393101Sstever@eecs.umich.edu 2403101Sstever@eecs.umich.edu _uncached_slave_ports = [] 2413101Sstever@eecs.umich.edu _uncached_master_ports = [] 2423101Sstever@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 2433101Sstever@eecs.umich.edu _uncached_slave_ports += ["interrupts[0].pio", 2443101Sstever@eecs.umich.edu "interrupts[0].int_slave"] 2453101Sstever@eecs.umich.edu _uncached_master_ports += ["interrupts[0].int_master"] 2463101Sstever@eecs.umich.edu 2473101Sstever@eecs.umich.edu def createInterruptController(self): 2483101Sstever@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'sparc': 2493101Sstever@eecs.umich.edu self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)] 2503101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'alpha': 2513101Sstever@eecs.umich.edu self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)] 2523101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 2533101Sstever@eecs.umich.edu self.apic_clk_domain = DerivedClockDomain(clk_domain = 2543101Sstever@eecs.umich.edu Parent.clk_domain, 2553101Sstever@eecs.umich.edu clk_divider = 16) 2563101Sstever@eecs.umich.edu self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain, 2573101Sstever@eecs.umich.edu pio_addr=0x2000000000000000) 2583101Sstever@eecs.umich.edu for i in xrange(self.numThreads)] 2593101Sstever@eecs.umich.edu _localApic = self.interrupts 2603101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 2613101Sstever@eecs.umich.edu self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)] 2623101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 2633101Sstever@eecs.umich.edu self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)] 2643101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'power': 2653101Sstever@eecs.umich.edu self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)] 2663101Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'riscv': 2673101Sstever@eecs.umich.edu self.interrupts = \ 2683101Sstever@eecs.umich.edu [RiscvInterrupts() for i in xrange(self.numThreads)] 2693101Sstever@eecs.umich.edu else: 2703101Sstever@eecs.umich.edu print "Don't know what Interrupt Controller to use for ISA %s" % \ 2713101Sstever@eecs.umich.edu buildEnv['TARGET_ISA'] 2723101Sstever@eecs.umich.edu sys.exit(1) 2733101Sstever@eecs.umich.edu 2743101Sstever@eecs.umich.edu def connectCachedPorts(self, bus): 2753101Sstever@eecs.umich.edu for p in self._cached_ports: 2763101Sstever@eecs.umich.edu exec('self.%s = bus.slave' % p) 2773101Sstever@eecs.umich.edu 2783101Sstever@eecs.umich.edu def connectUncachedPorts(self, bus): 2793101Sstever@eecs.umich.edu for p in self._uncached_slave_ports: 2803101Sstever@eecs.umich.edu exec('self.%s = bus.master' % p) 2813101Sstever@eecs.umich.edu for p in self._uncached_master_ports: 2823101Sstever@eecs.umich.edu exec('self.%s = bus.slave' % p) 2833101Sstever@eecs.umich.edu 2843101Sstever@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 2853101Sstever@eecs.umich.edu self.connectCachedPorts(cached_bus) 2863101Sstever@eecs.umich.edu if not uncached_bus: 2873101Sstever@eecs.umich.edu uncached_bus = cached_bus 2883101Sstever@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 2893101Sstever@eecs.umich.edu 2903101Sstever@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 2913101Sstever@eecs.umich.edu self.icache = ic 2923101Sstever@eecs.umich.edu self.dcache = dc 2933101Sstever@eecs.umich.edu self.icache_port = ic.cpu_side 2943101Sstever@eecs.umich.edu self.dcache_port = dc.cpu_side 2953101Sstever@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 2963101Sstever@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2973101Sstever@eecs.umich.edu if iwc and dwc: 2983101Sstever@eecs.umich.edu self.itb_walker_cache = iwc 2993101Sstever@eecs.umich.edu self.dtb_walker_cache = dwc 3003101Sstever@eecs.umich.edu self.itb.walker.port = iwc.cpu_side 3013101Sstever@eecs.umich.edu self.dtb.walker.port = dwc.cpu_side 3023101Sstever@eecs.umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 3033101Sstever@eecs.umich.edu "dtb_walker_cache.mem_side"] 3043101Sstever@eecs.umich.edu else: 3053101Sstever@eecs.umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 3063101Sstever@eecs.umich.edu 3073101Sstever@eecs.umich.edu # Checker doesn't need its own tlb caches because it does 3083101Sstever@eecs.umich.edu # functional accesses only 3093101Sstever@eecs.umich.edu if self.checker != NULL: 3103102Sstever@eecs.umich.edu self._cached_ports += ["checker.itb.walker.port", \ 3113101Sstever@eecs.umich.edu "checker.dtb.walker.port"] 3123101Sstever@eecs.umich.edu 3133101Sstever@eecs.umich.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 3143101Sstever@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 3153101Sstever@eecs.umich.edu self.toL2Bus = L2XBar() 3163101Sstever@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 3173101Sstever@eecs.umich.edu self.l2cache = l2c 3183101Sstever@eecs.umich.edu self.toL2Bus.master = self.l2cache.cpu_side 3193101Sstever@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 3203101Sstever@eecs.umich.edu 3213101Sstever@eecs.umich.edu def createThreads(self): 3223101Sstever@eecs.umich.edu # If no ISAs have been created, assume that the user wants the 3233101Sstever@eecs.umich.edu # default ISA. 3243101Sstever@eecs.umich.edu if len(self.isa) == 0: 3253101Sstever@eecs.umich.edu self.isa = [ default_isa_class() for i in xrange(self.numThreads) ] 3263101Sstever@eecs.umich.edu else: 3273101Sstever@eecs.umich.edu if len(self.isa) != int(self.numThreads): 3283101Sstever@eecs.umich.edu raise RuntimeError("Number of ISA instances doesn't " 3293101Sstever@eecs.umich.edu "match thread count") 3303101Sstever@eecs.umich.edu if self.checker != NULL: 3313101Sstever@eecs.umich.edu self.checker.createThreads() 3323101Sstever@eecs.umich.edu 3333101Sstever@eecs.umich.edu def addCheckerCpu(self): 3343101Sstever@eecs.umich.edu pass 3353101Sstever@eecs.umich.edu