BaseCPU.py revision 11988 
1# Copyright (c) 2012-2013, 2015 ARM Limited
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14# Copyright (c) 2011 Regents of the University of California
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39#
40# Authors: Nathan Binkert
41#          Rick Strong
42#          Andreas Hansson
43
44import sys
45
46from m5.SimObject import *
47from m5.defines import buildEnv
48from m5.params import *
49from m5.proxy import *
50
51from XBar import L2XBar
52from InstTracer import InstTracer
53from CPUTracers import ExeTracer
54from MemObject import MemObject
55from ClockDomain import *
56
57default_tracer = ExeTracer()
58
59if buildEnv['TARGET_ISA'] == 'alpha':
60    from AlphaTLB import AlphaDTB, AlphaITB
61    from AlphaInterrupts import AlphaInterrupts
62    from AlphaISA import AlphaISA
63    isa_class = AlphaISA
64elif buildEnv['TARGET_ISA'] == 'sparc':
65    from SparcTLB import SparcTLB
66    from SparcInterrupts import SparcInterrupts
67    from SparcISA import SparcISA
68    isa_class = SparcISA
69elif buildEnv['TARGET_ISA'] == 'x86':
70    from X86TLB import X86TLB
71    from X86LocalApic import X86LocalApic
72    from X86ISA import X86ISA
73    isa_class = X86ISA
74elif buildEnv['TARGET_ISA'] == 'mips':
75    from MipsTLB import MipsTLB
76    from MipsInterrupts import MipsInterrupts
77    from MipsISA import MipsISA
78    isa_class = MipsISA
79elif buildEnv['TARGET_ISA'] == 'arm':
80    from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
81    from ArmInterrupts import ArmInterrupts
82    from ArmISA import ArmISA
83    isa_class = ArmISA
84elif buildEnv['TARGET_ISA'] == 'power':
85    from PowerTLB import PowerTLB
86    from PowerInterrupts import PowerInterrupts
87    from PowerISA import PowerISA
88    isa_class = PowerISA
89elif buildEnv['TARGET_ISA'] == 'riscv':
90    from RiscvTLB import RiscvTLB
91    from RiscvInterrupts import RiscvInterrupts
92    from RiscvISA import RiscvISA
93    isa_class = RiscvISA
94
95class BaseCPU(MemObject):
96    type = 'BaseCPU'
97    abstract = True
98    cxx_header = "cpu/base.hh"
99
100    cxx_exports = [
101        PyBindMethod("switchOut"),
102        PyBindMethod("takeOverFrom"),
103        PyBindMethod("switchedOut"),
104        PyBindMethod("flushTLBs"),
105        PyBindMethod("totalInsts"),
106        PyBindMethod("scheduleInstStop"),
107        PyBindMethod("scheduleLoadStop"),
108        PyBindMethod("getCurrentInstCount"),
109    ]
110
111    @classmethod
112    def memory_mode(cls):
113        """Which memory mode does this CPU require?"""
114        return 'invalid'
115
116    @classmethod
117    def require_caches(cls):
118        """Does the CPU model require caches?
119
120        Some CPU models might make assumptions that require them to
121        have caches.
122        """
123        return False
124
125    @classmethod
126    def support_take_over(cls):
127        """Does the CPU model support CPU takeOverFrom?"""
128        return False
129
130    def takeOverFrom(self, old_cpu):
131        self._ccObject.takeOverFrom(old_cpu._ccObject)
132
133
134    system = Param.System(Parent.any, "system object")
135    cpu_id = Param.Int(-1, "CPU identifier")
136    socket_id = Param.Unsigned(0, "Physical Socket identifier")
137    numThreads = Param.Unsigned(1, "number of HW thread contexts")
138
139    function_trace = Param.Bool(False, "Enable function trace")
140    function_trace_start = Param.Tick(0, "Tick to start function trace")
141
142    checker = Param.BaseCPU(NULL, "checker CPU")
143
144    syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry")
145
146    do_checkpoint_insts = Param.Bool(True,
147        "enable checkpoint pseudo instructions")
148    do_statistics_insts = Param.Bool(True,
149        "enable statistics pseudo instructions")
150
151    profile = Param.Latency('0ns', "trace the kernel stack")
152    do_quiesce = Param.Bool(True, "enable quiesce instructions")
153
154    workload = VectorParam.Process([], "processes to run")
155
156    if buildEnv['TARGET_ISA'] == 'sparc':
157        dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
158        itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
159        interrupts = VectorParam.SparcInterrupts(
160                [], "Interrupt Controller")
161        isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
162    elif buildEnv['TARGET_ISA'] == 'alpha':
163        dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
164        itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
165        interrupts = VectorParam.AlphaInterrupts(
166                [], "Interrupt Controller")
167        isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
168    elif buildEnv['TARGET_ISA'] == 'x86':
169        dtb = Param.X86TLB(X86TLB(), "Data TLB")
170        itb = Param.X86TLB(X86TLB(), "Instruction TLB")
171        interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
172        isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
173    elif buildEnv['TARGET_ISA'] == 'mips':
174        dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
175        itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
176        interrupts = VectorParam.MipsInterrupts(
177                [], "Interrupt Controller")
178        isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
179    elif buildEnv['TARGET_ISA'] == 'arm':
180        dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
181        itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
182        istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
183        dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
184        interrupts = VectorParam.ArmInterrupts(
185                [], "Interrupt Controller")
186        isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
187    elif buildEnv['TARGET_ISA'] == 'power':
188        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
189        dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
190        itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
191        interrupts = VectorParam.PowerInterrupts(
192                [], "Interrupt Controller")
193        isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
194    elif buildEnv['TARGET_ISA'] == 'riscv':
195        dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
196        itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
197        interrupts = VectorParam.RiscvInterrupts(
198                [], "Interrupt Controller")
199        isa = VectorParam.RiscvISA([ isa_class() ], "ISA instance")
200    else:
201        print "Don't know what TLB to use for ISA %s" % \
202            buildEnv['TARGET_ISA']
203        sys.exit(1)
204
205    max_insts_all_threads = Param.Counter(0,
206        "terminate when all threads have reached this inst count")
207    max_insts_any_thread = Param.Counter(0,
208        "terminate when any thread reaches this inst count")
209    simpoint_start_insts = VectorParam.Counter([],
210        "starting instruction counts of simpoints")
211    max_loads_all_threads = Param.Counter(0,
212        "terminate when all threads have reached this load count")
213    max_loads_any_thread = Param.Counter(0,
214        "terminate when any thread reaches this load count")
215    progress_interval = Param.Frequency('0Hz',
216        "frequency to print out the progress message")
217
218    switched_out = Param.Bool(False,
219        "Leave the CPU switched out after startup (used when switching " \
220        "between CPU models)")
221
222    tracer = Param.InstTracer(default_tracer, "Instruction tracer")
223
224    icache_port = MasterPort("Instruction Port")
225    dcache_port = MasterPort("Data Port")
226    _cached_ports = ['icache_port', 'dcache_port']
227
228    if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
229        _cached_ports += ["itb.walker.port", "dtb.walker.port"]
230
231    _uncached_slave_ports = []
232    _uncached_master_ports = []
233    if buildEnv['TARGET_ISA'] == 'x86':
234        _uncached_slave_ports += ["interrupts[0].pio",
235                                  "interrupts[0].int_slave"]
236        _uncached_master_ports += ["interrupts[0].int_master"]
237
238    def createInterruptController(self):
239        if buildEnv['TARGET_ISA'] == 'sparc':
240            self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)]
241        elif buildEnv['TARGET_ISA'] == 'alpha':
242            self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)]
243        elif buildEnv['TARGET_ISA'] == 'x86':
244            self.apic_clk_domain = DerivedClockDomain(clk_domain =
245                                                      Parent.clk_domain,
246                                                      clk_divider = 16)
247            self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain,
248                                           pio_addr=0x2000000000000000)
249                               for i in xrange(self.numThreads)]
250            _localApic = self.interrupts
251        elif buildEnv['TARGET_ISA'] == 'mips':
252            self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
253        elif buildEnv['TARGET_ISA'] == 'arm':
254            self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
255        elif buildEnv['TARGET_ISA'] == 'power':
256            self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
257        elif buildEnv['TARGET_ISA'] == 'riscv':
258            self.interrupts = \
259                [RiscvInterrupts() for i in xrange(self.numThreads)]
260        else:
261            print "Don't know what Interrupt Controller to use for ISA %s" % \
262                buildEnv['TARGET_ISA']
263            sys.exit(1)
264
265    def connectCachedPorts(self, bus):
266        for p in self._cached_ports:
267            exec('self.%s = bus.slave' % p)
268
269    def connectUncachedPorts(self, bus):
270        for p in self._uncached_slave_ports:
271            exec('self.%s = bus.master' % p)
272        for p in self._uncached_master_ports:
273            exec('self.%s = bus.slave' % p)
274
275    def connectAllPorts(self, cached_bus, uncached_bus = None):
276        self.connectCachedPorts(cached_bus)
277        if not uncached_bus:
278            uncached_bus = cached_bus
279        self.connectUncachedPorts(uncached_bus)
280
281    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
282        self.icache = ic
283        self.dcache = dc
284        self.icache_port = ic.cpu_side
285        self.dcache_port = dc.cpu_side
286        self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
287        if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
288            if iwc and dwc:
289                self.itb_walker_cache = iwc
290                self.dtb_walker_cache = dwc
291                self.itb.walker.port = iwc.cpu_side
292                self.dtb.walker.port = dwc.cpu_side
293                self._cached_ports += ["itb_walker_cache.mem_side", \
294                                       "dtb_walker_cache.mem_side"]
295            else:
296                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
297
298            # Checker doesn't need its own tlb caches because it does
299            # functional accesses only
300            if self.checker != NULL:
301                self._cached_ports += ["checker.itb.walker.port", \
302                                       "checker.dtb.walker.port"]
303
304    def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
305        self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
306        self.toL2Bus = L2XBar()
307        self.connectCachedPorts(self.toL2Bus)
308        self.l2cache = l2c
309        self.toL2Bus.master = self.l2cache.cpu_side
310        self._cached_ports = ['l2cache.mem_side']
311
312    def createThreads(self):
313        self.isa = [ isa_class() for i in xrange(self.numThreads) ]
314        if self.checker != NULL:
315            self.checker.createThreads()
316
317    def addCheckerCpu(self):
318        pass
319