BaseCPU.py revision 8793
15335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 27897Shestness@cs.utexas.edu# Copyright (c) 2011 Regents of the University of California 34486Sbinkertn@umich.edu# All rights reserved. 44486Sbinkertn@umich.edu# 54486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 64486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 74486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 84486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 94486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 104486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 114486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 124486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 134486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 144486Sbinkertn@umich.edu# this software without specific prior written permission. 154486Sbinkertn@umich.edu# 164486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# Authors: Nathan Binkert 297897Shestness@cs.utexas.edu# Rick Strong 304486Sbinkertn@umich.edu 316654Snate@binkert.orgimport sys 326654Snate@binkert.org 336654Snate@binkert.orgfrom m5.defines import buildEnv 343102SN/Afrom m5.params import * 353102SN/Afrom m5.proxy import * 366654Snate@binkert.org 372998SN/Afrom Bus import Bus 384776Sgblack@eecs.umich.edufrom InstTracer import InstTracer 394776Sgblack@eecs.umich.edufrom ExeTracer import ExeTracer 406654Snate@binkert.orgfrom MemObject import MemObject 412667SN/A 424776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 434776Sgblack@eecs.umich.edu 446654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 456023Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 468745Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 476654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 486022Sgblack@eecs.umich.edu from SparcTLB import SparcTLB 498745Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 506654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 516022Sgblack@eecs.umich.edu from X86TLB import X86TLB 528745Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 536654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 546022Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 558745Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 566654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 576116Snate@binkert.org from ArmTLB import ArmTLB 588745Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 596691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'power': 606691Stjones1@inf.ed.ac.uk from PowerTLB import PowerTLB 618745Sgblack@eecs.umich.edu from PowerInterrupts import PowerInterrupts 624486Sbinkertn@umich.edu 635529Snate@binkert.orgclass BaseCPU(MemObject): 641366SN/A type = 'BaseCPU' 651310SN/A abstract = True 661310SN/A 672901SN/A system = Param.System(Parent.any, "system object") 685712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 695529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 705529Snate@binkert.org 715529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 725529Snate@binkert.org function_trace_start = Param.Tick(0, "Cycle to start function trace") 735529Snate@binkert.org 745821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 753170SN/A 765780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 775780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 785780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 795780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 805780Ssteve.reinhardt@amd.com 818784Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 828784Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 838784Sgblack@eecs.umich.edu 848793Sgblack@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 851310SN/A 866654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'sparc': 876022Sgblack@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 886022Sgblack@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 898745Sgblack@eecs.umich.edu interrupts = Param.SparcInterrupts( 905647Sgblack@eecs.umich.edu SparcInterrupts(), "Interrupt Controller") 916654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'alpha': 926023Snate@binkert.org dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 936023Snate@binkert.org itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 948745Sgblack@eecs.umich.edu interrupts = Param.AlphaInterrupts( 955647Sgblack@eecs.umich.edu AlphaInterrupts(), "Interrupt Controller") 966654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 976022Sgblack@eecs.umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 986022Sgblack@eecs.umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 998745Sgblack@eecs.umich.edu _localApic = X86LocalApic(pio_addr=0x2000000000000000) 1008745Sgblack@eecs.umich.edu interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller") 1016654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 1026022Sgblack@eecs.umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1036022Sgblack@eecs.umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1048745Sgblack@eecs.umich.edu interrupts = Param.MipsInterrupts( 1058745Sgblack@eecs.umich.edu MipsInterrupts(), "Interrupt Controller") 1066654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 1076116Snate@binkert.org dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1086116Snate@binkert.org itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1098745Sgblack@eecs.umich.edu interrupts = Param.ArmInterrupts( 1108745Sgblack@eecs.umich.edu ArmInterrupts(), "Interrupt Controller") 1116691Stjones1@inf.ed.ac.uk elif buildEnv['TARGET_ISA'] == 'power': 1126691Stjones1@inf.ed.ac.uk UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1136691Stjones1@inf.ed.ac.uk dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1146691Stjones1@inf.ed.ac.uk itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 1158745Sgblack@eecs.umich.edu interrupts = Param.PowerInterrupts( 1168745Sgblack@eecs.umich.edu PowerInterrupts(), "Interrupt Controller") 1174997Sgblack@eecs.umich.edu else: 1184997Sgblack@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 1196654Snate@binkert.org buildEnv['TARGET_ISA'] 1204997Sgblack@eecs.umich.edu sys.exit(1) 1214997Sgblack@eecs.umich.edu 1221310SN/A max_insts_all_threads = Param.Counter(0, 1231310SN/A "terminate when all threads have reached this inst count") 1241310SN/A max_insts_any_thread = Param.Counter(0, 1251310SN/A "terminate when any thread reaches this inst count") 1261310SN/A max_loads_all_threads = Param.Counter(0, 1271310SN/A "terminate when all threads have reached this load count") 1281310SN/A max_loads_any_thread = Param.Counter(0, 1291310SN/A "terminate when any thread reaches this load count") 1303878SN/A progress_interval = Param.Tick(0, 1313878SN/A "interval to print out the progress message") 1321310SN/A 1331369SN/A defer_registration = Param.Bool(False, 1341310SN/A "defer registration with system (for sampling)") 1351634SN/A 1364167SN/A clock = Param.Clock('1t', "clock speed") 1374167SN/A phase = Param.Latency('0ns', "clock phase") 1382998SN/A 1394776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 1404776Sgblack@eecs.umich.edu 1417876Sgblack@eecs.umich.edu _cached_ports = [] 1428756Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 1437876Sgblack@eecs.umich.edu _cached_ports = ["itb.walker.port", "dtb.walker.port"] 1447876Sgblack@eecs.umich.edu 1457876Sgblack@eecs.umich.edu _uncached_ports = [] 1468745Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 1477876Sgblack@eecs.umich.edu _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 1482998SN/A 1497876Sgblack@eecs.umich.edu def connectCachedPorts(self, bus): 1507876Sgblack@eecs.umich.edu for p in self._cached_ports: 1517876Sgblack@eecs.umich.edu exec('self.%s = bus.port' % p) 1527404SAli.Saidi@ARM.com 1537876Sgblack@eecs.umich.edu def connectUncachedPorts(self, bus): 1547876Sgblack@eecs.umich.edu for p in self._uncached_ports: 1557876Sgblack@eecs.umich.edu exec('self.%s = bus.port' % p) 1567876Sgblack@eecs.umich.edu 1577876Sgblack@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 1587876Sgblack@eecs.umich.edu self.connectCachedPorts(cached_bus) 1597876Sgblack@eecs.umich.edu if not uncached_bus: 1607876Sgblack@eecs.umich.edu uncached_bus = cached_bus 1617876Sgblack@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 1622998SN/A 1637868Sgblack@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 1647876Sgblack@eecs.umich.edu assert(len(self._cached_ports) < 7) 1652998SN/A self.icache = ic 1662998SN/A self.dcache = dc 1672998SN/A self.icache_port = ic.cpu_side 1682998SN/A self.dcache_port = dc.cpu_side 1697876Sgblack@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 1708756Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86' and iwc and dwc: 1718756Sgblack@eecs.umich.edu self.itb_walker_cache = iwc 1728756Sgblack@eecs.umich.edu self.dtb_walker_cache = dwc 1738756Sgblack@eecs.umich.edu self.itb.walker.port = iwc.cpu_side 1748756Sgblack@eecs.umich.edu self.dtb.walker.port = dwc.cpu_side 1758756Sgblack@eecs.umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 1768756Sgblack@eecs.umich.edu "dtb_walker_cache.mem_side"] 1778756Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 1788756Sgblack@eecs.umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 1792998SN/A 1807868Sgblack@eecs.umich.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 1817868Sgblack@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 1822998SN/A self.toL2Bus = Bus() 1837876Sgblack@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 1842998SN/A self.l2cache = l2c 1853017SN/A self.l2cache.cpu_side = self.toL2Bus.port 1867876Sgblack@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 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