BaseCPU.py revision 7776
15335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 24486Sbinkertn@umich.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 54486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 64486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 74486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 84486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 114486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 124486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 134486Sbinkertn@umich.edu# this software without specific prior written permission. 144486Sbinkertn@umich.edu# 154486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# Authors: Nathan Binkert 284486Sbinkertn@umich.edu 296654Snate@binkert.orgimport sys 306654Snate@binkert.org 316654Snate@binkert.orgfrom m5.defines import buildEnv 323102SN/Afrom m5.params import * 333102SN/Afrom m5.proxy import * 346654Snate@binkert.org 352998SN/Afrom Bus import Bus 364776Sgblack@eecs.umich.edufrom InstTracer import InstTracer 374776Sgblack@eecs.umich.edufrom ExeTracer import ExeTracer 386654Snate@binkert.orgfrom MemObject import MemObject 392667SN/A 404776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 414776Sgblack@eecs.umich.edu 426654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 436023Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 446654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 455647Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 466654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 476022Sgblack@eecs.umich.edu from SparcTLB import SparcTLB 486654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 495647Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 506654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 516022Sgblack@eecs.umich.edu from X86TLB import X86TLB 526654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 535647Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 546654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 556022Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 566654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 575647Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 586654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 596116Snate@binkert.org from ArmTLB import ArmTLB 606654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 615647Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 626691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'power': 636691Stjones1@inf.ed.ac.uk from PowerTLB import PowerTLB 646691Stjones1@inf.ed.ac.uk if buildEnv['FULL_SYSTEM']: 656691Stjones1@inf.ed.ac.uk from PowerInterrupts import PowerInterrupts 664486Sbinkertn@umich.edu 675529Snate@binkert.orgclass BaseCPU(MemObject): 681366SN/A type = 'BaseCPU' 691310SN/A abstract = True 701310SN/A 712901SN/A system = Param.System(Parent.any, "system object") 725712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 735529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 745529Snate@binkert.org 755529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 765529Snate@binkert.org function_trace_start = Param.Tick(0, "Cycle to start function trace") 775529Snate@binkert.org 785821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 793170SN/A 805780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 815780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 825780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 835780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 845780Ssteve.reinhardt@amd.com 856654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 865529Snate@binkert.org profile = Param.Latency('0ns', "trace the kernel stack") 873620SN/A do_quiesce = Param.Bool(True, "enable quiesce instructions") 881445SN/A else: 891445SN/A workload = VectorParam.Process("processes to run") 901310SN/A 916654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'sparc': 926022Sgblack@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 936022Sgblack@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 946654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 955647Sgblack@eecs.umich.edu interrupts = Param.SparcInterrupts( 965647Sgblack@eecs.umich.edu SparcInterrupts(), "Interrupt Controller") 976654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'alpha': 986023Snate@binkert.org dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 996023Snate@binkert.org itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 1006654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 1015647Sgblack@eecs.umich.edu interrupts = Param.AlphaInterrupts( 1025647Sgblack@eecs.umich.edu AlphaInterrupts(), "Interrupt Controller") 1036654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 1046022Sgblack@eecs.umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 1056022Sgblack@eecs.umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 1066654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 1075658Sgblack@eecs.umich.edu _localApic = X86LocalApic(pio_addr=0x2000000000000000) 1085648Sgblack@eecs.umich.edu interrupts = \ 1095648Sgblack@eecs.umich.edu Param.X86LocalApic(_localApic, "Interrupt Controller") 1106654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 1116022Sgblack@eecs.umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1126022Sgblack@eecs.umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1136654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 1145647Sgblack@eecs.umich.edu interrupts = Param.MipsInterrupts( 1155647Sgblack@eecs.umich.edu MipsInterrupts(), "Interrupt Controller") 1166654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 1176116Snate@binkert.org dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1186116Snate@binkert.org itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1196654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 1205647Sgblack@eecs.umich.edu interrupts = Param.ArmInterrupts( 1215647Sgblack@eecs.umich.edu ArmInterrupts(), "Interrupt Controller") 1226691Stjones1@inf.ed.ac.uk elif buildEnv['TARGET_ISA'] == 'power': 1236691Stjones1@inf.ed.ac.uk UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1246691Stjones1@inf.ed.ac.uk dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1256691Stjones1@inf.ed.ac.uk itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 1266691Stjones1@inf.ed.ac.uk if buildEnv['FULL_SYSTEM']: 1276691Stjones1@inf.ed.ac.uk interrupts = Param.PowerInterrupts( 1286691Stjones1@inf.ed.ac.uk PowerInterrupts(), "Interrupt Controller") 1294997Sgblack@eecs.umich.edu else: 1304997Sgblack@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 1316654Snate@binkert.org buildEnv['TARGET_ISA'] 1324997Sgblack@eecs.umich.edu sys.exit(1) 1334997Sgblack@eecs.umich.edu 1341310SN/A max_insts_all_threads = Param.Counter(0, 1351310SN/A "terminate when all threads have reached this inst count") 1361310SN/A max_insts_any_thread = Param.Counter(0, 1371310SN/A "terminate when any thread reaches this inst count") 1381310SN/A max_loads_all_threads = Param.Counter(0, 1391310SN/A "terminate when all threads have reached this load count") 1401310SN/A max_loads_any_thread = Param.Counter(0, 1411310SN/A "terminate when any thread reaches this load count") 1423878SN/A progress_interval = Param.Tick(0, 1433878SN/A "interval to print out the progress message") 1441310SN/A 1451369SN/A defer_registration = Param.Bool(False, 1461310SN/A "defer registration with system (for sampling)") 1471634SN/A 1484167SN/A clock = Param.Clock('1t', "clock speed") 1494167SN/A phase = Param.Latency('0ns', "clock phase") 1502998SN/A 1514776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 1524776Sgblack@eecs.umich.edu 1532998SN/A _mem_ports = [] 1546654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: 1555648Sgblack@eecs.umich.edu _mem_ports = ["itb.walker.port", 1565648Sgblack@eecs.umich.edu "dtb.walker.port", 1575651Sgblack@eecs.umich.edu "interrupts.pio", 1585651Sgblack@eecs.umich.edu "interrupts.int_port"] 1592998SN/A 1607404SAli.Saidi@ARM.com if buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']: 1617404SAli.Saidi@ARM.com _mem_ports = ["itb.walker.port", 1627404SAli.Saidi@ARM.com "dtb.walker.port"] 1637404SAli.Saidi@ARM.com 1642998SN/A def connectMemPorts(self, bus): 1652998SN/A for p in self._mem_ports: 1664968Sacolyte@umich.edu if p != 'physmem_port': 1674968Sacolyte@umich.edu exec('self.%s = bus.port' % p) 1682998SN/A 1692998SN/A def addPrivateSplitL1Caches(self, ic, dc): 1707776Sgblack@eecs.umich.edu assert(len(self._mem_ports) < 8) 1712998SN/A self.icache = ic 1722998SN/A self.dcache = dc 1732998SN/A self.icache_port = ic.cpu_side 1742998SN/A self.dcache_port = dc.cpu_side 1752998SN/A self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 1767404SAli.Saidi@ARM.com if buildEnv['FULL_SYSTEM']: 1777404SAli.Saidi@ARM.com if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 1787404SAli.Saidi@ARM.com self._mem_ports += ["itb.walker.port", "dtb.walker.port"] 1797776Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 1807776Sgblack@eecs.umich.edu self._mem_ports += ["interrupts.pio", "interrupts.int_port"] 1812998SN/A 1822998SN/A def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 1832998SN/A self.addPrivateSplitL1Caches(ic, dc) 1842998SN/A self.toL2Bus = Bus() 1852998SN/A self.connectMemPorts(self.toL2Bus) 1862998SN/A self.l2cache = l2c 1873017SN/A self.l2cache.cpu_side = self.toL2Bus.port 1882998SN/A self._mem_ports = ['l2cache.mem_side'] 1895222Sksewell@umich.edu 1906654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'mips': 1915222Sksewell@umich.edu CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") 1925222Sksewell@umich.edu CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") 1935222Sksewell@umich.edu CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") 1945222Sksewell@umich.edu CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") 1955222Sksewell@umich.edu CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") 1965222Sksewell@umich.edu CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") 1975222Sksewell@umich.edu CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company") 1985222Sksewell@umich.edu CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register") 1995222Sksewell@umich.edu CP0_Config_BE = Param.Unsigned(0,"Big Endian?") 2005222Sksewell@umich.edu CP0_Config_AT = Param.Unsigned(0,"No Description") 2015222Sksewell@umich.edu CP0_Config_AR = Param.Unsigned(0,"No Description") 2025222Sksewell@umich.edu CP0_Config_MT = Param.Unsigned(0,"No Description") 2035222Sksewell@umich.edu CP0_Config_VI = Param.Unsigned(0,"No Description") 2045222Sksewell@umich.edu CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?") 2055222Sksewell@umich.edu CP0_Config1_MMU = Param.Unsigned(0,"MMU Type") 2065222Sksewell@umich.edu CP0_Config1_IS = Param.Unsigned(0,"No Description") 2075222Sksewell@umich.edu CP0_Config1_IL = Param.Unsigned(0,"No Description") 2085222Sksewell@umich.edu CP0_Config1_IA = Param.Unsigned(0,"No Description") 2095222Sksewell@umich.edu CP0_Config1_DS = Param.Unsigned(0,"No Description") 2105222Sksewell@umich.edu CP0_Config1_DL = Param.Unsigned(0,"No Description") 2115222Sksewell@umich.edu CP0_Config1_DA = Param.Unsigned(0,"No Description") 2125222Sksewell@umich.edu CP0_Config1_C2 = Param.Bool(False,"No Description") 2135222Sksewell@umich.edu CP0_Config1_MD = Param.Bool(False,"No Description") 2145222Sksewell@umich.edu CP0_Config1_PC = Param.Bool(False,"No Description") 2155222Sksewell@umich.edu CP0_Config1_WR = Param.Bool(False,"No Description") 2165222Sksewell@umich.edu CP0_Config1_CA = Param.Bool(False,"No Description") 2175222Sksewell@umich.edu CP0_Config1_EP = Param.Bool(False,"No Description") 2185222Sksewell@umich.edu CP0_Config1_FP = Param.Bool(False,"FPU Implemented?") 2195222Sksewell@umich.edu CP0_Config2_M = Param.Bool(False,"Config3 Implemented?") 2205222Sksewell@umich.edu CP0_Config2_TU = Param.Unsigned(0,"No Description") 2215222Sksewell@umich.edu CP0_Config2_TS = Param.Unsigned(0,"No Description") 2225222Sksewell@umich.edu CP0_Config2_TL = Param.Unsigned(0,"No Description") 2235222Sksewell@umich.edu CP0_Config2_TA = Param.Unsigned(0,"No Description") 2245222Sksewell@umich.edu CP0_Config2_SU = Param.Unsigned(0,"No Description") 2255222Sksewell@umich.edu CP0_Config2_SS = Param.Unsigned(0,"No Description") 2265222Sksewell@umich.edu CP0_Config2_SL = Param.Unsigned(0,"No Description") 2275222Sksewell@umich.edu CP0_Config2_SA = Param.Unsigned(0,"No Description") 2285222Sksewell@umich.edu CP0_Config3_M = Param.Bool(False,"Config4 Implemented?") 2295222Sksewell@umich.edu CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?") 2305222Sksewell@umich.edu CP0_Config3_LPA = Param.Bool(False,"No Description") 2315222Sksewell@umich.edu CP0_Config3_VEIC = Param.Bool(False,"No Description") 2325222Sksewell@umich.edu CP0_Config3_VInt = Param.Bool(False,"No Description") 2335222Sksewell@umich.edu CP0_Config3_SP = Param.Bool(False,"No Description") 2345222Sksewell@umich.edu CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?") 2355222Sksewell@umich.edu CP0_Config3_SM = Param.Bool(False,"No Description") 2365222Sksewell@umich.edu CP0_Config3_TL = Param.Bool(False,"No Description") 2375222Sksewell@umich.edu CP0_WatchHi_M = Param.Bool(False,"No Description") 2385222Sksewell@umich.edu CP0_PerfCtr_M = Param.Bool(False,"No Description") 2395222Sksewell@umich.edu CP0_PerfCtr_W = Param.Bool(False,"No Description") 2405222Sksewell@umich.edu CP0_PRId = Param.Unsigned(0,"CP0 Status Register") 2415222Sksewell@umich.edu CP0_Config = Param.Unsigned(0,"CP0 Config Register") 2425222Sksewell@umich.edu CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register") 2435222Sksewell@umich.edu CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register") 2445222Sksewell@umich.edu CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register") 245