BaseCPU.py revision 4486
14486Sbinkertn@umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 24486Sbinkertn@umich.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 54486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 64486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 74486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 84486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 114486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 124486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 134486Sbinkertn@umich.edu# this software without specific prior written permission. 144486Sbinkertn@umich.edu# 154486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# Authors: Nathan Binkert 284486Sbinkertn@umich.edu 293102SN/Afrom m5.SimObject import SimObject 303102SN/Afrom m5.params import * 313102SN/Afrom m5.proxy import * 322667SN/Afrom m5 import build_env 332998SN/Afrom Bus import Bus 343584SN/Aimport sys 352667SN/A 364486Sbinkertn@umich.eduif build_env['FULL_SYSTEM']: 374486Sbinkertn@umich.edu if build_env['TARGET_ISA'] == 'alpha': 384486Sbinkertn@umich.edu from AlphaTLB import AlphaDTB, AlphaITB 394486Sbinkertn@umich.edu 404486Sbinkertn@umich.edu if build_env['TARGET_ISA'] == 'sparc': 414486Sbinkertn@umich.edu from SparcTLB import SparcDTB, SparcITB 424486Sbinkertn@umich.edu 431692SN/Aclass BaseCPU(SimObject): 441366SN/A type = 'BaseCPU' 451310SN/A abstract = True 461310SN/A 472901SN/A system = Param.System(Parent.any, "system object") 483170SN/A cpu_id = Param.Int("CPU identifier") 493170SN/A 501530SN/A if build_env['FULL_SYSTEM']: 513620SN/A do_quiesce = Param.Bool(True, "enable quiesce instructions") 523617SN/A do_checkpoint_insts = Param.Bool(True, 533617SN/A "enable checkpoint pseudo instructions") 543617SN/A do_statistics_insts = Param.Bool(True, 553617SN/A "enable statistics pseudo instructions") 563617SN/A 573584SN/A if build_env['TARGET_ISA'] == 'sparc': 583584SN/A dtb = Param.SparcDTB(SparcDTB(), "Data TLB") 593584SN/A itb = Param.SparcITB(SparcITB(), "Instruction TLB") 603584SN/A elif build_env['TARGET_ISA'] == 'alpha': 613584SN/A dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") 623584SN/A itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") 633584SN/A else: 643584SN/A print "Unknown architecture, can't pick TLBs" 653584SN/A sys.exit(1) 661445SN/A else: 671445SN/A workload = VectorParam.Process("processes to run") 681310SN/A 691310SN/A max_insts_all_threads = Param.Counter(0, 701310SN/A "terminate when all threads have reached this inst count") 711310SN/A max_insts_any_thread = Param.Counter(0, 721310SN/A "terminate when any thread reaches this inst count") 731310SN/A max_loads_all_threads = Param.Counter(0, 741310SN/A "terminate when all threads have reached this load count") 751310SN/A max_loads_any_thread = Param.Counter(0, 761310SN/A "terminate when any thread reaches this load count") 773878SN/A progress_interval = Param.Tick(0, 783878SN/A "interval to print out the progress message") 791310SN/A 801369SN/A defer_registration = Param.Bool(False, 811310SN/A "defer registration with system (for sampling)") 821634SN/A 834167SN/A clock = Param.Clock('1t', "clock speed") 844167SN/A phase = Param.Latency('0ns', "clock phase") 852998SN/A 862998SN/A _mem_ports = [] 872998SN/A 882998SN/A def connectMemPorts(self, bus): 892998SN/A for p in self._mem_ports: 902998SN/A exec('self.%s = bus.port' % p) 912998SN/A 922998SN/A def addPrivateSplitL1Caches(self, ic, dc): 932998SN/A assert(len(self._mem_ports) == 2) 942998SN/A self.icache = ic 952998SN/A self.dcache = dc 962998SN/A self.icache_port = ic.cpu_side 972998SN/A self.dcache_port = dc.cpu_side 982998SN/A self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 992998SN/A 1002998SN/A def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 1012998SN/A self.addPrivateSplitL1Caches(ic, dc) 1022998SN/A self.toL2Bus = Bus() 1032998SN/A self.connectMemPorts(self.toL2Bus) 1042998SN/A self.l2cache = l2c 1053017SN/A self.l2cache.cpu_side = self.toL2Bus.port 1062998SN/A self._mem_ports = ['l2cache.mem_side'] 107