BaseCPU.py revision 3878
12131SN/Afrom m5.SimObject import SimObject 25268Sksewell@umich.edufrom m5.params import * 35224Sksewell@umich.edufrom m5.proxy import * 45224Sksewell@umich.edufrom m5 import build_env 52131SN/Afrom AlphaTLB import AlphaDTB, AlphaITB 65224Sksewell@umich.edufrom SparcTLB import SparcDTB, SparcITB 75224Sksewell@umich.edufrom Bus import Bus 85224Sksewell@umich.eduimport sys 95224Sksewell@umich.edu 105224Sksewell@umich.educlass BaseCPU(SimObject): 115224Sksewell@umich.edu type = 'BaseCPU' 125224Sksewell@umich.edu abstract = True 135224Sksewell@umich.edu 145224Sksewell@umich.edu system = Param.System(Parent.any, "system object") 155224Sksewell@umich.edu cpu_id = Param.Int("CPU identifier") 162131SN/A 175224Sksewell@umich.edu if build_env['FULL_SYSTEM']: 185224Sksewell@umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 195224Sksewell@umich.edu do_checkpoint_insts = Param.Bool(True, 205224Sksewell@umich.edu "enable checkpoint pseudo instructions") 215224Sksewell@umich.edu do_statistics_insts = Param.Bool(True, 225224Sksewell@umich.edu "enable statistics pseudo instructions") 235224Sksewell@umich.edu 245224Sksewell@umich.edu if build_env['TARGET_ISA'] == 'sparc': 255224Sksewell@umich.edu dtb = Param.SparcDTB(SparcDTB(), "Data TLB") 265224Sksewell@umich.edu itb = Param.SparcITB(SparcITB(), "Instruction TLB") 275224Sksewell@umich.edu elif build_env['TARGET_ISA'] == 'alpha': 282665Ssaidi@eecs.umich.edu dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") 295224Sksewell@umich.edu itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") 305224Sksewell@umich.edu else: 315222Sksewell@umich.edu print "Unknown architecture, can't pick TLBs" 322131SN/A sys.exit(1) 332131SN/A else: 342239SN/A workload = VectorParam.Process("processes to run") 352239SN/A 362131SN/A max_insts_all_threads = Param.Counter(0, 372131SN/A "terminate when all threads have reached this inst count") 382447SN/A max_insts_any_thread = Param.Counter(0, 392447SN/A "terminate when any thread reaches this inst count") 402447SN/A max_loads_all_threads = Param.Counter(0, 416378Sgblack@eecs.umich.edu "terminate when all threads have reached this load count") 422447SN/A max_loads_any_thread = Param.Counter(0, 432131SN/A "terminate when any thread reaches this load count") 448566Sgblack@eecs.umich.edu progress_interval = Param.Tick(0, 452131SN/A "interval to print out the progress message") 462447SN/A 472447SN/A defer_registration = Param.Bool(False, 482447SN/A "defer registration with system (for sampling)") 492131SN/A 508566Sgblack@eecs.umich.edu clock = Param.Clock(Parent.clock, "clock speed") 518566Sgblack@eecs.umich.edu phase = Param.Latency("0ns", "clock phase") 528566Sgblack@eecs.umich.edu 538566Sgblack@eecs.umich.edu _mem_ports = [] 548566Sgblack@eecs.umich.edu 558566Sgblack@eecs.umich.edu def connectMemPorts(self, bus): 568566Sgblack@eecs.umich.edu for p in self._mem_ports: 576379Sgblack@eecs.umich.edu exec('self.%s = bus.port' % p) 586379Sgblack@eecs.umich.edu 596379Sgblack@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc): 606379Sgblack@eecs.umich.edu assert(len(self._mem_ports) == 2) 616379Sgblack@eecs.umich.edu self.icache = ic 622447SN/A self.dcache = dc 637678Sgblack@eecs.umich.edu self.icache_port = ic.cpu_side 647678Sgblack@eecs.umich.edu self.dcache_port = dc.cpu_side 657678Sgblack@eecs.umich.edu self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 666378Sgblack@eecs.umich.edu 676378Sgblack@eecs.umich.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 682447SN/A self.addPrivateSplitL1Caches(ic, dc) 692131SN/A self.toL2Bus = Bus() 702131SN/A self.connectMemPorts(self.toL2Bus) 718566Sgblack@eecs.umich.edu self.l2cache = l2c 728566Sgblack@eecs.umich.edu self.l2cache.cpu_side = self.toL2Bus.port 732131SN/A self._mem_ports = ['l2cache.mem_side'] 748566Sgblack@eecs.umich.edu