BaseCPU.py revision 1634
110663SN/Asimobj BaseCPU(SimObject): 210663SN/A type = 'BaseCPU' 310663SN/A abstract = True 410663SN/A icache = Param.BaseMem(NULL, "L1 instruction cache object") 510663SN/A dcache = Param.BaseMem(NULL, "L1 data cache object") 610663SN/A 710663SN/A if build_env['FULL_SYSTEM']: 810663SN/A dtb = Param.AlphaDTB("Data TLB") 910663SN/A itb = Param.AlphaITB("Instruction TLB") 1010663SN/A mem = Param.FunctionalMemory("memory") 1110663SN/A system = Param.BaseSystem(parent.any, "system object") 1210663SN/A else: 1310663SN/A workload = VectorParam.Process("processes to run") 1410663SN/A 1510663SN/A max_insts_all_threads = Param.Counter(0, 1610663SN/A "terminate when all threads have reached this inst count") 1710663SN/A max_insts_any_thread = Param.Counter(0, 1810663SN/A "terminate when any thread reaches this inst count") 1910663SN/A max_loads_all_threads = Param.Counter(0, 2010663SN/A "terminate when all threads have reached this load count") 2110663SN/A max_loads_any_thread = Param.Counter(0, 2210663SN/A "terminate when any thread reaches this load count") 2310663SN/A 2410663SN/A defer_registration = Param.Bool(False, 2510663SN/A "defer registration with system (for sampling)") 2610663SN/A 2710663SN/A cycle_time = Param.ClockPeriod(parent.frequency, "clock speed") 2810663SN/A