BaseCPU.py revision 12440
112276Sanouk.vanlaer@arm.com# Copyright (c) 2012-2013, 2015-2017 ARM Limited 28839Sandreas.hansson@arm.com# All rights reserved. 38839Sandreas.hansson@arm.com# 48839Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58839Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68839Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78839Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88839Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98839Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108839Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118839Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128839Sandreas.hansson@arm.com# 135335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 147897Shestness@cs.utexas.edu# Copyright (c) 2011 Regents of the University of California 154486Sbinkertn@umich.edu# All rights reserved. 164486Sbinkertn@umich.edu# 174486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 184486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 194486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 204486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 214486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 224486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 234486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 244486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 254486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 264486Sbinkertn@umich.edu# this software without specific prior written permission. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394486Sbinkertn@umich.edu# 404486Sbinkertn@umich.edu# Authors: Nathan Binkert 417897Shestness@cs.utexas.edu# Rick Strong 428839Sandreas.hansson@arm.com# Andreas Hansson 434486Sbinkertn@umich.edu 446654Snate@binkert.orgimport sys 456654Snate@binkert.org 4611988Sandreas.sandberg@arm.comfrom m5.SimObject import * 476654Snate@binkert.orgfrom m5.defines import buildEnv 483102SN/Afrom m5.params import * 493102SN/Afrom m5.proxy import * 506654Snate@binkert.org 5110720Sandreas.hansson@arm.comfrom XBar import L2XBar 524776Sgblack@eecs.umich.edufrom InstTracer import InstTracer 5310663SAli.Saidi@ARM.comfrom CPUTracers import ExeTracer 546654Snate@binkert.orgfrom MemObject import MemObject 559793Sakash.bagdia@arm.comfrom ClockDomain import * 562667SN/A 574776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 584776Sgblack@eecs.umich.edu 596654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 6012434Sgabeblack@google.com from AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB 618745Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 629384SAndreas.Sandberg@arm.com from AlphaISA import AlphaISA 6312325Sandreas.sandberg@arm.com default_isa_class = AlphaISA 646654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 6512434Sgabeblack@google.com from SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB 668745Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 679384SAndreas.Sandberg@arm.com from SparcISA import SparcISA 6812325Sandreas.sandberg@arm.com default_isa_class = SparcISA 696654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 7012434Sgabeblack@google.com from X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB 718745Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 729384SAndreas.Sandberg@arm.com from X86ISA import X86ISA 7312325Sandreas.sandberg@arm.com default_isa_class = X86ISA 746654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 7512434Sgabeblack@google.com from MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB 768745Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 779384SAndreas.Sandberg@arm.com from MipsISA import MipsISA 7812325Sandreas.sandberg@arm.com default_isa_class = MipsISA 796654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 8012434Sgabeblack@google.com from ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB 8112434Sgabeblack@google.com from ArmTLB import ArmStage2IMMU, ArmStage2DMMU 828745Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 839384SAndreas.Sandberg@arm.com from ArmISA import ArmISA 8412325Sandreas.sandberg@arm.com default_isa_class = ArmISA 856691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'power': 8612434Sgabeblack@google.com from PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB 878745Sgblack@eecs.umich.edu from PowerInterrupts import PowerInterrupts 889384SAndreas.Sandberg@arm.com from PowerISA import PowerISA 8912325Sandreas.sandberg@arm.com default_isa_class = PowerISA 9011723Sar4jc@virginia.eduelif buildEnv['TARGET_ISA'] == 'riscv': 9112434Sgabeblack@google.com from RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB 9211723Sar4jc@virginia.edu from RiscvInterrupts import RiscvInterrupts 9311723Sar4jc@virginia.edu from RiscvISA import RiscvISA 9412325Sandreas.sandberg@arm.com default_isa_class = RiscvISA 954486Sbinkertn@umich.edu 965529Snate@binkert.orgclass BaseCPU(MemObject): 971366SN/A type = 'BaseCPU' 981310SN/A abstract = True 999338SAndreas.Sandberg@arm.com cxx_header = "cpu/base.hh" 1009254SAndreas.Sandberg@arm.com 10111988Sandreas.sandberg@arm.com cxx_exports = [ 10211988Sandreas.sandberg@arm.com PyBindMethod("switchOut"), 10311988Sandreas.sandberg@arm.com PyBindMethod("takeOverFrom"), 10411988Sandreas.sandberg@arm.com PyBindMethod("switchedOut"), 10511988Sandreas.sandberg@arm.com PyBindMethod("flushTLBs"), 10611988Sandreas.sandberg@arm.com PyBindMethod("totalInsts"), 10711988Sandreas.sandberg@arm.com PyBindMethod("scheduleInstStop"), 10811988Sandreas.sandberg@arm.com PyBindMethod("scheduleLoadStop"), 10911988Sandreas.sandberg@arm.com PyBindMethod("getCurrentInstCount"), 11011988Sandreas.sandberg@arm.com ] 1119254SAndreas.Sandberg@arm.com 1129518SAndreas.Sandberg@ARM.com @classmethod 1139518SAndreas.Sandberg@ARM.com def memory_mode(cls): 1149518SAndreas.Sandberg@ARM.com """Which memory mode does this CPU require?""" 1159518SAndreas.Sandberg@ARM.com return 'invalid' 1169518SAndreas.Sandberg@ARM.com 1179518SAndreas.Sandberg@ARM.com @classmethod 1189518SAndreas.Sandberg@ARM.com def require_caches(cls): 1199518SAndreas.Sandberg@ARM.com """Does the CPU model require caches? 1209518SAndreas.Sandberg@ARM.com 1219518SAndreas.Sandberg@ARM.com Some CPU models might make assumptions that require them to 1229518SAndreas.Sandberg@ARM.com have caches. 1239518SAndreas.Sandberg@ARM.com """ 1249518SAndreas.Sandberg@ARM.com return False 1259518SAndreas.Sandberg@ARM.com 1269518SAndreas.Sandberg@ARM.com @classmethod 1279518SAndreas.Sandberg@ARM.com def support_take_over(cls): 1289518SAndreas.Sandberg@ARM.com """Does the CPU model support CPU takeOverFrom?""" 1299518SAndreas.Sandberg@ARM.com return False 1309518SAndreas.Sandberg@ARM.com 1319254SAndreas.Sandberg@arm.com def takeOverFrom(self, old_cpu): 1329254SAndreas.Sandberg@arm.com self._ccObject.takeOverFrom(old_cpu._ccObject) 1339254SAndreas.Sandberg@arm.com 1349254SAndreas.Sandberg@arm.com 1352901SN/A system = Param.System(Parent.any, "system object") 1365712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 13710190Sakash.bagdia@arm.com socket_id = Param.Unsigned(0, "Physical Socket identifier") 1385529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 13912276Sanouk.vanlaer@arm.com pwr_gating_latency = Param.Cycles(300, 14012276Sanouk.vanlaer@arm.com "Latency to enter power gating state when all contexts are suspended") 1415529Snate@binkert.org 14212277Sjose.marinho@arm.com power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\ 14312277Sjose.marinho@arm.com "to the OFF power state after all thread are disabled for "\ 14412277Sjose.marinho@arm.com "pwr_gating_latency cycles") 14512277Sjose.marinho@arm.com 1465529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 1479161Sandreas.hansson@arm.com function_trace_start = Param.Tick(0, "Tick to start function trace") 1485529Snate@binkert.org 1495821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1503170SN/A 15111877Sbrandon.potter@amd.com syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry") 15211877Sbrandon.potter@amd.com 1535780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 1545780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 1555780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 1565780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 1575780Ssteve.reinhardt@amd.com 1588784Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 1598784Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 1608784Sgblack@eecs.umich.edu 16112122Sjose.marinho@arm.com wait_for_remote_gdb = Param.Bool(False, 16212122Sjose.marinho@arm.com "Wait for a remote GDB connection"); 16312122Sjose.marinho@arm.com 1648793Sgblack@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 1651310SN/A 16612434Sgabeblack@google.com dtb = Param.BaseTLB(ArchDTB(), "Data TLB") 16712434Sgabeblack@google.com itb = Param.BaseTLB(ArchITB(), "Instruction TLB") 1686654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'sparc': 16911150Smitch.hayenga@arm.com interrupts = VectorParam.SparcInterrupts( 17011150Smitch.hayenga@arm.com [], "Interrupt Controller") 17112325Sandreas.sandberg@arm.com isa = VectorParam.SparcISA([], "ISA instance") 1726654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'alpha': 17311150Smitch.hayenga@arm.com interrupts = VectorParam.AlphaInterrupts( 17411150Smitch.hayenga@arm.com [], "Interrupt Controller") 17512325Sandreas.sandberg@arm.com isa = VectorParam.AlphaISA([], "ISA instance") 1766654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 17711150Smitch.hayenga@arm.com interrupts = VectorParam.X86LocalApic([], "Interrupt Controller") 17812325Sandreas.sandberg@arm.com isa = VectorParam.X86ISA([], "ISA instance") 1796654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 18011150Smitch.hayenga@arm.com interrupts = VectorParam.MipsInterrupts( 18111150Smitch.hayenga@arm.com [], "Interrupt Controller") 18212325Sandreas.sandberg@arm.com isa = VectorParam.MipsISA([], "ISA instance") 1836654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 18410037SARM gem5 Developers istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") 18510037SARM gem5 Developers dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") 18611150Smitch.hayenga@arm.com interrupts = VectorParam.ArmInterrupts( 18711150Smitch.hayenga@arm.com [], "Interrupt Controller") 18812325Sandreas.sandberg@arm.com isa = VectorParam.ArmISA([], "ISA instance") 1896691Stjones1@inf.ed.ac.uk elif buildEnv['TARGET_ISA'] == 'power': 1906691Stjones1@inf.ed.ac.uk UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 19111150Smitch.hayenga@arm.com interrupts = VectorParam.PowerInterrupts( 19211150Smitch.hayenga@arm.com [], "Interrupt Controller") 19312325Sandreas.sandberg@arm.com isa = VectorParam.PowerISA([], "ISA instance") 19411723Sar4jc@virginia.edu elif buildEnv['TARGET_ISA'] == 'riscv': 19511723Sar4jc@virginia.edu interrupts = VectorParam.RiscvInterrupts( 19611723Sar4jc@virginia.edu [], "Interrupt Controller") 19712325Sandreas.sandberg@arm.com isa = VectorParam.RiscvISA([], "ISA instance") 1984997Sgblack@eecs.umich.edu else: 1994997Sgblack@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 2006654Snate@binkert.org buildEnv['TARGET_ISA'] 2014997Sgblack@eecs.umich.edu sys.exit(1) 2024997Sgblack@eecs.umich.edu 2031310SN/A max_insts_all_threads = Param.Counter(0, 2041310SN/A "terminate when all threads have reached this inst count") 2051310SN/A max_insts_any_thread = Param.Counter(0, 2061310SN/A "terminate when any thread reaches this inst count") 2079647Sdam.sunwoo@arm.com simpoint_start_insts = VectorParam.Counter([], 2089647Sdam.sunwoo@arm.com "starting instruction counts of simpoints") 2091310SN/A max_loads_all_threads = Param.Counter(0, 2101310SN/A "terminate when all threads have reached this load count") 2111310SN/A max_loads_any_thread = Param.Counter(0, 2121310SN/A "terminate when any thread reaches this load count") 2139180Sandreas.hansson@arm.com progress_interval = Param.Frequency('0Hz', 2149180Sandreas.hansson@arm.com "frequency to print out the progress message") 2151310SN/A 2169433SAndreas.Sandberg@ARM.com switched_out = Param.Bool(False, 2179433SAndreas.Sandberg@ARM.com "Leave the CPU switched out after startup (used when switching " \ 2189433SAndreas.Sandberg@ARM.com "between CPU models)") 2191634SN/A 2204776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 2214776Sgblack@eecs.umich.edu 2228839Sandreas.hansson@arm.com icache_port = MasterPort("Instruction Port") 2238839Sandreas.hansson@arm.com dcache_port = MasterPort("Data Port") 2248707Sandreas.hansson@arm.com _cached_ports = ['icache_port', 'dcache_port'] 2258707Sandreas.hansson@arm.com 2268756Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2278707Sandreas.hansson@arm.com _cached_ports += ["itb.walker.port", "dtb.walker.port"] 2287876Sgblack@eecs.umich.edu 2298839Sandreas.hansson@arm.com _uncached_slave_ports = [] 2308839Sandreas.hansson@arm.com _uncached_master_ports = [] 2318745Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 23211150Smitch.hayenga@arm.com _uncached_slave_ports += ["interrupts[0].pio", 23311150Smitch.hayenga@arm.com "interrupts[0].int_slave"] 23411150Smitch.hayenga@arm.com _uncached_master_ports += ["interrupts[0].int_master"] 2352998SN/A 2368863Snilay@cs.wisc.edu def createInterruptController(self): 2378863Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == 'sparc': 23811150Smitch.hayenga@arm.com self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)] 2398863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'alpha': 24011150Smitch.hayenga@arm.com self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)] 2418863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'x86': 2429793Sakash.bagdia@arm.com self.apic_clk_domain = DerivedClockDomain(clk_domain = 2439793Sakash.bagdia@arm.com Parent.clk_domain, 2449793Sakash.bagdia@arm.com clk_divider = 16) 24511150Smitch.hayenga@arm.com self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain, 2469544Sandreas.hansson@arm.com pio_addr=0x2000000000000000) 24711150Smitch.hayenga@arm.com for i in xrange(self.numThreads)] 2489544Sandreas.hansson@arm.com _localApic = self.interrupts 2498863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'mips': 25011150Smitch.hayenga@arm.com self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)] 2518863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'arm': 25211150Smitch.hayenga@arm.com self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)] 2538863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'power': 25411150Smitch.hayenga@arm.com self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)] 25511723Sar4jc@virginia.edu elif buildEnv['TARGET_ISA'] == 'riscv': 25611723Sar4jc@virginia.edu self.interrupts = \ 25711723Sar4jc@virginia.edu [RiscvInterrupts() for i in xrange(self.numThreads)] 2588863Snilay@cs.wisc.edu else: 2598863Snilay@cs.wisc.edu print "Don't know what Interrupt Controller to use for ISA %s" % \ 2608863Snilay@cs.wisc.edu buildEnv['TARGET_ISA'] 2618863Snilay@cs.wisc.edu sys.exit(1) 2628863Snilay@cs.wisc.edu 2637876Sgblack@eecs.umich.edu def connectCachedPorts(self, bus): 2647876Sgblack@eecs.umich.edu for p in self._cached_ports: 2658839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2667404SAli.Saidi@ARM.com 2677876Sgblack@eecs.umich.edu def connectUncachedPorts(self, bus): 2688839Sandreas.hansson@arm.com for p in self._uncached_slave_ports: 2698839Sandreas.hansson@arm.com exec('self.%s = bus.master' % p) 2708839Sandreas.hansson@arm.com for p in self._uncached_master_ports: 2718839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2727876Sgblack@eecs.umich.edu 2737876Sgblack@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 2747876Sgblack@eecs.umich.edu self.connectCachedPorts(cached_bus) 2757876Sgblack@eecs.umich.edu if not uncached_bus: 2767876Sgblack@eecs.umich.edu uncached_bus = cached_bus 2777876Sgblack@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 2782998SN/A 2797868Sgblack@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 2802998SN/A self.icache = ic 2812998SN/A self.dcache = dc 2822998SN/A self.icache_port = ic.cpu_side 2832998SN/A self.dcache_port = dc.cpu_side 2847876Sgblack@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 2858796Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2868796Sgblack@eecs.umich.edu if iwc and dwc: 2878796Sgblack@eecs.umich.edu self.itb_walker_cache = iwc 2888796Sgblack@eecs.umich.edu self.dtb_walker_cache = dwc 28910717Sandreas.hansson@arm.com self.itb.walker.port = iwc.cpu_side 29010717Sandreas.hansson@arm.com self.dtb.walker.port = dwc.cpu_side 2918796Sgblack@eecs.umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 2928796Sgblack@eecs.umich.edu "dtb_walker_cache.mem_side"] 2938796Sgblack@eecs.umich.edu else: 2948796Sgblack@eecs.umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 2958887Sgeoffrey.blake@arm.com 2968809Sgblack@eecs.umich.edu # Checker doesn't need its own tlb caches because it does 2978809Sgblack@eecs.umich.edu # functional accesses only 2988887Sgeoffrey.blake@arm.com if self.checker != NULL: 2998809Sgblack@eecs.umich.edu self._cached_ports += ["checker.itb.walker.port", \ 3008809Sgblack@eecs.umich.edu "checker.dtb.walker.port"] 3012998SN/A 30212440Sxiaoyuma@google.com def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None, 30312440Sxiaoyuma@google.com xbar=None): 3047868Sgblack@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 30512440Sxiaoyuma@google.com self.toL2Bus = xbar if xbar else L2XBar() 3067876Sgblack@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 3072998SN/A self.l2cache = l2c 3088839Sandreas.hansson@arm.com self.toL2Bus.master = self.l2cache.cpu_side 3097876Sgblack@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 3108887Sgeoffrey.blake@arm.com 3119384SAndreas.Sandberg@arm.com def createThreads(self): 31212325Sandreas.sandberg@arm.com # If no ISAs have been created, assume that the user wants the 31312325Sandreas.sandberg@arm.com # default ISA. 31412325Sandreas.sandberg@arm.com if len(self.isa) == 0: 31512325Sandreas.sandberg@arm.com self.isa = [ default_isa_class() for i in xrange(self.numThreads) ] 31612325Sandreas.sandberg@arm.com else: 31712325Sandreas.sandberg@arm.com if len(self.isa) != int(self.numThreads): 31812325Sandreas.sandberg@arm.com raise RuntimeError("Number of ISA instances doesn't " 31912325Sandreas.sandberg@arm.com "match thread count") 3209384SAndreas.Sandberg@arm.com if self.checker != NULL: 3219384SAndreas.Sandberg@arm.com self.checker.createThreads() 3229384SAndreas.Sandberg@arm.com 3238887Sgeoffrey.blake@arm.com def addCheckerCpu(self): 3248887Sgeoffrey.blake@arm.com pass 325