BaseCPU.py revision 12325
112276Sanouk.vanlaer@arm.com# Copyright (c) 2012-2013, 2015-2017 ARM Limited 28839Sandreas.hansson@arm.com# All rights reserved. 38839Sandreas.hansson@arm.com# 48839Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58839Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68839Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78839Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88839Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98839Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108839Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118839Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128839Sandreas.hansson@arm.com# 135335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 147897Shestness@cs.utexas.edu# Copyright (c) 2011 Regents of the University of California 154486Sbinkertn@umich.edu# All rights reserved. 164486Sbinkertn@umich.edu# 174486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 184486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 194486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 204486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 214486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 224486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 234486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 244486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 254486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 264486Sbinkertn@umich.edu# this software without specific prior written permission. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394486Sbinkertn@umich.edu# 404486Sbinkertn@umich.edu# Authors: Nathan Binkert 417897Shestness@cs.utexas.edu# Rick Strong 428839Sandreas.hansson@arm.com# Andreas Hansson 434486Sbinkertn@umich.edu 446654Snate@binkert.orgimport sys 456654Snate@binkert.org 4611988Sandreas.sandberg@arm.comfrom m5.SimObject import * 476654Snate@binkert.orgfrom m5.defines import buildEnv 483102SN/Afrom m5.params import * 493102SN/Afrom m5.proxy import * 506654Snate@binkert.org 5110720Sandreas.hansson@arm.comfrom XBar import L2XBar 524776Sgblack@eecs.umich.edufrom InstTracer import InstTracer 5310663SAli.Saidi@ARM.comfrom CPUTracers import ExeTracer 546654Snate@binkert.orgfrom MemObject import MemObject 559793Sakash.bagdia@arm.comfrom ClockDomain import * 562667SN/A 574776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 584776Sgblack@eecs.umich.edu 596654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 606023Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 618745Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 629384SAndreas.Sandberg@arm.com from AlphaISA import AlphaISA 6312325Sandreas.sandberg@arm.com default_isa_class = AlphaISA 646654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 656022Sgblack@eecs.umich.edu from SparcTLB import SparcTLB 668745Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 679384SAndreas.Sandberg@arm.com from SparcISA import SparcISA 6812325Sandreas.sandberg@arm.com default_isa_class = SparcISA 696654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 706022Sgblack@eecs.umich.edu from X86TLB import X86TLB 718745Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 729384SAndreas.Sandberg@arm.com from X86ISA import X86ISA 7312325Sandreas.sandberg@arm.com default_isa_class = X86ISA 746654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 756022Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 768745Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 779384SAndreas.Sandberg@arm.com from MipsISA import MipsISA 7812325Sandreas.sandberg@arm.com default_isa_class = MipsISA 796654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 8010037SARM gem5 Developers from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU 818745Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 829384SAndreas.Sandberg@arm.com from ArmISA import ArmISA 8312325Sandreas.sandberg@arm.com default_isa_class = ArmISA 846691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'power': 856691Stjones1@inf.ed.ac.uk from PowerTLB import PowerTLB 868745Sgblack@eecs.umich.edu from PowerInterrupts import PowerInterrupts 879384SAndreas.Sandberg@arm.com from PowerISA import PowerISA 8812325Sandreas.sandberg@arm.com default_isa_class = PowerISA 8911723Sar4jc@virginia.eduelif buildEnv['TARGET_ISA'] == 'riscv': 9011723Sar4jc@virginia.edu from RiscvTLB import RiscvTLB 9111723Sar4jc@virginia.edu from RiscvInterrupts import RiscvInterrupts 9211723Sar4jc@virginia.edu from RiscvISA import RiscvISA 9312325Sandreas.sandberg@arm.com default_isa_class = RiscvISA 944486Sbinkertn@umich.edu 955529Snate@binkert.orgclass BaseCPU(MemObject): 961366SN/A type = 'BaseCPU' 971310SN/A abstract = True 989338SAndreas.Sandberg@arm.com cxx_header = "cpu/base.hh" 999254SAndreas.Sandberg@arm.com 10011988Sandreas.sandberg@arm.com cxx_exports = [ 10111988Sandreas.sandberg@arm.com PyBindMethod("switchOut"), 10211988Sandreas.sandberg@arm.com PyBindMethod("takeOverFrom"), 10311988Sandreas.sandberg@arm.com PyBindMethod("switchedOut"), 10411988Sandreas.sandberg@arm.com PyBindMethod("flushTLBs"), 10511988Sandreas.sandberg@arm.com PyBindMethod("totalInsts"), 10611988Sandreas.sandberg@arm.com PyBindMethod("scheduleInstStop"), 10711988Sandreas.sandberg@arm.com PyBindMethod("scheduleLoadStop"), 10811988Sandreas.sandberg@arm.com PyBindMethod("getCurrentInstCount"), 10911988Sandreas.sandberg@arm.com ] 1109254SAndreas.Sandberg@arm.com 1119518SAndreas.Sandberg@ARM.com @classmethod 1129518SAndreas.Sandberg@ARM.com def memory_mode(cls): 1139518SAndreas.Sandberg@ARM.com """Which memory mode does this CPU require?""" 1149518SAndreas.Sandberg@ARM.com return 'invalid' 1159518SAndreas.Sandberg@ARM.com 1169518SAndreas.Sandberg@ARM.com @classmethod 1179518SAndreas.Sandberg@ARM.com def require_caches(cls): 1189518SAndreas.Sandberg@ARM.com """Does the CPU model require caches? 1199518SAndreas.Sandberg@ARM.com 1209518SAndreas.Sandberg@ARM.com Some CPU models might make assumptions that require them to 1219518SAndreas.Sandberg@ARM.com have caches. 1229518SAndreas.Sandberg@ARM.com """ 1239518SAndreas.Sandberg@ARM.com return False 1249518SAndreas.Sandberg@ARM.com 1259518SAndreas.Sandberg@ARM.com @classmethod 1269518SAndreas.Sandberg@ARM.com def support_take_over(cls): 1279518SAndreas.Sandberg@ARM.com """Does the CPU model support CPU takeOverFrom?""" 1289518SAndreas.Sandberg@ARM.com return False 1299518SAndreas.Sandberg@ARM.com 1309254SAndreas.Sandberg@arm.com def takeOverFrom(self, old_cpu): 1319254SAndreas.Sandberg@arm.com self._ccObject.takeOverFrom(old_cpu._ccObject) 1329254SAndreas.Sandberg@arm.com 1339254SAndreas.Sandberg@arm.com 1342901SN/A system = Param.System(Parent.any, "system object") 1355712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 13610190Sakash.bagdia@arm.com socket_id = Param.Unsigned(0, "Physical Socket identifier") 1375529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 13812276Sanouk.vanlaer@arm.com pwr_gating_latency = Param.Cycles(300, 13912276Sanouk.vanlaer@arm.com "Latency to enter power gating state when all contexts are suspended") 1405529Snate@binkert.org 14112277Sjose.marinho@arm.com power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\ 14212277Sjose.marinho@arm.com "to the OFF power state after all thread are disabled for "\ 14312277Sjose.marinho@arm.com "pwr_gating_latency cycles") 14412277Sjose.marinho@arm.com 1455529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 1469161Sandreas.hansson@arm.com function_trace_start = Param.Tick(0, "Tick to start function trace") 1475529Snate@binkert.org 1485821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1493170SN/A 15011877Sbrandon.potter@amd.com syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry") 15111877Sbrandon.potter@amd.com 1525780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 1535780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 1545780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 1555780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 1565780Ssteve.reinhardt@amd.com 1578784Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 1588784Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 1598784Sgblack@eecs.umich.edu 16012122Sjose.marinho@arm.com wait_for_remote_gdb = Param.Bool(False, 16112122Sjose.marinho@arm.com "Wait for a remote GDB connection"); 16212122Sjose.marinho@arm.com 1638793Sgblack@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 1641310SN/A 1656654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'sparc': 1666022Sgblack@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 1676022Sgblack@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 16811150Smitch.hayenga@arm.com interrupts = VectorParam.SparcInterrupts( 16911150Smitch.hayenga@arm.com [], "Interrupt Controller") 17012325Sandreas.sandberg@arm.com isa = VectorParam.SparcISA([], "ISA instance") 1716654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'alpha': 1726023Snate@binkert.org dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 1736023Snate@binkert.org itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 17411150Smitch.hayenga@arm.com interrupts = VectorParam.AlphaInterrupts( 17511150Smitch.hayenga@arm.com [], "Interrupt Controller") 17612325Sandreas.sandberg@arm.com isa = VectorParam.AlphaISA([], "ISA instance") 1776654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 1786022Sgblack@eecs.umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 1796022Sgblack@eecs.umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 18011150Smitch.hayenga@arm.com interrupts = VectorParam.X86LocalApic([], "Interrupt Controller") 18112325Sandreas.sandberg@arm.com isa = VectorParam.X86ISA([], "ISA instance") 1826654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 1836022Sgblack@eecs.umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1846022Sgblack@eecs.umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 18511150Smitch.hayenga@arm.com interrupts = VectorParam.MipsInterrupts( 18611150Smitch.hayenga@arm.com [], "Interrupt Controller") 18712325Sandreas.sandberg@arm.com isa = VectorParam.MipsISA([], "ISA instance") 1886654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 1896116Snate@binkert.org dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1906116Snate@binkert.org itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 19110037SARM gem5 Developers istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") 19210037SARM gem5 Developers dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") 19311150Smitch.hayenga@arm.com interrupts = VectorParam.ArmInterrupts( 19411150Smitch.hayenga@arm.com [], "Interrupt Controller") 19512325Sandreas.sandberg@arm.com isa = VectorParam.ArmISA([], "ISA instance") 1966691Stjones1@inf.ed.ac.uk elif buildEnv['TARGET_ISA'] == 'power': 1976691Stjones1@inf.ed.ac.uk UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1986691Stjones1@inf.ed.ac.uk dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1996691Stjones1@inf.ed.ac.uk itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 20011150Smitch.hayenga@arm.com interrupts = VectorParam.PowerInterrupts( 20111150Smitch.hayenga@arm.com [], "Interrupt Controller") 20212325Sandreas.sandberg@arm.com isa = VectorParam.PowerISA([], "ISA instance") 20311723Sar4jc@virginia.edu elif buildEnv['TARGET_ISA'] == 'riscv': 20411723Sar4jc@virginia.edu dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB") 20511723Sar4jc@virginia.edu itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB") 20611723Sar4jc@virginia.edu interrupts = VectorParam.RiscvInterrupts( 20711723Sar4jc@virginia.edu [], "Interrupt Controller") 20812325Sandreas.sandberg@arm.com isa = VectorParam.RiscvISA([], "ISA instance") 2094997Sgblack@eecs.umich.edu else: 2104997Sgblack@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 2116654Snate@binkert.org buildEnv['TARGET_ISA'] 2124997Sgblack@eecs.umich.edu sys.exit(1) 2134997Sgblack@eecs.umich.edu 2141310SN/A max_insts_all_threads = Param.Counter(0, 2151310SN/A "terminate when all threads have reached this inst count") 2161310SN/A max_insts_any_thread = Param.Counter(0, 2171310SN/A "terminate when any thread reaches this inst count") 2189647Sdam.sunwoo@arm.com simpoint_start_insts = VectorParam.Counter([], 2199647Sdam.sunwoo@arm.com "starting instruction counts of simpoints") 2201310SN/A max_loads_all_threads = Param.Counter(0, 2211310SN/A "terminate when all threads have reached this load count") 2221310SN/A max_loads_any_thread = Param.Counter(0, 2231310SN/A "terminate when any thread reaches this load count") 2249180Sandreas.hansson@arm.com progress_interval = Param.Frequency('0Hz', 2259180Sandreas.hansson@arm.com "frequency to print out the progress message") 2261310SN/A 2279433SAndreas.Sandberg@ARM.com switched_out = Param.Bool(False, 2289433SAndreas.Sandberg@ARM.com "Leave the CPU switched out after startup (used when switching " \ 2299433SAndreas.Sandberg@ARM.com "between CPU models)") 2301634SN/A 2314776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 2324776Sgblack@eecs.umich.edu 2338839Sandreas.hansson@arm.com icache_port = MasterPort("Instruction Port") 2348839Sandreas.hansson@arm.com dcache_port = MasterPort("Data Port") 2358707Sandreas.hansson@arm.com _cached_ports = ['icache_port', 'dcache_port'] 2368707Sandreas.hansson@arm.com 2378756Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2388707Sandreas.hansson@arm.com _cached_ports += ["itb.walker.port", "dtb.walker.port"] 2397876Sgblack@eecs.umich.edu 2408839Sandreas.hansson@arm.com _uncached_slave_ports = [] 2418839Sandreas.hansson@arm.com _uncached_master_ports = [] 2428745Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 24311150Smitch.hayenga@arm.com _uncached_slave_ports += ["interrupts[0].pio", 24411150Smitch.hayenga@arm.com "interrupts[0].int_slave"] 24511150Smitch.hayenga@arm.com _uncached_master_ports += ["interrupts[0].int_master"] 2462998SN/A 2478863Snilay@cs.wisc.edu def createInterruptController(self): 2488863Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == 'sparc': 24911150Smitch.hayenga@arm.com self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)] 2508863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'alpha': 25111150Smitch.hayenga@arm.com self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)] 2528863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'x86': 2539793Sakash.bagdia@arm.com self.apic_clk_domain = DerivedClockDomain(clk_domain = 2549793Sakash.bagdia@arm.com Parent.clk_domain, 2559793Sakash.bagdia@arm.com clk_divider = 16) 25611150Smitch.hayenga@arm.com self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain, 2579544Sandreas.hansson@arm.com pio_addr=0x2000000000000000) 25811150Smitch.hayenga@arm.com for i in xrange(self.numThreads)] 2599544Sandreas.hansson@arm.com _localApic = self.interrupts 2608863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'mips': 26111150Smitch.hayenga@arm.com self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)] 2628863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'arm': 26311150Smitch.hayenga@arm.com self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)] 2648863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'power': 26511150Smitch.hayenga@arm.com self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)] 26611723Sar4jc@virginia.edu elif buildEnv['TARGET_ISA'] == 'riscv': 26711723Sar4jc@virginia.edu self.interrupts = \ 26811723Sar4jc@virginia.edu [RiscvInterrupts() for i in xrange(self.numThreads)] 2698863Snilay@cs.wisc.edu else: 2708863Snilay@cs.wisc.edu print "Don't know what Interrupt Controller to use for ISA %s" % \ 2718863Snilay@cs.wisc.edu buildEnv['TARGET_ISA'] 2728863Snilay@cs.wisc.edu sys.exit(1) 2738863Snilay@cs.wisc.edu 2747876Sgblack@eecs.umich.edu def connectCachedPorts(self, bus): 2757876Sgblack@eecs.umich.edu for p in self._cached_ports: 2768839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2777404SAli.Saidi@ARM.com 2787876Sgblack@eecs.umich.edu def connectUncachedPorts(self, bus): 2798839Sandreas.hansson@arm.com for p in self._uncached_slave_ports: 2808839Sandreas.hansson@arm.com exec('self.%s = bus.master' % p) 2818839Sandreas.hansson@arm.com for p in self._uncached_master_ports: 2828839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2837876Sgblack@eecs.umich.edu 2847876Sgblack@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 2857876Sgblack@eecs.umich.edu self.connectCachedPorts(cached_bus) 2867876Sgblack@eecs.umich.edu if not uncached_bus: 2877876Sgblack@eecs.umich.edu uncached_bus = cached_bus 2887876Sgblack@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 2892998SN/A 2907868Sgblack@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 2912998SN/A self.icache = ic 2922998SN/A self.dcache = dc 2932998SN/A self.icache_port = ic.cpu_side 2942998SN/A self.dcache_port = dc.cpu_side 2957876Sgblack@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 2968796Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2978796Sgblack@eecs.umich.edu if iwc and dwc: 2988796Sgblack@eecs.umich.edu self.itb_walker_cache = iwc 2998796Sgblack@eecs.umich.edu self.dtb_walker_cache = dwc 30010717Sandreas.hansson@arm.com self.itb.walker.port = iwc.cpu_side 30110717Sandreas.hansson@arm.com self.dtb.walker.port = dwc.cpu_side 3028796Sgblack@eecs.umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 3038796Sgblack@eecs.umich.edu "dtb_walker_cache.mem_side"] 3048796Sgblack@eecs.umich.edu else: 3058796Sgblack@eecs.umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 3068887Sgeoffrey.blake@arm.com 3078809Sgblack@eecs.umich.edu # Checker doesn't need its own tlb caches because it does 3088809Sgblack@eecs.umich.edu # functional accesses only 3098887Sgeoffrey.blake@arm.com if self.checker != NULL: 3108809Sgblack@eecs.umich.edu self._cached_ports += ["checker.itb.walker.port", \ 3118809Sgblack@eecs.umich.edu "checker.dtb.walker.port"] 3122998SN/A 3137868Sgblack@eecs.umich.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 3147868Sgblack@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 31510720Sandreas.hansson@arm.com self.toL2Bus = L2XBar() 3167876Sgblack@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 3172998SN/A self.l2cache = l2c 3188839Sandreas.hansson@arm.com self.toL2Bus.master = self.l2cache.cpu_side 3197876Sgblack@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 3208887Sgeoffrey.blake@arm.com 3219384SAndreas.Sandberg@arm.com def createThreads(self): 32212325Sandreas.sandberg@arm.com # If no ISAs have been created, assume that the user wants the 32312325Sandreas.sandberg@arm.com # default ISA. 32412325Sandreas.sandberg@arm.com if len(self.isa) == 0: 32512325Sandreas.sandberg@arm.com self.isa = [ default_isa_class() for i in xrange(self.numThreads) ] 32612325Sandreas.sandberg@arm.com else: 32712325Sandreas.sandberg@arm.com if len(self.isa) != int(self.numThreads): 32812325Sandreas.sandberg@arm.com raise RuntimeError("Number of ISA instances doesn't " 32912325Sandreas.sandberg@arm.com "match thread count") 3309384SAndreas.Sandberg@arm.com if self.checker != NULL: 3319384SAndreas.Sandberg@arm.com self.checker.createThreads() 3329384SAndreas.Sandberg@arm.com 3338887Sgeoffrey.blake@arm.com def addCheckerCpu(self): 3348887Sgeoffrey.blake@arm.com pass 335