types.hh revision 9031
11196Shsul@eecs.umich.edu/*
21196Shsul@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan
31196Shsul@eecs.umich.edu * All rights reserved.
41196Shsul@eecs.umich.edu *
51196Shsul@eecs.umich.edu * Redistribution and use in source and binary forms, with or without
61196Shsul@eecs.umich.edu * modification, are permitted provided that the following conditions are
71196Shsul@eecs.umich.edu * met: redistributions of source code must retain the above copyright
81196Shsul@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
91196Shsul@eecs.umich.edu * redistributions in binary form must reproduce the above copyright
101196Shsul@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the
111196Shsul@eecs.umich.edu * documentation and/or other materials provided with the distribution;
121196Shsul@eecs.umich.edu * neither the name of the copyright holders nor the names of its
131196Shsul@eecs.umich.edu * contributors may be used to endorse or promote products derived from
141196Shsul@eecs.umich.edu * this software without specific prior written permission.
151196Shsul@eecs.umich.edu *
161196Shsul@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171196Shsul@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181196Shsul@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191196Shsul@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201196Shsul@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211196Shsul@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221196Shsul@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231196Shsul@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241196Shsul@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251196Shsul@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261196Shsul@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
271196Shsul@eecs.umich.edu *
281196Shsul@eecs.umich.edu * Authors: Nathan Binkert
291196Shsul@eecs.umich.edu */
301196Shsul@eecs.umich.edu
311196Shsul@eecs.umich.edu/**
321196Shsul@eecs.umich.edu * @file
331196Shsul@eecs.umich.edu * Defines global host-dependent types:
341196Shsul@eecs.umich.edu * Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
351196Shsul@eecs.umich.edu */
361196Shsul@eecs.umich.edu
371196Shsul@eecs.umich.edu#ifndef __BASE_TYPES_HH__
381196Shsul@eecs.umich.edu#define __BASE_TYPES_HH__
391196Shsul@eecs.umich.edu
401196Shsul@eecs.umich.edu#include <inttypes.h>
411196Shsul@eecs.umich.edu
421196Shsul@eecs.umich.edu/** uint64_t constant */
431196Shsul@eecs.umich.edu#define ULL(N)          ((uint64_t)N##ULL)
441196Shsul@eecs.umich.edu/** int64_t constant */
451196Shsul@eecs.umich.edu#define LL(N)           ((int64_t)N##LL)
461196Shsul@eecs.umich.edu
471196Shsul@eecs.umich.edu/** Statistics counter type.  Not much excuse for not using a 64-bit
481196Shsul@eecs.umich.edu * integer here, but if you're desperate and only run short
491196Shsul@eecs.umich.edu * simulations you could make this 32 bits.
501196Shsul@eecs.umich.edu */
511196Shsul@eecs.umich.edutypedef int64_t Counter;
52
53/**
54 * Clock cycle count type.
55 * @note using an unsigned breaks the cache.
56 */
57typedef int64_t Tick;
58typedef uint64_t UTick;
59
60const Tick MaxTick = LL(0x7fffffffffffffff);
61
62/**
63 * Address type
64 * This will probably be moved somewhere else in the near future.
65 * This should be at least as big as the biggest address width in use
66 * in the system, which will probably be 64 bits.
67 */
68typedef uint64_t Addr;
69
70typedef uint16_t MicroPC;
71
72static const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1);
73
74static inline MicroPC
75romMicroPC(MicroPC upc)
76{
77    return upc | MicroPCRomBit;
78}
79
80static inline MicroPC
81normalMicroPC(MicroPC upc)
82{
83    return upc & ~MicroPCRomBit;
84}
85
86static inline bool
87isRomMicroPC(MicroPC upc)
88{
89    return MicroPCRomBit & upc;
90}
91
92const Addr MaxAddr = (Addr)-1;
93
94/**
95 * Thread index/ID type
96 */
97typedef int16_t ThreadID;
98const ThreadID InvalidThreadID = (ThreadID)-1;
99
100/**
101 * Port index/ID type, and a symbolic name for an invalid port id.
102 */
103typedef int16_t PortID;
104const PortID InvalidPortID = (PortID)-1;
105
106class FaultBase;
107template <class T> class RefCountingPtr;
108typedef RefCountingPtr<FaultBase> Fault;
109
110#endif // __BASE_TYPES_HH__
111