types.hh revision 9500
12SN/A/*
21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Nathan Binkert
292SN/A */
302SN/A
312SN/A/**
322SN/A * @file
336214Snate@binkert.org * Defines global host-dependent types:
342SN/A * Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
352SN/A */
362SN/A
376214Snate@binkert.org#ifndef __BASE_TYPES_HH__
386214Snate@binkert.org#define __BASE_TYPES_HH__
392SN/A
402SN/A#include <inttypes.h>
412SN/A
429180Sandreas.hansson@arm.com#include <cassert>
439500Snilay@cs.wisc.edu#include <ostream>
449180Sandreas.hansson@arm.com
452SN/A/** uint64_t constant */
465543SN/A#define ULL(N)          ((uint64_t)N##ULL)
472SN/A/** int64_t constant */
485543SN/A#define LL(N)           ((int64_t)N##LL)
492SN/A
502SN/A/** Statistics counter type.  Not much excuse for not using a 64-bit
512SN/A * integer here, but if you're desperate and only run short
522SN/A * simulations you could make this 32 bits.
532SN/A */
542SN/Atypedef int64_t Counter;
552SN/A
562SN/A/**
579158Sandreas.hansson@arm.com * Tick count type.
582SN/A */
599158Sandreas.hansson@arm.comtypedef uint64_t Tick;
602SN/A
619158Sandreas.hansson@arm.comconst Tick MaxTick = ULL(0xffffffffffffffff);
622667SN/A
632130SN/A/**
649180Sandreas.hansson@arm.com * Cycles is a wrapper class for representing cycle counts, i.e. a
659180Sandreas.hansson@arm.com * relative difference between two points in time, expressed in a
669180Sandreas.hansson@arm.com * number of clock cycles.
679180Sandreas.hansson@arm.com *
689180Sandreas.hansson@arm.com * The Cycles wrapper class is a type-safe alternative to a
699180Sandreas.hansson@arm.com * typedef, aiming to avoid unintentional mixing of cycles and ticks
709180Sandreas.hansson@arm.com * in the code base.
719180Sandreas.hansson@arm.com *
729180Sandreas.hansson@arm.com * Operators are defined inside an ifndef block to avoid swig touching
739180Sandreas.hansson@arm.com * them. Note that there is no overloading of the bool operator as the
749180Sandreas.hansson@arm.com * compiler is allowed to turn booleans into integers and this causes
759180Sandreas.hansson@arm.com * a whole range of issues in a handful locations. The solution to
769180Sandreas.hansson@arm.com * this problem would be to use the safe bool idiom, but for now we
779180Sandreas.hansson@arm.com * make do without the test and use the more elaborate comparison >
789180Sandreas.hansson@arm.com * Cycles(0).
799180Sandreas.hansson@arm.com */
809180Sandreas.hansson@arm.comclass Cycles
819180Sandreas.hansson@arm.com{
829180Sandreas.hansson@arm.com
839180Sandreas.hansson@arm.com  private:
849180Sandreas.hansson@arm.com
859180Sandreas.hansson@arm.com    /** Member holding the actual value. */
869180Sandreas.hansson@arm.com    uint64_t c;
879180Sandreas.hansson@arm.com
889180Sandreas.hansson@arm.com  public:
899180Sandreas.hansson@arm.com
909180Sandreas.hansson@arm.com    /** Explicit constructor assigning a value. */
919180Sandreas.hansson@arm.com    explicit Cycles(uint64_t _c) : c(_c) { }
929180Sandreas.hansson@arm.com
939184Sandreas.hansson@arm.com    /** Default constructor for parameter classes. */
949184Sandreas.hansson@arm.com    Cycles() : c(0) { }
959184Sandreas.hansson@arm.com
969180Sandreas.hansson@arm.com#ifndef SWIG // keep the operators away from SWIG
979180Sandreas.hansson@arm.com
989180Sandreas.hansson@arm.com    /** Converting back to the value type. */
999180Sandreas.hansson@arm.com    operator uint64_t() const { return c; }
1009180Sandreas.hansson@arm.com
1019180Sandreas.hansson@arm.com    /** Prefix increment operator. */
1029180Sandreas.hansson@arm.com    Cycles& operator++()
1039180Sandreas.hansson@arm.com    { ++c; return *this; }
1049180Sandreas.hansson@arm.com
1059180Sandreas.hansson@arm.com    /** Prefix decrement operator. Is only temporarily used in the O3 CPU. */
1069180Sandreas.hansson@arm.com    Cycles& operator--()
1079180Sandreas.hansson@arm.com    { assert(c != 0); --c; return *this; }
1089180Sandreas.hansson@arm.com
1099180Sandreas.hansson@arm.com    /** In-place addition of cycles. */
1109180Sandreas.hansson@arm.com    const Cycles& operator+=(const Cycles& cc)
1119180Sandreas.hansson@arm.com    { c += cc.c; return *this; }
1129180Sandreas.hansson@arm.com
1139180Sandreas.hansson@arm.com    /** Greater than comparison used for > Cycles(0). */
1149180Sandreas.hansson@arm.com    bool operator>(const Cycles& cc) const
1159180Sandreas.hansson@arm.com    { return c > cc.c; }
1169180Sandreas.hansson@arm.com
1179498Snilay@cs.wisc.edu    const Cycles operator +(const Cycles& b) const
1189498Snilay@cs.wisc.edu    { return Cycles(c + b.c); }
1199498Snilay@cs.wisc.edu
1209498Snilay@cs.wisc.edu    const Cycles operator -(const Cycles& b) const
1219498Snilay@cs.wisc.edu    { assert(c >= b.c); return Cycles(c - b.c); }
1229498Snilay@cs.wisc.edu
1239498Snilay@cs.wisc.edu    const Cycles operator <<(const int32_t shift)
1249498Snilay@cs.wisc.edu    { return Cycles(c << shift); }
1259498Snilay@cs.wisc.edu
1269498Snilay@cs.wisc.edu    const Cycles operator >>(const int32_t shift)
1279498Snilay@cs.wisc.edu    { return Cycles(c >> shift); }
1289498Snilay@cs.wisc.edu
1299500Snilay@cs.wisc.edu    friend std::ostream& operator<<(std::ostream &out, const Cycles & cycles);
1309500Snilay@cs.wisc.edu
1319180Sandreas.hansson@arm.com#endif // SWIG not touching operators
1329180Sandreas.hansson@arm.com
1339180Sandreas.hansson@arm.com};
1349180Sandreas.hansson@arm.com
1359180Sandreas.hansson@arm.com/**
1362130SN/A * Address type
1372130SN/A * This will probably be moved somewhere else in the near future.
1382130SN/A * This should be at least as big as the biggest address width in use
1392130SN/A * in the system, which will probably be 64 bits.
1402130SN/A */
1412130SN/Atypedef uint64_t Addr;
1422130SN/A
1437720Sgblack@eecs.umich.edutypedef uint16_t MicroPC;
1447720Sgblack@eecs.umich.edu
1457720Sgblack@eecs.umich.edustatic const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1);
1467720Sgblack@eecs.umich.edu
1477720Sgblack@eecs.umich.edustatic inline MicroPC
1487720Sgblack@eecs.umich.eduromMicroPC(MicroPC upc)
1497720Sgblack@eecs.umich.edu{
1507720Sgblack@eecs.umich.edu    return upc | MicroPCRomBit;
1517720Sgblack@eecs.umich.edu}
1527720Sgblack@eecs.umich.edu
1537720Sgblack@eecs.umich.edustatic inline MicroPC
1547720Sgblack@eecs.umich.edunormalMicroPC(MicroPC upc)
1557720Sgblack@eecs.umich.edu{
1567720Sgblack@eecs.umich.edu    return upc & ~MicroPCRomBit;
1577720Sgblack@eecs.umich.edu}
1587720Sgblack@eecs.umich.edu
1597720Sgblack@eecs.umich.edustatic inline bool
1607720Sgblack@eecs.umich.eduisRomMicroPC(MicroPC upc)
1617720Sgblack@eecs.umich.edu{
1627720Sgblack@eecs.umich.edu    return MicroPCRomBit & upc;
1637720Sgblack@eecs.umich.edu}
1647720Sgblack@eecs.umich.edu
1652438SN/Aconst Addr MaxAddr = (Addr)-1;
1662438SN/A
1676221Snate@binkert.org/**
1686221Snate@binkert.org * Thread index/ID type
1696221Snate@binkert.org */
1706221Snate@binkert.orgtypedef int16_t ThreadID;
1716221Snate@binkert.orgconst ThreadID InvalidThreadID = (ThreadID)-1;
1726221Snate@binkert.org
1739031Sandreas.hansson@arm.com/**
1749031Sandreas.hansson@arm.com * Port index/ID type, and a symbolic name for an invalid port id.
1759031Sandreas.hansson@arm.com */
1769031Sandreas.hansson@arm.comtypedef int16_t PortID;
1779031Sandreas.hansson@arm.comconst PortID InvalidPortID = (PortID)-1;
1789031Sandreas.hansson@arm.com
1797678Sgblack@eecs.umich.educlass FaultBase;
1807678Sgblack@eecs.umich.edutemplate <class T> class RefCountingPtr;
1817678Sgblack@eecs.umich.edutypedef RefCountingPtr<FaultBase> Fault;
1827678Sgblack@eecs.umich.edu
1836214Snate@binkert.org#endif // __BASE_TYPES_HH__
184