types.hh revision 9158
12SN/A/*
21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Nathan Binkert
292SN/A */
302SN/A
312SN/A/**
322SN/A * @file
336214Snate@binkert.org * Defines global host-dependent types:
342SN/A * Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
352SN/A */
362SN/A
376214Snate@binkert.org#ifndef __BASE_TYPES_HH__
386214Snate@binkert.org#define __BASE_TYPES_HH__
392SN/A
402SN/A#include <inttypes.h>
412SN/A
422SN/A/** uint64_t constant */
435543SN/A#define ULL(N)          ((uint64_t)N##ULL)
442SN/A/** int64_t constant */
455543SN/A#define LL(N)           ((int64_t)N##LL)
462SN/A
472SN/A/** Statistics counter type.  Not much excuse for not using a 64-bit
482SN/A * integer here, but if you're desperate and only run short
492SN/A * simulations you could make this 32 bits.
502SN/A */
512SN/Atypedef int64_t Counter;
522SN/A
532SN/A/**
549158Sandreas.hansson@arm.com * Tick count type.
552SN/A */
569158Sandreas.hansson@arm.comtypedef uint64_t Tick;
572SN/A
589158Sandreas.hansson@arm.comconst Tick MaxTick = ULL(0xffffffffffffffff);
592667SN/A
602130SN/A/**
612130SN/A * Address type
622130SN/A * This will probably be moved somewhere else in the near future.
632130SN/A * This should be at least as big as the biggest address width in use
642130SN/A * in the system, which will probably be 64 bits.
652130SN/A */
662130SN/Atypedef uint64_t Addr;
672130SN/A
687720Sgblack@eecs.umich.edutypedef uint16_t MicroPC;
697720Sgblack@eecs.umich.edu
707720Sgblack@eecs.umich.edustatic const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1);
717720Sgblack@eecs.umich.edu
727720Sgblack@eecs.umich.edustatic inline MicroPC
737720Sgblack@eecs.umich.eduromMicroPC(MicroPC upc)
747720Sgblack@eecs.umich.edu{
757720Sgblack@eecs.umich.edu    return upc | MicroPCRomBit;
767720Sgblack@eecs.umich.edu}
777720Sgblack@eecs.umich.edu
787720Sgblack@eecs.umich.edustatic inline MicroPC
797720Sgblack@eecs.umich.edunormalMicroPC(MicroPC upc)
807720Sgblack@eecs.umich.edu{
817720Sgblack@eecs.umich.edu    return upc & ~MicroPCRomBit;
827720Sgblack@eecs.umich.edu}
837720Sgblack@eecs.umich.edu
847720Sgblack@eecs.umich.edustatic inline bool
857720Sgblack@eecs.umich.eduisRomMicroPC(MicroPC upc)
867720Sgblack@eecs.umich.edu{
877720Sgblack@eecs.umich.edu    return MicroPCRomBit & upc;
887720Sgblack@eecs.umich.edu}
897720Sgblack@eecs.umich.edu
902438SN/Aconst Addr MaxAddr = (Addr)-1;
912438SN/A
926221Snate@binkert.org/**
936221Snate@binkert.org * Thread index/ID type
946221Snate@binkert.org */
956221Snate@binkert.orgtypedef int16_t ThreadID;
966221Snate@binkert.orgconst ThreadID InvalidThreadID = (ThreadID)-1;
976221Snate@binkert.org
989031Sandreas.hansson@arm.com/**
999031Sandreas.hansson@arm.com * Port index/ID type, and a symbolic name for an invalid port id.
1009031Sandreas.hansson@arm.com */
1019031Sandreas.hansson@arm.comtypedef int16_t PortID;
1029031Sandreas.hansson@arm.comconst PortID InvalidPortID = (PortID)-1;
1039031Sandreas.hansson@arm.com
1047678Sgblack@eecs.umich.educlass FaultBase;
1057678Sgblack@eecs.umich.edutemplate <class T> class RefCountingPtr;
1067678Sgblack@eecs.umich.edutypedef RefCountingPtr<FaultBase> Fault;
1077678Sgblack@eecs.umich.edu
1086214Snate@binkert.org#endif // __BASE_TYPES_HH__
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