x86_traits.hh revision 9040:cdfe09f9bdee
1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#ifndef __ARCH_X86_X86TRAITS_HH__ 39#define __ARCH_X86_X86TRAITS_HH__ 40 41#include <cassert> 42 43#include "arch/x86/types.hh" 44#include "base/types.hh" 45 46namespace X86ISA 47{ 48 const int NumMicroIntRegs = 16; 49 50 const int NumPseudoIntRegs = 4; 51 //1. The condition code bits of the rflags register. 52 const int NumImplicitIntRegs = 6; 53 //1. The lower part of the result of multiplication. 54 //2. The upper part of the result of multiplication. 55 //3. The quotient from division 56 //4. The remainder from division 57 //5. The divisor for division 58 //6. The register to use for shift doubles 59 60 const int NumMMXRegs = 8; 61 const int NumXMMRegs = 16; 62 const int NumMicroFpRegs = 8; 63 64 const int NumCRegs = 16; 65 const int NumDRegs = 8; 66 67 const int NumSegments = 6; 68 const int NumSysSegments = 4; 69 70 const Addr IntAddrPrefixMask = ULL(0xffffffff00000000); 71 const Addr IntAddrPrefixCPUID = ULL(0x100000000); 72 const Addr IntAddrPrefixMSR = ULL(0x200000000); 73 const Addr IntAddrPrefixIO = ULL(0x300000000); 74 75 const Addr PhysAddrPrefixIO = ULL(0x8000000000000000); 76 const Addr PhysAddrPrefixPciConfig = ULL(0xC000000000000000); 77 const Addr PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000); 78 const Addr PhysAddrPrefixInterrupts = ULL(0xA000000000000000); 79 // Each APIC gets two pages. One page is used for local apics to field 80 // accesses from the CPU, and the other is for all APICs to communicate. 81 const Addr PhysAddrAPICRangeSize = 1 << 12; 82 83 static inline Addr 84 x86IOAddress(const uint32_t port) 85 { 86 return PhysAddrPrefixIO | port; 87 } 88 89 static inline Addr 90 x86PciConfigAddress(const uint32_t addr) 91 { 92 return PhysAddrPrefixPciConfig | addr; 93 } 94 95 static inline Addr 96 x86LocalAPICAddress(const uint8_t id, const uint16_t addr) 97 { 98 assert(addr < (1 << 12)); 99 return PhysAddrPrefixLocalAPIC | (id * (1 << 12)) | addr; 100 } 101 102 static inline Addr 103 x86InterruptAddress(const uint8_t id, const uint16_t addr) 104 { 105 assert(addr < PhysAddrAPICRangeSize); 106 return PhysAddrPrefixInterrupts | (id * PhysAddrAPICRangeSize) | addr; 107 } 108 109 const ExtMachInst NoopMachInst = { 110 0x0, // No legacy prefixes. 111 0x0, // No rex prefix. 112 { 1, 0x0, 0x0, 0x90 }, // One opcode byte, 0x90. 113 0x0, 0x0, // No modrm or sib. 114 0, 0, // No immediate or displacement. 115 8, 8, 8, // All sizes are 8. 116 0, // Displacement size is 0. 117 SixtyFourBitMode // Behave as if we're in 64 bit 118 // mode (this doesn't actually matter). 119 }; 120} 121 122#endif //__ARCH_X86_X86TRAITS_HH__ 123