utility.hh revision 9889:2dbc34e3b922
12SN/A/* 213107Sgiacomo.travaglini@arm.com * Copyright (c) 2007 The Hewlett-Packard Development Company 310905Sandreas.sandberg@arm.com * All rights reserved. 410905Sandreas.sandberg@arm.com * 510905Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 610905Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 710905Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 810905Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 910905Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1010905Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1110905Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1210905Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1310905Sandreas.sandberg@arm.com * 141762SN/A * Redistribution and use in source and binary forms, with or without 152SN/A * modification, are permitted provided that the following conditions are 162SN/A * met: redistributions of source code must retain the above copyright 172SN/A * notice, this list of conditions and the following disclaimer; 182SN/A * redistributions in binary form must reproduce the above copyright 192SN/A * notice, this list of conditions and the following disclaimer in the 202SN/A * documentation and/or other materials provided with the distribution; 212SN/A * neither the name of the copyright holders nor the names of its 222SN/A * contributors may be used to endorse or promote products derived from 232SN/A * this software without specific prior written permission. 242SN/A * 252SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362SN/A * 372SN/A * Authors: Gabe Black 382SN/A */ 392665Ssaidi@eecs.umich.edu 402760Sbinkertn@umich.edu#ifndef __ARCH_X86_UTILITY_HH__ 412760Sbinkertn@umich.edu#define __ARCH_X86_UTILITY_HH__ 422665Ssaidi@eecs.umich.edu 4310905Sandreas.sandberg@arm.com#include "arch/x86/regs/misc.hh" 442SN/A#include "arch/x86/types.hh" 452SN/A#include "base/hashmap.hh" 462SN/A#include "base/misc.hh" 472SN/A#include "base/types.hh" 482SN/A#include "cpu/static_inst.hh" 492SN/A#include "cpu/thread_context.hh" 502SN/A#include "sim/full_system.hh" 512SN/A 522SN/Aclass ThreadContext; 532SN/A 5413107Sgiacomo.travaglini@arm.comnamespace X86ISA 558229Snate@binkert.org{ 562SN/A 578229Snate@binkert.org inline PCState 5810905Sandreas.sandberg@arm.com buildRetPC(const PCState &curPC, const PCState &callPC) 5911076SCurtis.Dunham@arm.com { 604841Ssaidi@eecs.umich.edu PCState retPC = callPC; 612SN/A retPC.uEnd(); 6210459SAndreas.Sandberg@ARM.com return retPC; 632SN/A } 6411800Sbrandon.potter@amd.com 652738Sstever@eecs.umich.edu uint64_t 66395SN/A getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 674000Ssaidi@eecs.umich.edu 6811067Sandreas.sandberg@arm.com static inline bool 692SN/A inUserMode(ThreadContext *tc) 7010905Sandreas.sandberg@arm.com { 7110905Sandreas.sandberg@arm.com if (!FullSystem) { 7210905Sandreas.sandberg@arm.com return true; 73217SN/A } else { 7410905Sandreas.sandberg@arm.com HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 75217SN/A return m5reg.cpl == 3; 7612452Sgabeblack@google.com } 7712452Sgabeblack@google.com } 7812452Sgabeblack@google.com 7910459SAndreas.Sandberg@ARM.com /** 8012452Sgabeblack@google.com * Function to insure ISA semantics about 0 registers. 8110459SAndreas.Sandberg@ARM.com * @param tc The thread context. 8210459SAndreas.Sandberg@ARM.com */ 83217SN/A template <class TC> 8410905Sandreas.sandberg@arm.com void zeroRegisters(TC *tc); 85217SN/A 8612452Sgabeblack@google.com void initCPU(ThreadContext *tc, int cpuId); 8712452Sgabeblack@google.com 8812452Sgabeblack@google.com void startupCPU(ThreadContext *tc, int cpuId); 8910459SAndreas.Sandberg@ARM.com 9012452Sgabeblack@google.com void copyRegs(ThreadContext *src, ThreadContext *dest); 9112452Sgabeblack@google.com 9212452Sgabeblack@google.com void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 9310459SAndreas.Sandberg@ARM.com 9410459SAndreas.Sandberg@ARM.com void skipFunction(ThreadContext *tc); 95217SN/A 9611075SCurtis.Dunham@arm.com inline void 9711075SCurtis.Dunham@arm.com advancePC(PCState &pc, const StaticInstPtr inst) 986820SLisa.Hsu@amd.com { 9912452Sgabeblack@google.com inst->advancePC(pc); 10012452Sgabeblack@google.com } 10112452Sgabeblack@google.com 10212452Sgabeblack@google.com inline uint64_t 10310459SAndreas.Sandberg@ARM.com getExecutingAsid(ThreadContext *tc) 10412452Sgabeblack@google.com { 10512452Sgabeblack@google.com return 0; 10612452Sgabeblack@google.com } 10712452Sgabeblack@google.com 10812452Sgabeblack@google.com 10912452Sgabeblack@google.com /** 11012452Sgabeblack@google.com * Reconstruct the rflags register from the internal gem5 register 11110459SAndreas.Sandberg@ARM.com * state. 11210459SAndreas.Sandberg@ARM.com * 1136820SLisa.Hsu@amd.com * gem5 stores rflags in several different registers to avoid 11410905Sandreas.sandberg@arm.com * pipeline dependencies. In order to get the true rflags value, 1156227Snate@binkert.org * we can't simply read the value of MISCREG_RFLAGS. Instead, we 116217SN/A * need to read out various state from microcode registers and 117217SN/A * merge that with MISCREG_RFLAGS. 11810905Sandreas.sandberg@arm.com * 1194841Ssaidi@eecs.umich.edu * @param tc Thread context to read rflags from. 1204841Ssaidi@eecs.umich.edu * @return rflags as seen by the guest. 1214841Ssaidi@eecs.umich.edu */ 12210905Sandreas.sandberg@arm.com uint64_t getRFlags(ThreadContext *tc); 1237948SAli.Saidi@ARM.com 1247948SAli.Saidi@ARM.com /** 1257948SAli.Saidi@ARM.com * Set update the rflags register and internal gem5 state. 12611076SCurtis.Dunham@arm.com * 12711076SCurtis.Dunham@arm.com * @note This function does not update MISCREG_M5_REG. You might 12811076SCurtis.Dunham@arm.com * need to update this register by writing anything to 12911076SCurtis.Dunham@arm.com * MISCREG_M5_REG with side-effects. 13010905Sandreas.sandberg@arm.com * 13110905Sandreas.sandberg@arm.com * @see X86ISA::getRFlags() 132217SN/A * 1334841Ssaidi@eecs.umich.edu * @param tc Thread context to update 13410905Sandreas.sandberg@arm.com * @param val New rflags value to store in TC 13510905Sandreas.sandberg@arm.com */ 1364841Ssaidi@eecs.umich.edu void setRFlags(ThreadContext *tc, uint64_t val); 1377948SAli.Saidi@ARM.com 13810905Sandreas.sandberg@arm.com /** 13910905Sandreas.sandberg@arm.com * Extract the bit string representing a double value. 1407948SAli.Saidi@ARM.com */ 14111076SCurtis.Dunham@arm.com inline uint64_t getDoubleBits(double val) { 14211076SCurtis.Dunham@arm.com return *(uint64_t *)(&val); 14311076SCurtis.Dunham@arm.com } 14411076SCurtis.Dunham@arm.com 145237SN/A /** 14610905Sandreas.sandberg@arm.com * Convert an x87 tag word to abridged tag format. 147237SN/A * 14813107Sgiacomo.travaglini@arm.com * Convert from the x87 tag representation to the tag abridged 14913107Sgiacomo.travaglini@arm.com * representation used in the FXSAVE area. The classic format uses 15013107Sgiacomo.travaglini@arm.com * 2 bits per stack position to indicate if a position is valid, 15113107Sgiacomo.travaglini@arm.com * zero, special, or empty. The abridged format only stores 15213107Sgiacomo.travaglini@arm.com * whether a position is empty or not. 15313107Sgiacomo.travaglini@arm.com * 15413107Sgiacomo.travaglini@arm.com * @param ftw Tag word in classic x87 format. 15513107Sgiacomo.travaglini@arm.com * @return Tag word in the abridged format. 15613107Sgiacomo.travaglini@arm.com */ 15713107Sgiacomo.travaglini@arm.com uint8_t convX87TagsToXTags(uint16_t ftw); 15813107Sgiacomo.travaglini@arm.com 15913107Sgiacomo.travaglini@arm.com /** 16013107Sgiacomo.travaglini@arm.com * Convert an x87 xtag word to normal tags format. 16113107Sgiacomo.travaglini@arm.com * 16213107Sgiacomo.travaglini@arm.com * Convert from the abridged x87 tag representation used in the 16313107Sgiacomo.travaglini@arm.com * FXSAVE area to a full x87 tag. The classic format uses 2 bits 16413107Sgiacomo.travaglini@arm.com * per stack position to indicate if a position is valid, zero, 16513107Sgiacomo.travaglini@arm.com * special, or empty. The abridged format only stores whether a 16613107Sgiacomo.travaglini@arm.com * position is empty or not. 16713107Sgiacomo.travaglini@arm.com * 16813107Sgiacomo.travaglini@arm.com * @todo Reconstruct the correct state of stack positions instead 16913107Sgiacomo.travaglini@arm.com * of just valid/invalid. 17013107Sgiacomo.travaglini@arm.com * 17113107Sgiacomo.travaglini@arm.com * @param ftwx Tag word in the abridged format. 17213107Sgiacomo.travaglini@arm.com * @return Tag word in classic x87 format. 173217SN/A */ 174217SN/A uint16_t convX87XTagsToTags(uint8_t ftwx); 175217SN/A 176237SN/A /** 17710905Sandreas.sandberg@arm.com * Generate and updated x87 tag register after a push/pop 178217SN/A * operation. 17910905Sandreas.sandberg@arm.com * 18010905Sandreas.sandberg@arm.com * @note There is currently no support for setting other tags than 181217SN/A * valid and invalid. A real x87 will set the tag value to zero or 182223SN/A * special for some special floating point values. 18310905Sandreas.sandberg@arm.com * 184223SN/A * @param ftw Current value of the FTW register. 18511068Sandreas.sandberg@arm.com * @param top Current x87 TOP value. 18611068Sandreas.sandberg@arm.com * @param spm Stack displacement. 18711068Sandreas.sandberg@arm.com * @return New value of the FTW register. 18811068Sandreas.sandberg@arm.com */ 18911068Sandreas.sandberg@arm.com uint16_t genX87Tags(uint16_t ftw, uint8_t top, int8_t spm); 19011068Sandreas.sandberg@arm.com 191223SN/A /** 1925543Ssaidi@eecs.umich.edu * Load an 80-bit float from memory and convert it to double. 19310905Sandreas.sandberg@arm.com * 194217SN/A * @param mem Pointer to an 80-bit float. 1955543Ssaidi@eecs.umich.edu * @return double representation of the 80-bit float. 19610905Sandreas.sandberg@arm.com */ 197237SN/A double loadFloat80(const void *mem); 19810903Sandreas.sandberg@arm.com 19910905Sandreas.sandberg@arm.com /** 20010903Sandreas.sandberg@arm.com * Convert and store a double as an 80-bit float. 20110903Sandreas.sandberg@arm.com * 20210905Sandreas.sandberg@arm.com * @param mem Pointer to destination for the 80-bit float. 20310903Sandreas.sandberg@arm.com * @param value Double precision float to store. 20410906Sandreas.sandberg@arm.com */ 20510906Sandreas.sandberg@arm.com void storeFloat80(void *mem, double value); 20610906Sandreas.sandberg@arm.com} 20710906Sandreas.sandberg@arm.com 20810906Sandreas.sandberg@arm.com#endif // __ARCH_X86_UTILITY_HH__ 20910906Sandreas.sandberg@arm.com