utility.hh revision 6313:95f69a436c82 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
21 *     Office of Strategy and Technology
22 *     Hewlett-Packard Company
23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
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31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_UTILITY_HH__
59#define __ARCH_X86_UTILITY_HH__
60
61#include "arch/x86/miscregs.hh"
62#include "arch/x86/types.hh"
63#include "base/hashmap.hh"
64#include "base/misc.hh"
65#include "base/types.hh"
66#include "config/full_system.hh"
67#include "cpu/thread_context.hh"
68
69class ThreadContext;
70
71namespace __hash_namespace {
72    template<>
73    struct hash<X86ISA::ExtMachInst> {
74        size_t operator()(const X86ISA::ExtMachInst &emi) const {
75            return (((uint64_t)emi.legacy << 56) |
76                    ((uint64_t)emi.rex  << 48) |
77                    ((uint64_t)emi.modRM << 40) |
78                    ((uint64_t)emi.sib << 32) |
79                    ((uint64_t)emi.opcode.num << 24) |
80                    ((uint64_t)emi.opcode.prefixA << 16) |
81                    ((uint64_t)emi.opcode.prefixB << 8) |
82                    ((uint64_t)emi.opcode.op)) ^
83                    emi.immediate ^ emi.displacement ^
84                    emi.mode ^
85                    emi.opSize ^ emi.addrSize ^ emi.stackSize;
86        };
87    };
88}
89
90namespace X86ISA
91{
92    uint64_t getArgument(ThreadContext *tc, int number, bool fp);
93
94    static inline bool
95    inUserMode(ThreadContext *tc)
96    {
97#if FULL_SYSTEM
98        HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
99        return m5reg.cpl == 3;
100#else
101        return true;
102#endif
103    }
104
105    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
106        panic("register classification not implemented");
107        return false;
108    }
109
110    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
111        panic("register classification not implemented");
112        return false;
113    }
114
115    inline bool isCallerSaveFloatRegister(unsigned int reg) {
116        panic("register classification not implemented");
117        return false;
118    }
119
120    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
121        panic("register classification not implemented");
122        return false;
123    }
124
125    // Instruction address compression hooks
126    inline Addr realPCToFetchPC(const Addr &addr)
127    {
128        return addr;
129    }
130
131    inline Addr fetchPCToRealPC(const Addr &addr)
132    {
133        return addr;
134    }
135
136    // the size of "fetched" instructions (not necessarily the size
137    // of real instructions for PISA)
138    inline size_t fetchInstSize()
139    {
140        return sizeof(MachInst);
141    }
142
143    /**
144     * Function to insure ISA semantics about 0 registers.
145     * @param tc The thread context.
146     */
147    template <class TC>
148    void zeroRegisters(TC *tc);
149
150#if FULL_SYSTEM
151
152    void initCPU(ThreadContext *tc, int cpuId);
153
154#endif
155
156    void startupCPU(ThreadContext *tc, int cpuId);
157};
158
159#endif // __ARCH_X86_UTILITY_HH__
160