utility.hh revision 8300
12SN/A/* 21762SN/A * Copyright (c) 2007 The Hewlett-Packard Development Company 35502Snate@binkert.org * All rights reserved. 49983Sstever@gmail.com * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Redistribution and use in source and binary forms, with or without 152SN/A * modification, are permitted provided that the following conditions are 162SN/A * met: redistributions of source code must retain the above copyright 172SN/A * notice, this list of conditions and the following disclaimer; 182SN/A * redistributions in binary form must reproduce the above copyright 192SN/A * notice, this list of conditions and the following disclaimer in the 202SN/A * documentation and/or other materials provided with the distribution; 212SN/A * neither the name of the copyright holders nor the names of its 222SN/A * contributors may be used to endorse or promote products derived from 232SN/A * this software without specific prior written permission. 242SN/A * 252SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292665Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302665Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312665Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322665Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 355501Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362SN/A * 372SN/A * Authors: Gabe Black 382SN/A */ 392SN/A 405502Snate@binkert.org#ifndef __ARCH_X86_UTILITY_HH__ 415501Snate@binkert.org#define __ARCH_X86_UTILITY_HH__ 425501Snate@binkert.org 431717SN/A#include "arch/x86/regs/misc.hh" 448232Snate@binkert.org#include "arch/x86/types.hh" 455501Snate@binkert.org#include "base/hashmap.hh" 469356Snilay@cs.wisc.edu#include "base/misc.hh" 472SN/A#include "base/types.hh" 482SN/A#include "config/full_system.hh" 492SN/A#include "cpu/static_inst.hh" 509983Sstever@gmail.com#include "cpu/thread_context.hh" 519983Sstever@gmail.com 522SN/Aclass ThreadContext; 539983Sstever@gmail.com 542SN/Anamespace X86ISA 559983Sstever@gmail.com{ 562SN/A 572SN/A inline PCState 589983Sstever@gmail.com buildRetPC(const PCState &curPC, const PCState &callPC) 599983Sstever@gmail.com { 609983Sstever@gmail.com PCState retPC = callPC; 619983Sstever@gmail.com retPC.uEnd(); 629983Sstever@gmail.com return retPC; 639983Sstever@gmail.com } 649983Sstever@gmail.com 659983Sstever@gmail.com uint64_t 669983Sstever@gmail.com getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 679983Sstever@gmail.com 689983Sstever@gmail.com static inline bool 699983Sstever@gmail.com inUserMode(ThreadContext *tc) 709983Sstever@gmail.com { 719983Sstever@gmail.com#if FULL_SYSTEM 729983Sstever@gmail.com HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 739983Sstever@gmail.com return m5reg.cpl == 3; 742SN/A#else 754017Sstever@eecs.umich.edu return true; 764016Sstever@eecs.umich.edu#endif 774017Sstever@eecs.umich.edu } 784016Sstever@eecs.umich.edu 795768Snate@binkert.org /** 805768Snate@binkert.org * Function to insure ISA semantics about 0 registers. 815774Snate@binkert.org * @param tc The thread context. 827059Snate@binkert.org */ 835768Snate@binkert.org template <class TC> 845768Snate@binkert.org void zeroRegisters(TC *tc); 855768Snate@binkert.org 865768Snate@binkert.org#if FULL_SYSTEM 875768Snate@binkert.org 885768Snate@binkert.org void initCPU(ThreadContext *tc, int cpuId); 895768Snate@binkert.org 905768Snate@binkert.org#endif 915768Snate@binkert.org 925768Snate@binkert.org void startupCPU(ThreadContext *tc, int cpuId); 935768Snate@binkert.org 945768Snate@binkert.org void copyRegs(ThreadContext *src, ThreadContext *dest); 955768Snate@binkert.org 965602Snate@binkert.org void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 975602Snate@binkert.org 985502Snate@binkert.org void skipFunction(ThreadContext *tc); 995503Snate@binkert.org 1005502Snate@binkert.org inline void 1015502Snate@binkert.org advancePC(PCState &pc, const StaticInstPtr inst) 1025502Snate@binkert.org { 1035502Snate@binkert.org inst->advancePC(pc); 1045502Snate@binkert.org } 1055503Snate@binkert.org 1065502Snate@binkert.org inline uint64_t 1075502Snate@binkert.org getExecutingAsid(ThreadContext *tc) 1085502Snate@binkert.org { 1095502Snate@binkert.org return 0; 1105503Snate@binkert.org } 1115503Snate@binkert.org 1125503Snate@binkert.org}; 1135502Snate@binkert.org 1145503Snate@binkert.org#endif // __ARCH_X86_UTILITY_HH__ 1155502Snate@binkert.org