utility.hh revision 5135
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IN NO EVENT SHALL THE COPYRIGHT 476285Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 486285Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 497039Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 507039Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 516285Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 527544SBrad.Beckmann@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 537544SBrad.Beckmann@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 547544SBrad.Beckmann@amd.com * 557544SBrad.Beckmann@amd.com * Authors: Gabe Black 567039Snate@binkert.org */ 577039Snate@binkert.org 587039Snate@binkert.org#ifndef __ARCH_X86_UTILITY_HH__ 597039Snate@binkert.org#define __ARCH_X86_UTILITY_HH__ 607039Snate@binkert.org 617039Snate@binkert.org#include "arch/x86/types.hh" 627039Snate@binkert.org#include "base/hashmap.hh" 637039Snate@binkert.org#include "base/misc.hh" 647039Snate@binkert.org#include "config/full_system.hh" 657039Snate@binkert.org#include "cpu/thread_context.hh" 667039Snate@binkert.org#include "sim/host.hh" 677039Snate@binkert.org 687039Snate@binkert.orgclass ThreadContext; 697907Shestness@cs.utexas.edu 707907Shestness@cs.utexas.edunamespace __hash_namespace { 717039Snate@binkert.org template<> 727039Snate@binkert.org struct hash<X86ISA::ExtMachInst> { 737908Shestness@cs.utexas.edu size_t operator()(const X86ISA::ExtMachInst &emi) const { 747908Shestness@cs.utexas.edu return (((uint64_t)emi.legacy << 56) | 757039Snate@binkert.org ((uint64_t)emi.rex << 48) | 767039Snate@binkert.org ((uint64_t)emi.modRM << 40) | 777039Snate@binkert.org ((uint64_t)emi.sib << 32) | 787039Snate@binkert.org ((uint64_t)emi.opcode.num << 24) | 796285Snate@binkert.org ((uint64_t)emi.opcode.prefixA << 16) | 807039Snate@binkert.org ((uint64_t)emi.opcode.prefixB << 8) | 817039Snate@binkert.org ((uint64_t)emi.opcode.op)) ^ 826285Snate@binkert.org emi.immediate ^ emi.displacement ^ 837039Snate@binkert.org emi.mode ^ 847039Snate@binkert.org emi.opSize ^ emi.addrSize ^ emi.stackSize; 857039Snate@binkert.org }; 867039Snate@binkert.org }; 877039Snate@binkert.org} 887039Snate@binkert.org 897039Snate@binkert.orgnamespace X86ISA 906285Snate@binkert.org{ 917453Snate@binkert.org uint64_t getArgument(ThreadContext *tc, int number, bool fp); 927453Snate@binkert.org 937453Snate@binkert.org static inline bool 947453Snate@binkert.org inUserMode(ThreadContext *tc) 957039Snate@binkert.org { 966888SBrad.Beckmann@amd.com return false; 977453Snate@binkert.org } 987039Snate@binkert.org 996888SBrad.Beckmann@amd.com inline bool isCallerSaveIntegerRegister(unsigned int reg) { 1007915SBrad.Beckmann@amd.com panic("register classification not implemented"); 1017915SBrad.Beckmann@amd.com return false; 1027915SBrad.Beckmann@amd.com } 1037915SBrad.Beckmann@amd.com 1047039Snate@binkert.org inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 1056888SBrad.Beckmann@amd.com panic("register classification not implemented"); 1067039Snate@binkert.org return false; 1077039Snate@binkert.org } 1087453Snate@binkert.org 1096285Snate@binkert.org inline bool isCallerSaveFloatRegister(unsigned int reg) { 1107039Snate@binkert.org panic("register classification not implemented"); 1116285Snate@binkert.org return false; 1126285Snate@binkert.org } 1137039Snate@binkert.org 1147039Snate@binkert.org inline bool isCalleeSaveFloatRegister(unsigned int reg) { 1156285Snate@binkert.org panic("register classification not implemented"); 1167039Snate@binkert.org return false; 1177039Snate@binkert.org } 1187039Snate@binkert.org 1197544SBrad.Beckmann@amd.com // Instruction address compression hooks 1207039Snate@binkert.org inline Addr realPCToFetchPC(const Addr &addr) 1217039Snate@binkert.org { 1227039Snate@binkert.org return addr; 1237039Snate@binkert.org } 1246285Snate@binkert.org 1257453Snate@binkert.org inline Addr fetchPCToRealPC(const Addr &addr) 1267453Snate@binkert.org { 1277039Snate@binkert.org return addr; 1286888SBrad.Beckmann@amd.com } 1297453Snate@binkert.org 1307453Snate@binkert.org // the size of "fetched" instructions (not necessarily the size 1316888SBrad.Beckmann@amd.com // of real instructions for PISA) 1327453Snate@binkert.org inline size_t fetchInstSize() 1337039Snate@binkert.org { 1346888SBrad.Beckmann@amd.com return sizeof(MachInst); 1357453Snate@binkert.org } 1367039Snate@binkert.org 1377039Snate@binkert.org /** 1387039Snate@binkert.org * Function to insure ISA semantics about 0 registers. 1397039Snate@binkert.org * @param tc The thread context. 1406888SBrad.Beckmann@amd.com */ 1417039Snate@binkert.org template <class TC> 1427453Snate@binkert.org void zeroRegisters(TC *tc); 1437039Snate@binkert.org 1447453Snate@binkert.org#if FULL_SYSTEM 1457453Snate@binkert.org 1467039Snate@binkert.org void initCPU(ThreadContext *tc, int cpuId); 1477453Snate@binkert.org 1487039Snate@binkert.org#endif 1496888SBrad.Beckmann@amd.com 1507039Snate@binkert.org void startupCPU(ThreadContext *tc, int cpuId); 1517039Snate@binkert.org}; 1527453Snate@binkert.org 1537544SBrad.Beckmann@amd.com#endif // __ARCH_X86_UTILITY_HH__ 1546285Snate@binkert.org