utility.cc revision 9544:1a075d9bc1bc
112027Sjungma@eit.uni-kl.de/* 212027Sjungma@eit.uni-kl.de * Copyright (c) 2007 The Hewlett-Packard Development Company 312027Sjungma@eit.uni-kl.de * Copyright (c) 2011 Advanced Micro Devices, Inc. 412027Sjungma@eit.uni-kl.de * All rights reserved. 512027Sjungma@eit.uni-kl.de * 612027Sjungma@eit.uni-kl.de * The license below extends only to copyright in the software and shall 712027Sjungma@eit.uni-kl.de * not be construed as granting a license to any other intellectual 812027Sjungma@eit.uni-kl.de * property including but not limited to intellectual property relating 912027Sjungma@eit.uni-kl.de * to a hardware implementation of the functionality of the software 1012027Sjungma@eit.uni-kl.de * licensed hereunder. You may use the software subject to the license 1112027Sjungma@eit.uni-kl.de * terms below provided that you ensure that this notice is replicated 1212027Sjungma@eit.uni-kl.de * unmodified and in its entirety in all distributions of the software, 1312027Sjungma@eit.uni-kl.de * modified or unmodified, in source code or in binary form. 1412027Sjungma@eit.uni-kl.de * 1512027Sjungma@eit.uni-kl.de * Redistribution and use in source and binary forms, with or without 1612027Sjungma@eit.uni-kl.de * modification, are permitted provided that the following conditions are 1712027Sjungma@eit.uni-kl.de * met: redistributions of source code must retain the above copyright 1812027Sjungma@eit.uni-kl.de * notice, this list of conditions and the following disclaimer; 1912027Sjungma@eit.uni-kl.de * redistributions in binary form must reproduce the above copyright 2012027Sjungma@eit.uni-kl.de * notice, this list of conditions and the following disclaimer in the 2112027Sjungma@eit.uni-kl.de * documentation and/or other materials provided with the distribution; 2212027Sjungma@eit.uni-kl.de * neither the name of the copyright holders nor the names of its 2312027Sjungma@eit.uni-kl.de * contributors may be used to endorse or promote products derived from 2412027Sjungma@eit.uni-kl.de * this software without specific prior written permission. 2512027Sjungma@eit.uni-kl.de * 2612027Sjungma@eit.uni-kl.de * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2712027Sjungma@eit.uni-kl.de * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2812027Sjungma@eit.uni-kl.de * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2912027Sjungma@eit.uni-kl.de * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3012027Sjungma@eit.uni-kl.de * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3112027Sjungma@eit.uni-kl.de * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3212027Sjungma@eit.uni-kl.de * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3312027Sjungma@eit.uni-kl.de * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3412027Sjungma@eit.uni-kl.de * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3512027Sjungma@eit.uni-kl.de * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3612027Sjungma@eit.uni-kl.de * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3712027Sjungma@eit.uni-kl.de * 3812027Sjungma@eit.uni-kl.de * Authors: Gabe Black 3912027Sjungma@eit.uni-kl.de */ 4012027Sjungma@eit.uni-kl.de 4112027Sjungma@eit.uni-kl.de#include "arch/x86/interrupts.hh" 4212027Sjungma@eit.uni-kl.de#include "arch/x86/registers.hh" 4312027Sjungma@eit.uni-kl.de#include "arch/x86/tlb.hh" 4412027Sjungma@eit.uni-kl.de#include "arch/x86/utility.hh" 4512027Sjungma@eit.uni-kl.de#include "arch/x86/x86_traits.hh" 4612027Sjungma@eit.uni-kl.de#include "cpu/base.hh" 4712027Sjungma@eit.uni-kl.de#include "sim/system.hh" 4812027Sjungma@eit.uni-kl.de 4912027Sjungma@eit.uni-kl.denamespace X86ISA { 5012027Sjungma@eit.uni-kl.de 5112027Sjungma@eit.uni-kl.deuint64_t 5212027Sjungma@eit.uni-kl.degetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 5312027Sjungma@eit.uni-kl.de{ 5412027Sjungma@eit.uni-kl.de panic("getArgument() not implemented for x86!\n"); 5512027Sjungma@eit.uni-kl.de M5_DUMMY_RETURN 5612027Sjungma@eit.uni-kl.de} 5712027Sjungma@eit.uni-kl.de 5812027Sjungma@eit.uni-kl.devoid initCPU(ThreadContext *tc, int cpuId) 5912027Sjungma@eit.uni-kl.de{ 6012027Sjungma@eit.uni-kl.de // This function is essentially performing a reset. The actual INIT 6112027Sjungma@eit.uni-kl.de // interrupt does a subset of this, so we'll piggyback on some of its 6212027Sjungma@eit.uni-kl.de // functionality. 6312027Sjungma@eit.uni-kl.de InitInterrupt init(0); 6412027Sjungma@eit.uni-kl.de init.invoke(tc); 6512027Sjungma@eit.uni-kl.de 6612027Sjungma@eit.uni-kl.de PCState pc = tc->pcState(); 6712027Sjungma@eit.uni-kl.de pc.upc(0); 6812027Sjungma@eit.uni-kl.de pc.nupc(1); 6912027Sjungma@eit.uni-kl.de tc->pcState(pc); 7012027Sjungma@eit.uni-kl.de 7112027Sjungma@eit.uni-kl.de // These next two loops zero internal microcode and implicit registers. 7212027Sjungma@eit.uni-kl.de // They aren't specified by the ISA but are used internally by M5's 7312027Sjungma@eit.uni-kl.de // implementation. 7412027Sjungma@eit.uni-kl.de for (int index = 0; index < NumMicroIntRegs; index++) { 7512027Sjungma@eit.uni-kl.de tc->setIntReg(INTREG_MICRO(index), 0); 7612027Sjungma@eit.uni-kl.de } 7712027Sjungma@eit.uni-kl.de 7812027Sjungma@eit.uni-kl.de for (int index = 0; index < NumImplicitIntRegs; index++) { 7912027Sjungma@eit.uni-kl.de tc->setIntReg(INTREG_IMPLICIT(index), 0); 8012027Sjungma@eit.uni-kl.de } 8112027Sjungma@eit.uni-kl.de 8212027Sjungma@eit.uni-kl.de // Set integer register EAX to 0 to indicate that the optional BIST 8312027Sjungma@eit.uni-kl.de // passed. No BIST actually runs, but software may still check this 8412027Sjungma@eit.uni-kl.de // register for errors. 8512027Sjungma@eit.uni-kl.de tc->setIntReg(INTREG_RAX, 0); 8612027Sjungma@eit.uni-kl.de 8712027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL); 8812027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_CR8, 0); 8912027Sjungma@eit.uni-kl.de 9012027Sjungma@eit.uni-kl.de // TODO initialize x87, 64 bit, and 128 bit media state 9112027Sjungma@eit.uni-kl.de 9212027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRRCAP, 0x0508); 9312027Sjungma@eit.uni-kl.de for (int i = 0; i < 8; i++) { 9412027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0); 9512027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0); 9612027Sjungma@eit.uni-kl.de } 9712027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0); 9812027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0); 9912027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0); 10012027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0); 10112027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0); 10212027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0); 10312027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0); 10412027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0); 10512027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0); 10612027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0); 10712027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0); 10812027Sjungma@eit.uni-kl.de 10912027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_DEF_TYPE, 0); 11012027Sjungma@eit.uni-kl.de 11112027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MCG_CAP, 0x104); 11212027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MCG_STATUS, 0); 11312027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MCG_CTL, 0); 11412027Sjungma@eit.uni-kl.de 11512027Sjungma@eit.uni-kl.de for (int i = 0; i < 5; i++) { 11612027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MC_CTL(i), 0); 11712027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MC_STATUS(i), 0); 11812027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MC_ADDR(i), 0); 11912027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_MC_MISC(i), 0); 12012027Sjungma@eit.uni-kl.de } 12112027Sjungma@eit.uni-kl.de 12212027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_TSC, 0); 12312027Sjungma@eit.uni-kl.de tc->setMiscReg(MISCREG_TSC_AUX, 0); 124 125 for (int i = 0; i < 4; i++) { 126 tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0); 127 tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0); 128 } 129 130 tc->setMiscReg(MISCREG_STAR, 0); 131 tc->setMiscReg(MISCREG_LSTAR, 0); 132 tc->setMiscReg(MISCREG_CSTAR, 0); 133 134 tc->setMiscReg(MISCREG_SF_MASK, 0); 135 136 tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0); 137 138 tc->setMiscReg(MISCREG_SYSENTER_CS, 0); 139 tc->setMiscReg(MISCREG_SYSENTER_ESP, 0); 140 tc->setMiscReg(MISCREG_SYSENTER_EIP, 0); 141 142 tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL); 143 144 tc->setMiscReg(MISCREG_SYSCFG, 0x20601); 145 146 tc->setMiscReg(MISCREG_IORR_BASE0, 0); 147 tc->setMiscReg(MISCREG_IORR_BASE1, 0); 148 149 tc->setMiscReg(MISCREG_IORR_MASK0, 0); 150 tc->setMiscReg(MISCREG_IORR_MASK1, 0); 151 152 tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000); 153 tc->setMiscReg(MISCREG_TOP_MEM2, 0x0); 154 155 tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0); 156 tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0); 157 tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0); 158 tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0); 159 tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0); 160 161 // Invalidate the caches (this should already be done for us) 162 163 LocalApicBase lApicBase = 0; 164 lApicBase.base = 0xFEE00000 >> 12; 165 lApicBase.enable = 1; 166 lApicBase.bsp = (cpuId == 0); 167 tc->setMiscReg(MISCREG_APIC_BASE, lApicBase); 168 169 Interrupts * interrupts = dynamic_cast<Interrupts *>( 170 tc->getCpuPtr()->getInterruptController()); 171 assert(interrupts); 172 173 interrupts->setRegNoEffect(APIC_ID, cpuId << 24); 174 175 interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14); 176 177 // TODO Set the SMRAM base address (SMBASE) to 0x00030000 178 179 tc->setMiscReg(MISCREG_VM_CR, 0); 180 tc->setMiscReg(MISCREG_IGNNE, 0); 181 tc->setMiscReg(MISCREG_SMM_CTL, 0); 182 tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0); 183} 184 185void startupCPU(ThreadContext *tc, int cpuId) 186{ 187 if (cpuId == 0 || !FullSystem) { 188 tc->activate(Cycles(0)); 189 } else { 190 // This is an application processor (AP). It should be initialized to 191 // look like only the BIOS POST has run on it and put then put it into 192 // a halted state. 193 tc->suspend(Cycles(0)); 194 } 195} 196 197void 198copyMiscRegs(ThreadContext *src, ThreadContext *dest) 199{ 200 // This function assumes no side effects other than TLB invalidation 201 // need to be considered while copying state. That will likely not be 202 // true in the future. 203 for (int i = 0; i < NUM_MISCREGS; ++i) { 204 if ( ( i != MISCREG_CR1 && 205 !(i > MISCREG_CR4 && i < MISCREG_CR8) && 206 !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) { 207 continue; 208 } 209 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 210 } 211 212 dest->getITBPtr()->flushAll(); 213 dest->getDTBPtr()->flushAll(); 214} 215 216void 217copyRegs(ThreadContext *src, ThreadContext *dest) 218{ 219 //copy int regs 220 for (int i = 0; i < NumIntRegs; ++i) 221 dest->setIntReg(i, src->readIntReg(i)); 222 //copy float regs 223 for (int i = 0; i < NumFloatRegs; ++i) 224 dest->setFloatRegBits(i, src->readFloatRegBits(i)); 225 copyMiscRegs(src, dest); 226 dest->pcState(src->pcState()); 227} 228 229void 230skipFunction(ThreadContext *tc) 231{ 232 panic("Not implemented for x86\n"); 233} 234 235 236} // namespace X86_ISA 237