utility.cc revision 7707
15086Sgblack@eecs.umich.edu/* 25086Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 35086Sgblack@eecs.umich.edu * All rights reserved. 45086Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 135086Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 157087Snate@binkert.org * modification, are permitted provided that the following conditions are 167087Snate@binkert.org * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 225086Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 245086Sgblack@eecs.umich.edu * 255086Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 265086Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 275086Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 285086Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 295086Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 305086Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 315086Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 325086Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 335086Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 345086Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 355086Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 365086Sgblack@eecs.umich.edu * 375086Sgblack@eecs.umich.edu * Authors: Gabe Black 385086Sgblack@eecs.umich.edu */ 395086Sgblack@eecs.umich.edu 405647Sgblack@eecs.umich.edu#include "config/full_system.hh" 415647Sgblack@eecs.umich.edu 425647Sgblack@eecs.umich.edu#if FULL_SYSTEM 435647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 445647Sgblack@eecs.umich.edu#endif 457629Sgblack@eecs.umich.edu#include "arch/x86/regs/int.hh" 467629Sgblack@eecs.umich.edu#include "arch/x86/regs/misc.hh" 477629Sgblack@eecs.umich.edu#include "arch/x86/regs/segment.hh" 485086Sgblack@eecs.umich.edu#include "arch/x86/utility.hh" 495135Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 505647Sgblack@eecs.umich.edu#include "cpu/base.hh" 515234Sgblack@eecs.umich.edu#include "sim/system.hh" 525086Sgblack@eecs.umich.edu 535086Sgblack@eecs.umich.edunamespace X86ISA { 545086Sgblack@eecs.umich.edu 557707Sgblack@eecs.umich.eduuint64_t 567707Sgblack@eecs.umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 577707Sgblack@eecs.umich.edu{ 585086Sgblack@eecs.umich.edu#if FULL_SYSTEM 595086Sgblack@eecs.umich.edu panic("getArgument() not implemented for x86!\n"); 605086Sgblack@eecs.umich.edu#else 615086Sgblack@eecs.umich.edu panic("getArgument() only implemented for FULL_SYSTEM\n"); 625086Sgblack@eecs.umich.edu M5_DUMMY_RETURN 635086Sgblack@eecs.umich.edu#endif 645086Sgblack@eecs.umich.edu} 655135Sgblack@eecs.umich.edu 665135Sgblack@eecs.umich.edu# if FULL_SYSTEM 675135Sgblack@eecs.umich.eduvoid initCPU(ThreadContext *tc, int cpuId) 685135Sgblack@eecs.umich.edu{ 696048Sgblack@eecs.umich.edu // This function is essentially performing a reset. The actual INIT 706048Sgblack@eecs.umich.edu // interrupt does a subset of this, so we'll piggyback on some of its 716048Sgblack@eecs.umich.edu // functionality. 726048Sgblack@eecs.umich.edu InitInterrupt init(0); 736048Sgblack@eecs.umich.edu init.invoke(tc); 746048Sgblack@eecs.umich.edu 756048Sgblack@eecs.umich.edu tc->setMicroPC(0); 766048Sgblack@eecs.umich.edu tc->setNextMicroPC(1); 775135Sgblack@eecs.umich.edu 785135Sgblack@eecs.umich.edu // These next two loops zero internal microcode and implicit registers. 795135Sgblack@eecs.umich.edu // They aren't specified by the ISA but are used internally by M5's 805135Sgblack@eecs.umich.edu // implementation. 815135Sgblack@eecs.umich.edu for (int index = 0; index < NumMicroIntRegs; index++) { 825135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_MICRO(index), 0); 835135Sgblack@eecs.umich.edu } 845135Sgblack@eecs.umich.edu 855135Sgblack@eecs.umich.edu for (int index = 0; index < NumImplicitIntRegs; index++) { 865135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_IMPLICIT(index), 0); 875135Sgblack@eecs.umich.edu } 885135Sgblack@eecs.umich.edu 895135Sgblack@eecs.umich.edu // Set integer register EAX to 0 to indicate that the optional BIST 905135Sgblack@eecs.umich.edu // passed. No BIST actually runs, but software may still check this 915135Sgblack@eecs.umich.edu // register for errors. 925135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_RAX, 0); 935135Sgblack@eecs.umich.edu 945264Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL); 955135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR8, 0); 965135Sgblack@eecs.umich.edu 975135Sgblack@eecs.umich.edu // TODO initialize x87, 64 bit, and 128 bit media state 985135Sgblack@eecs.umich.edu 995141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRRCAP, 0x0508); 1005141Sgblack@eecs.umich.edu for (int i = 0; i < 8; i++) { 1015141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0); 1025141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0); 1035141Sgblack@eecs.umich.edu } 1045141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0); 1055141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0); 1065141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0); 1075141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0); 1085182Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0); 1095141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0); 1105141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0); 1115141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0); 1125141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0); 1135141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0); 1145141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0); 1155135Sgblack@eecs.umich.edu 1165141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DEF_TYPE, 0); 1175141Sgblack@eecs.umich.edu 1185141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_CAP, 0x104); 1195141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_STATUS, 0); 1205141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_CTL, 0); 1215141Sgblack@eecs.umich.edu 1225141Sgblack@eecs.umich.edu for (int i = 0; i < 5; i++) { 1235141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_CTL(i), 0); 1245141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_STATUS(i), 0); 1255141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_ADDR(i), 0); 1265141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_MISC(i), 0); 1275141Sgblack@eecs.umich.edu } 1285135Sgblack@eecs.umich.edu 1295141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TSC, 0); 1305141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TSC_AUX, 0); 1315135Sgblack@eecs.umich.edu 1325141Sgblack@eecs.umich.edu for (int i = 0; i < 4; i++) { 1335141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0); 1345141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0); 1355141Sgblack@eecs.umich.edu } 1365135Sgblack@eecs.umich.edu 1375141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_STAR, 0); 1385141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LSTAR, 0); 1395141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CSTAR, 0); 1405141Sgblack@eecs.umich.edu 1415141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SF_MASK, 0); 1425141Sgblack@eecs.umich.edu 1435141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0); 1445141Sgblack@eecs.umich.edu 1455141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_CS, 0); 1465141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_ESP, 0); 1475141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_EIP, 0); 1485141Sgblack@eecs.umich.edu 1495264Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL); 1505141Sgblack@eecs.umich.edu 1515141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSCFG, 0x20601); 1525141Sgblack@eecs.umich.edu 1535141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_BASE0, 0); 1545141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_BASE1, 0); 1555141Sgblack@eecs.umich.edu 1565141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_MASK0, 0); 1575141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_MASK1, 0); 1585141Sgblack@eecs.umich.edu 1595141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000); 1605141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TOP_MEM2, 0x0); 1615141Sgblack@eecs.umich.edu 1625141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0); 1635141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0); 1645141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0); 1655141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0); 1665141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0); 1675135Sgblack@eecs.umich.edu 1685135Sgblack@eecs.umich.edu // Invalidate the caches (this should already be done for us) 1695135Sgblack@eecs.umich.edu 1705360Sgblack@eecs.umich.edu LocalApicBase lApicBase = 0; 1715360Sgblack@eecs.umich.edu lApicBase.base = 0xFEE00000 >> 12; 1725360Sgblack@eecs.umich.edu lApicBase.enable = 1; 1735360Sgblack@eecs.umich.edu lApicBase.bsp = (cpuId == 0); 1745360Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_APIC_BASE, lApicBase); 1755360Sgblack@eecs.umich.edu 1765647Sgblack@eecs.umich.edu Interrupts * interrupts = dynamic_cast<Interrupts *>( 1775647Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 1785647Sgblack@eecs.umich.edu assert(interrupts); 1795360Sgblack@eecs.umich.edu 1805647Sgblack@eecs.umich.edu interrupts->setRegNoEffect(APIC_ID, cpuId << 24); 1815647Sgblack@eecs.umich.edu 1825647Sgblack@eecs.umich.edu interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14); 1835648Sgblack@eecs.umich.edu 1845648Sgblack@eecs.umich.edu interrupts->setClock(tc->getCpuPtr()->ticks(16)); 1855360Sgblack@eecs.umich.edu 1865141Sgblack@eecs.umich.edu // TODO Set the SMRAM base address (SMBASE) to 0x00030000 1875141Sgblack@eecs.umich.edu 1885141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_VM_CR, 0); 1895141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IGNNE, 0); 1905141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SMM_CTL, 0); 1915141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0); 1925135Sgblack@eecs.umich.edu} 1935135Sgblack@eecs.umich.edu 1945135Sgblack@eecs.umich.edu#endif 1955135Sgblack@eecs.umich.edu 1965135Sgblack@eecs.umich.eduvoid startupCPU(ThreadContext *tc, int cpuId) 1975135Sgblack@eecs.umich.edu{ 1986042Sgblack@eecs.umich.edu#if FULL_SYSTEM 1995135Sgblack@eecs.umich.edu if (cpuId == 0) { 2005135Sgblack@eecs.umich.edu tc->activate(0); 2015135Sgblack@eecs.umich.edu } else { 2025135Sgblack@eecs.umich.edu // This is an application processor (AP). It should be initialized to 2035135Sgblack@eecs.umich.edu // look like only the BIOS POST has run on it and put then put it into 2045135Sgblack@eecs.umich.edu // a halted state. 2056042Sgblack@eecs.umich.edu tc->suspend(0); 2065135Sgblack@eecs.umich.edu } 2076042Sgblack@eecs.umich.edu#else 2086042Sgblack@eecs.umich.edu tc->activate(0); 2096042Sgblack@eecs.umich.edu#endif 2105135Sgblack@eecs.umich.edu} 2115135Sgblack@eecs.umich.edu 2126329Sgblack@eecs.umich.eduvoid 2136329Sgblack@eecs.umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest) 2146329Sgblack@eecs.umich.edu{ 2156329Sgblack@eecs.umich.edu warn("copyMiscRegs is naively implemented for x86\n"); 2166329Sgblack@eecs.umich.edu for (int i = 0; i < NUM_MISCREGS; ++i) { 2176329Sgblack@eecs.umich.edu if ( ( i != MISCREG_CR1 && 2186329Sgblack@eecs.umich.edu !(i > MISCREG_CR4 && i < MISCREG_CR8) && 2196329Sgblack@eecs.umich.edu !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) { 2206329Sgblack@eecs.umich.edu continue; 2216329Sgblack@eecs.umich.edu } 2226329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 2236329Sgblack@eecs.umich.edu } 2246329Sgblack@eecs.umich.edu} 2256329Sgblack@eecs.umich.edu 2266329Sgblack@eecs.umich.eduvoid 2276329Sgblack@eecs.umich.educopyRegs(ThreadContext *src, ThreadContext *dest) 2286329Sgblack@eecs.umich.edu{ 2296329Sgblack@eecs.umich.edu panic("copyRegs not implemented for x86!\n"); 2306329Sgblack@eecs.umich.edu //copy int regs 2316329Sgblack@eecs.umich.edu //copy float regs 2326329Sgblack@eecs.umich.edu copyMiscRegs(src, dest); 2336329Sgblack@eecs.umich.edu 2346329Sgblack@eecs.umich.edu dest->setPC(src->readPC()); 2356329Sgblack@eecs.umich.edu dest->setNextPC(src->readNextPC()); 2366329Sgblack@eecs.umich.edu} 2376329Sgblack@eecs.umich.edu 2387693SAli.Saidi@ARM.comvoid 2397693SAli.Saidi@ARM.comskipFunction(ThreadContext *tc) 2407693SAli.Saidi@ARM.com{ 2417693SAli.Saidi@ARM.com panic("Not implemented for x86\n"); 2427693SAli.Saidi@ARM.com} 2437693SAli.Saidi@ARM.com 2447693SAli.Saidi@ARM.com 2455086Sgblack@eecs.umich.edu} //namespace X86_ISA 246