utility.cc revision 6329
15086Sgblack@eecs.umich.edu/* 25086Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 35086Sgblack@eecs.umich.edu * All rights reserved. 45086Sgblack@eecs.umich.edu * 55086Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 65086Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 75086Sgblack@eecs.umich.edu * following conditions are met: 85086Sgblack@eecs.umich.edu * 95086Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 105086Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 115086Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. Illustrative 125086Sgblack@eecs.umich.edu * examples of non-commercial use are academic research, personal study, 135086Sgblack@eecs.umich.edu * teaching, education and corporate research & development. 145086Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for 155086Sgblack@eecs.umich.edu * commercial advantage and providing services using the software for 165086Sgblack@eecs.umich.edu * commercial advantage. 175086Sgblack@eecs.umich.edu * 185086Sgblack@eecs.umich.edu * If you wish to use this software or functionality therein that may be 195086Sgblack@eecs.umich.edu * covered by patents for commercial use, please contact: 205086Sgblack@eecs.umich.edu * Director of Intellectual Property Licensing 215086Sgblack@eecs.umich.edu * Office of Strategy and Technology 225086Sgblack@eecs.umich.edu * Hewlett-Packard Company 235086Sgblack@eecs.umich.edu * 1501 Page Mill Road 245086Sgblack@eecs.umich.edu * Palo Alto, California 94304 255086Sgblack@eecs.umich.edu * 265086Sgblack@eecs.umich.edu * Redistributions of source code must retain the above copyright notice, 275086Sgblack@eecs.umich.edu * this list of conditions and the following disclaimer. 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IN NO EVENT SHALL THE COPYRIGHT 475086Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 485086Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 495086Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 505086Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 515086Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 525086Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 535086Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 545086Sgblack@eecs.umich.edu * 555086Sgblack@eecs.umich.edu * Authors: Gabe Black 565086Sgblack@eecs.umich.edu */ 575086Sgblack@eecs.umich.edu 585647Sgblack@eecs.umich.edu#include "config/full_system.hh" 595647Sgblack@eecs.umich.edu 605647Sgblack@eecs.umich.edu#if FULL_SYSTEM 615647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 625647Sgblack@eecs.umich.edu#endif 635135Sgblack@eecs.umich.edu#include "arch/x86/intregs.hh" 645135Sgblack@eecs.umich.edu#include "arch/x86/miscregs.hh" 655135Sgblack@eecs.umich.edu#include "arch/x86/segmentregs.hh" 665086Sgblack@eecs.umich.edu#include "arch/x86/utility.hh" 675135Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 685647Sgblack@eecs.umich.edu#include "cpu/base.hh" 695234Sgblack@eecs.umich.edu#include "sim/system.hh" 705086Sgblack@eecs.umich.edu 715086Sgblack@eecs.umich.edunamespace X86ISA { 725086Sgblack@eecs.umich.edu 735086Sgblack@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int number, bool fp) { 745086Sgblack@eecs.umich.edu#if FULL_SYSTEM 755086Sgblack@eecs.umich.edu panic("getArgument() not implemented for x86!\n"); 765086Sgblack@eecs.umich.edu#else 775086Sgblack@eecs.umich.edu panic("getArgument() only implemented for FULL_SYSTEM\n"); 785086Sgblack@eecs.umich.edu M5_DUMMY_RETURN 795086Sgblack@eecs.umich.edu#endif 805086Sgblack@eecs.umich.edu} 815135Sgblack@eecs.umich.edu 825135Sgblack@eecs.umich.edu# if FULL_SYSTEM 835135Sgblack@eecs.umich.eduvoid initCPU(ThreadContext *tc, int cpuId) 845135Sgblack@eecs.umich.edu{ 856048Sgblack@eecs.umich.edu // This function is essentially performing a reset. The actual INIT 866048Sgblack@eecs.umich.edu // interrupt does a subset of this, so we'll piggyback on some of its 876048Sgblack@eecs.umich.edu // functionality. 886048Sgblack@eecs.umich.edu InitInterrupt init(0); 896048Sgblack@eecs.umich.edu init.invoke(tc); 906048Sgblack@eecs.umich.edu 916048Sgblack@eecs.umich.edu tc->setMicroPC(0); 926048Sgblack@eecs.umich.edu tc->setNextMicroPC(1); 935135Sgblack@eecs.umich.edu 945135Sgblack@eecs.umich.edu // These next two loops zero internal microcode and implicit registers. 955135Sgblack@eecs.umich.edu // They aren't specified by the ISA but are used internally by M5's 965135Sgblack@eecs.umich.edu // implementation. 975135Sgblack@eecs.umich.edu for (int index = 0; index < NumMicroIntRegs; index++) { 985135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_MICRO(index), 0); 995135Sgblack@eecs.umich.edu } 1005135Sgblack@eecs.umich.edu 1015135Sgblack@eecs.umich.edu for (int index = 0; index < NumImplicitIntRegs; index++) { 1025135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_IMPLICIT(index), 0); 1035135Sgblack@eecs.umich.edu } 1045135Sgblack@eecs.umich.edu 1055135Sgblack@eecs.umich.edu // Set integer register EAX to 0 to indicate that the optional BIST 1065135Sgblack@eecs.umich.edu // passed. No BIST actually runs, but software may still check this 1075135Sgblack@eecs.umich.edu // register for errors. 1085135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_RAX, 0); 1095135Sgblack@eecs.umich.edu 1105264Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL); 1115135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR8, 0); 1125135Sgblack@eecs.umich.edu 1135135Sgblack@eecs.umich.edu // TODO initialize x87, 64 bit, and 128 bit media state 1145135Sgblack@eecs.umich.edu 1155141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRRCAP, 0x0508); 1165141Sgblack@eecs.umich.edu for (int i = 0; i < 8; i++) { 1175141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0); 1185141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0); 1195141Sgblack@eecs.umich.edu } 1205141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0); 1215141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0); 1225141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0); 1235141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0); 1245182Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0); 1255141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0); 1265141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0); 1275141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0); 1285141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0); 1295141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0); 1305141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0); 1315135Sgblack@eecs.umich.edu 1325141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DEF_TYPE, 0); 1335141Sgblack@eecs.umich.edu 1345141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_CAP, 0x104); 1355141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_STATUS, 0); 1365141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_CTL, 0); 1375141Sgblack@eecs.umich.edu 1385141Sgblack@eecs.umich.edu for (int i = 0; i < 5; i++) { 1395141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_CTL(i), 0); 1405141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_STATUS(i), 0); 1415141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_ADDR(i), 0); 1425141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_MISC(i), 0); 1435141Sgblack@eecs.umich.edu } 1445135Sgblack@eecs.umich.edu 1455141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TSC, 0); 1465141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TSC_AUX, 0); 1475135Sgblack@eecs.umich.edu 1485141Sgblack@eecs.umich.edu for (int i = 0; i < 4; i++) { 1495141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0); 1505141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0); 1515141Sgblack@eecs.umich.edu } 1525135Sgblack@eecs.umich.edu 1535141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_STAR, 0); 1545141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LSTAR, 0); 1555141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CSTAR, 0); 1565141Sgblack@eecs.umich.edu 1575141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SF_MASK, 0); 1585141Sgblack@eecs.umich.edu 1595141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0); 1605141Sgblack@eecs.umich.edu 1615141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_CS, 0); 1625141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_ESP, 0); 1635141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_EIP, 0); 1645141Sgblack@eecs.umich.edu 1655264Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL); 1665141Sgblack@eecs.umich.edu 1675141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSCFG, 0x20601); 1685141Sgblack@eecs.umich.edu 1695141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_BASE0, 0); 1705141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_BASE1, 0); 1715141Sgblack@eecs.umich.edu 1725141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_MASK0, 0); 1735141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_MASK1, 0); 1745141Sgblack@eecs.umich.edu 1755141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000); 1765141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TOP_MEM2, 0x0); 1775141Sgblack@eecs.umich.edu 1785141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0); 1795141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0); 1805141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0); 1815141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0); 1825141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0); 1835135Sgblack@eecs.umich.edu 1845135Sgblack@eecs.umich.edu // Invalidate the caches (this should already be done for us) 1855135Sgblack@eecs.umich.edu 1865360Sgblack@eecs.umich.edu LocalApicBase lApicBase = 0; 1875360Sgblack@eecs.umich.edu lApicBase.base = 0xFEE00000 >> 12; 1885360Sgblack@eecs.umich.edu lApicBase.enable = 1; 1895360Sgblack@eecs.umich.edu lApicBase.bsp = (cpuId == 0); 1905360Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_APIC_BASE, lApicBase); 1915360Sgblack@eecs.umich.edu 1925647Sgblack@eecs.umich.edu Interrupts * interrupts = dynamic_cast<Interrupts *>( 1935647Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 1945647Sgblack@eecs.umich.edu assert(interrupts); 1955360Sgblack@eecs.umich.edu 1965647Sgblack@eecs.umich.edu interrupts->setRegNoEffect(APIC_ID, cpuId << 24); 1975647Sgblack@eecs.umich.edu 1985647Sgblack@eecs.umich.edu interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14); 1995648Sgblack@eecs.umich.edu 2005648Sgblack@eecs.umich.edu interrupts->setClock(tc->getCpuPtr()->ticks(16)); 2015360Sgblack@eecs.umich.edu 2025141Sgblack@eecs.umich.edu // TODO Set the SMRAM base address (SMBASE) to 0x00030000 2035141Sgblack@eecs.umich.edu 2045141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_VM_CR, 0); 2055141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IGNNE, 0); 2065141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SMM_CTL, 0); 2075141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0); 2085135Sgblack@eecs.umich.edu} 2095135Sgblack@eecs.umich.edu 2105135Sgblack@eecs.umich.edu#endif 2115135Sgblack@eecs.umich.edu 2125135Sgblack@eecs.umich.eduvoid startupCPU(ThreadContext *tc, int cpuId) 2135135Sgblack@eecs.umich.edu{ 2146042Sgblack@eecs.umich.edu#if FULL_SYSTEM 2155135Sgblack@eecs.umich.edu if (cpuId == 0) { 2165135Sgblack@eecs.umich.edu tc->activate(0); 2175135Sgblack@eecs.umich.edu } else { 2185135Sgblack@eecs.umich.edu // This is an application processor (AP). It should be initialized to 2195135Sgblack@eecs.umich.edu // look like only the BIOS POST has run on it and put then put it into 2205135Sgblack@eecs.umich.edu // a halted state. 2216042Sgblack@eecs.umich.edu tc->suspend(0); 2225135Sgblack@eecs.umich.edu } 2236042Sgblack@eecs.umich.edu#else 2246042Sgblack@eecs.umich.edu tc->activate(0); 2256042Sgblack@eecs.umich.edu#endif 2265135Sgblack@eecs.umich.edu} 2275135Sgblack@eecs.umich.edu 2286329Sgblack@eecs.umich.eduvoid 2296329Sgblack@eecs.umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest) 2306329Sgblack@eecs.umich.edu{ 2316329Sgblack@eecs.umich.edu warn("copyMiscRegs is naively implemented for x86\n"); 2326329Sgblack@eecs.umich.edu for (int i = 0; i < NUM_MISCREGS; ++i) { 2336329Sgblack@eecs.umich.edu if ( ( i != MISCREG_CR1 && 2346329Sgblack@eecs.umich.edu !(i > MISCREG_CR4 && i < MISCREG_CR8) && 2356329Sgblack@eecs.umich.edu !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) { 2366329Sgblack@eecs.umich.edu continue; 2376329Sgblack@eecs.umich.edu } 2386329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 2396329Sgblack@eecs.umich.edu } 2406329Sgblack@eecs.umich.edu} 2416329Sgblack@eecs.umich.edu 2426329Sgblack@eecs.umich.eduvoid 2436329Sgblack@eecs.umich.educopyRegs(ThreadContext *src, ThreadContext *dest) 2446329Sgblack@eecs.umich.edu{ 2456329Sgblack@eecs.umich.edu panic("copyRegs not implemented for x86!\n"); 2466329Sgblack@eecs.umich.edu //copy int regs 2476329Sgblack@eecs.umich.edu //copy float regs 2486329Sgblack@eecs.umich.edu copyMiscRegs(src, dest); 2496329Sgblack@eecs.umich.edu 2506329Sgblack@eecs.umich.edu dest->setPC(src->readPC()); 2516329Sgblack@eecs.umich.edu dest->setNextPC(src->readNextPC()); 2526329Sgblack@eecs.umich.edu} 2536329Sgblack@eecs.umich.edu 2545086Sgblack@eecs.umich.edu} //namespace X86_ISA 255