utility.cc revision 5141
15086Sgblack@eecs.umich.edu/* 25086Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 35086Sgblack@eecs.umich.edu * All rights reserved. 45086Sgblack@eecs.umich.edu * 55086Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 65086Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 75086Sgblack@eecs.umich.edu * following conditions are met: 85086Sgblack@eecs.umich.edu * 95086Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 105086Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 115086Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. 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IN NO EVENT SHALL THE COPYRIGHT 475086Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 485086Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 495086Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 505086Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 515086Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 525086Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 535086Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 545086Sgblack@eecs.umich.edu * 555086Sgblack@eecs.umich.edu * Authors: Gabe Black 565086Sgblack@eecs.umich.edu */ 575086Sgblack@eecs.umich.edu 585135Sgblack@eecs.umich.edu#include "arch/x86/intregs.hh" 595135Sgblack@eecs.umich.edu#include "arch/x86/miscregs.hh" 605135Sgblack@eecs.umich.edu#include "arch/x86/segmentregs.hh" 615086Sgblack@eecs.umich.edu#include "arch/x86/utility.hh" 625135Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 635086Sgblack@eecs.umich.edu 645086Sgblack@eecs.umich.edunamespace X86ISA { 655086Sgblack@eecs.umich.edu 665086Sgblack@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int number, bool fp) { 675086Sgblack@eecs.umich.edu#if FULL_SYSTEM 685086Sgblack@eecs.umich.edu panic("getArgument() not implemented for x86!\n"); 695086Sgblack@eecs.umich.edu#else 705086Sgblack@eecs.umich.edu panic("getArgument() only implemented for FULL_SYSTEM\n"); 715086Sgblack@eecs.umich.edu M5_DUMMY_RETURN 725086Sgblack@eecs.umich.edu#endif 735086Sgblack@eecs.umich.edu} 745135Sgblack@eecs.umich.edu 755135Sgblack@eecs.umich.edu# if FULL_SYSTEM 765135Sgblack@eecs.umich.eduvoid initCPU(ThreadContext *tc, int cpuId) 775135Sgblack@eecs.umich.edu{ 785135Sgblack@eecs.umich.edu // The otherwise unmodified integer registers should be set to 0. 795135Sgblack@eecs.umich.edu for (int index = 0; index < NUM_INTREGS; index++) { 805135Sgblack@eecs.umich.edu tc->setIntReg(index, 0); 815135Sgblack@eecs.umich.edu } 825135Sgblack@eecs.umich.edu 835135Sgblack@eecs.umich.edu // These next two loops zero internal microcode and implicit registers. 845135Sgblack@eecs.umich.edu // They aren't specified by the ISA but are used internally by M5's 855135Sgblack@eecs.umich.edu // implementation. 865135Sgblack@eecs.umich.edu for (int index = 0; index < NumMicroIntRegs; index++) { 875135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_MICRO(index), 0); 885135Sgblack@eecs.umich.edu } 895135Sgblack@eecs.umich.edu 905135Sgblack@eecs.umich.edu for (int index = 0; index < NumImplicitIntRegs; index++) { 915135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_IMPLICIT(index), 0); 925135Sgblack@eecs.umich.edu } 935135Sgblack@eecs.umich.edu 945135Sgblack@eecs.umich.edu // Set integer register EAX to 0 to indicate that the optional BIST 955135Sgblack@eecs.umich.edu // passed. No BIST actually runs, but software may still check this 965135Sgblack@eecs.umich.edu // register for errors. 975135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_RAX, 0); 985135Sgblack@eecs.umich.edu 995135Sgblack@eecs.umich.edu //The following values are dictated by the architecture for after a RESET# 1005135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, 0x0000000060000010); 1015135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR2, 0); 1025135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR3, 0); 1035135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR4, 0); 1045135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR8, 0); 1055135Sgblack@eecs.umich.edu 1065135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002); 1075135Sgblack@eecs.umich.edu 1085135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_EFER, 0); 1095135Sgblack@eecs.umich.edu 1105141Sgblack@eecs.umich.edu SegAttr dataAttr = 0; 1115141Sgblack@eecs.umich.edu dataAttr.writable = 1; 1125141Sgblack@eecs.umich.edu dataAttr.readable = 1; 1135141Sgblack@eecs.umich.edu dataAttr.expandDown = 0; 1145141Sgblack@eecs.umich.edu dataAttr.dpl = 0; 1155141Sgblack@eecs.umich.edu dataAttr.defaultSize = 0; 1165141Sgblack@eecs.umich.edu 1175135Sgblack@eecs.umich.edu for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) { 1185135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_SEL(seg), 0); 1195135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_BASE(seg), 0); 1205135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff); 1215141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr); 1225135Sgblack@eecs.umich.edu } 1235135Sgblack@eecs.umich.edu 1245141Sgblack@eecs.umich.edu SegAttr codeAttr = 0; 1255141Sgblack@eecs.umich.edu codeAttr.writable = 0; 1265141Sgblack@eecs.umich.edu codeAttr.readable = 1; 1275141Sgblack@eecs.umich.edu codeAttr.expandDown = 0; 1285141Sgblack@eecs.umich.edu codeAttr.dpl = 0; 1295141Sgblack@eecs.umich.edu codeAttr.defaultSize = 0; 1305141Sgblack@eecs.umich.edu 1315135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS, 0xf000); 1325135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000); 1335135Sgblack@eecs.umich.edu // This has the base value pre-added. 1345135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff); 1355141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS_ATTR, codeAttr); 1365135Sgblack@eecs.umich.edu 1375135Sgblack@eecs.umich.edu tc->setPC(0x000000000000fff0 + 1385135Sgblack@eecs.umich.edu tc->readMiscReg(MISCREG_CS_BASE)); 1395135Sgblack@eecs.umich.edu tc->setNextPC(tc->readPC() + sizeof(MachInst)); 1405135Sgblack@eecs.umich.edu 1415135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_GDTR_BASE, 0); 1425135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff); 1435135Sgblack@eecs.umich.edu 1445135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IDTR_BASE, 0); 1455135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); 1465135Sgblack@eecs.umich.edu 1475135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LDTR, 0); 1485135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LDTR_BASE, 0); 1495135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff); 1505135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LDTR_ATTR, 0); 1515135Sgblack@eecs.umich.edu 1525135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TR, 0); 1535135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TR_BASE, 0); 1545135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff); 1555135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TR_ATTR, 0); 1565135Sgblack@eecs.umich.edu 1575135Sgblack@eecs.umich.edu // This value should be the family/model/stepping of the processor. 1585135Sgblack@eecs.umich.edu // (page 418). It should be consistent with the value from CPUID, but the 1595135Sgblack@eecs.umich.edu // actual value probably doesn't matter much. 1605135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_RDX, 0); 1615135Sgblack@eecs.umich.edu 1625135Sgblack@eecs.umich.edu // TODO initialize x87, 64 bit, and 128 bit media state 1635135Sgblack@eecs.umich.edu 1645141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRRCAP, 0x0508); 1655141Sgblack@eecs.umich.edu for (int i = 0; i < 8; i++) { 1665141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0); 1675141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0); 1685141Sgblack@eecs.umich.edu } 1695141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0); 1705141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0); 1715141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0); 1725141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0); 1735141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4k_C8000, 0); 1745141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0); 1755141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0); 1765141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0); 1775141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0); 1785141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0); 1795141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0); 1805135Sgblack@eecs.umich.edu 1815141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DEF_TYPE, 0); 1825141Sgblack@eecs.umich.edu 1835141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_CAP, 0x104); 1845141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_STATUS, 0); 1855141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_CTL, 0); 1865141Sgblack@eecs.umich.edu 1875141Sgblack@eecs.umich.edu for (int i = 0; i < 5; i++) { 1885141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_CTL(i), 0); 1895141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_STATUS(i), 0); 1905141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_ADDR(i), 0); 1915141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_MISC(i), 0); 1925141Sgblack@eecs.umich.edu } 1935135Sgblack@eecs.umich.edu 1945135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR0, 0); 1955135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR1, 0); 1965135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR2, 0); 1975135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR3, 0); 1985135Sgblack@eecs.umich.edu 1995135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0); 2005135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR7, 0x0000000000000400); 2015135Sgblack@eecs.umich.edu 2025141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TSC, 0); 2035141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TSC_AUX, 0); 2045135Sgblack@eecs.umich.edu 2055141Sgblack@eecs.umich.edu for (int i = 0; i < 4; i++) { 2065141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0); 2075141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0); 2085141Sgblack@eecs.umich.edu } 2095135Sgblack@eecs.umich.edu 2105141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_STAR, 0); 2115141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LSTAR, 0); 2125141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CSTAR, 0); 2135141Sgblack@eecs.umich.edu 2145141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SF_MASK, 0); 2155141Sgblack@eecs.umich.edu 2165141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0); 2175141Sgblack@eecs.umich.edu 2185141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_CS, 0); 2195141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_ESP, 0); 2205141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_EIP, 0); 2215141Sgblack@eecs.umich.edu 2225141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PAT, 0x0007040600070406); 2235141Sgblack@eecs.umich.edu 2245141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSCFG, 0x20601); 2255141Sgblack@eecs.umich.edu 2265141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_BASE0, 0); 2275141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_BASE1, 0); 2285141Sgblack@eecs.umich.edu 2295141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_MASK0, 0); 2305141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_MASK1, 0); 2315141Sgblack@eecs.umich.edu 2325141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000); 2335141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TOP_MEM2, 0x0); 2345141Sgblack@eecs.umich.edu 2355141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0); 2365141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0); 2375141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0); 2385141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0); 2395141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0); 2405135Sgblack@eecs.umich.edu 2415135Sgblack@eecs.umich.edu // Invalidate the caches (this should already be done for us) 2425135Sgblack@eecs.umich.edu 2435135Sgblack@eecs.umich.edu // TODO Turn on the APIC. This should be handled elsewhere but it isn't 2445135Sgblack@eecs.umich.edu // currently being handled at all. 2455135Sgblack@eecs.umich.edu 2465141Sgblack@eecs.umich.edu // TODO Set the SMRAM base address (SMBASE) to 0x00030000 2475141Sgblack@eecs.umich.edu 2485141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_VM_CR, 0); 2495141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IGNNE, 0); 2505141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SMM_CTL, 0); 2515141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0); 2525135Sgblack@eecs.umich.edu} 2535135Sgblack@eecs.umich.edu 2545135Sgblack@eecs.umich.edu#endif 2555135Sgblack@eecs.umich.edu 2565135Sgblack@eecs.umich.eduvoid startupCPU(ThreadContext *tc, int cpuId) 2575135Sgblack@eecs.umich.edu{ 2585135Sgblack@eecs.umich.edu if (cpuId == 0) { 2595135Sgblack@eecs.umich.edu // This is the boot strap processor (BSP). Initialize it to look like 2605135Sgblack@eecs.umich.edu // the boot loader has just turned control over to the 64 bit OS. 2615135Sgblack@eecs.umich.edu 2625135Sgblack@eecs.umich.edu // Enable paging, turn on long mode, etc. 2635135Sgblack@eecs.umich.edu 2645135Sgblack@eecs.umich.edu tc->activate(0); 2655135Sgblack@eecs.umich.edu } else { 2665135Sgblack@eecs.umich.edu // This is an application processor (AP). It should be initialized to 2675135Sgblack@eecs.umich.edu // look like only the BIOS POST has run on it and put then put it into 2685135Sgblack@eecs.umich.edu // a halted state. 2695135Sgblack@eecs.umich.edu } 2705135Sgblack@eecs.umich.edu} 2715135Sgblack@eecs.umich.edu 2725086Sgblack@eecs.umich.edu} //namespace X86_ISA 273