utility.cc revision 5135
17506Stjones1@inf.ed.ac.uk/* 27506Stjones1@inf.ed.ac.uk * Copyright (c) 2007 The Hewlett-Packard Development Company 37506Stjones1@inf.ed.ac.uk * All rights reserved. 47506Stjones1@inf.ed.ac.uk * 57506Stjones1@inf.ed.ac.uk * Redistribution and use of this software in source and binary forms, 67506Stjones1@inf.ed.ac.uk * with or without modification, are permitted provided that the 77506Stjones1@inf.ed.ac.uk * following conditions are met: 87506Stjones1@inf.ed.ac.uk * 97506Stjones1@inf.ed.ac.uk * The software must be used only for Non-Commercial Use which means any 107506Stjones1@inf.ed.ac.uk * use which is NOT directed to receiving any direct monetary 117506Stjones1@inf.ed.ac.uk * compensation for, or commercial advantage from such use. Illustrative 127506Stjones1@inf.ed.ac.uk * examples of non-commercial use are academic research, personal study, 137506Stjones1@inf.ed.ac.uk * teaching, education and corporate research & development. 147506Stjones1@inf.ed.ac.uk * Illustrative examples of commercial use are distributing products for 157506Stjones1@inf.ed.ac.uk * commercial advantage and providing services using the software for 167506Stjones1@inf.ed.ac.uk * commercial advantage. 177506Stjones1@inf.ed.ac.uk * 187506Stjones1@inf.ed.ac.uk * If you wish to use this software or functionality therein that may be 197506Stjones1@inf.ed.ac.uk * covered by patents for commercial use, please contact: 207506Stjones1@inf.ed.ac.uk * Director of Intellectual Property Licensing 217506Stjones1@inf.ed.ac.uk * Office of Strategy and Technology 227506Stjones1@inf.ed.ac.uk * Hewlett-Packard Company 237506Stjones1@inf.ed.ac.uk * 1501 Page Mill Road 247506Stjones1@inf.ed.ac.uk * Palo Alto, California 94304 257506Stjones1@inf.ed.ac.uk * 267506Stjones1@inf.ed.ac.uk * Redistributions of source code must retain the above copyright notice, 277506Stjones1@inf.ed.ac.uk * this list of conditions and the following disclaimer. Redistributions 287506Stjones1@inf.ed.ac.uk * in binary form must reproduce the above copyright notice, this list of 297506Stjones1@inf.ed.ac.uk * conditions and the following disclaimer in the documentation and/or 307506Stjones1@inf.ed.ac.uk * other materials provided with the distribution. Neither the name of 317506Stjones1@inf.ed.ac.uk * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 327506Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from 337506Stjones1@inf.ed.ac.uk * this software without specific prior written permission. No right of 347506Stjones1@inf.ed.ac.uk * sublicense is granted herewith. Derivatives of the software and 357506Stjones1@inf.ed.ac.uk * output created using the software may be prepared, but only for 367698SAli.Saidi@ARM.com * Non-Commercial Uses. Derivatives of the software may be shared with 377506Stjones1@inf.ed.ac.uk * others provided: (i) the others agree to abide by the list of 387506Stjones1@inf.ed.ac.uk * conditions herein which includes the Non-Commercial Use restrictions; 397506Stjones1@inf.ed.ac.uk * and (ii) such Derivatives of the software include the above copyright 407506Stjones1@inf.ed.ac.uk * notice to acknowledge the contribution from this software where 417506Stjones1@inf.ed.ac.uk * applicable, this list of conditions and the disclaimer below. 427506Stjones1@inf.ed.ac.uk * 437506Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 447506Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 457506Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 467506Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 477506Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 487506Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 497506Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 507506Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 519920Syasuko.eckert@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 529920Syasuko.eckert@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 539920Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 547506Stjones1@inf.ed.ac.uk * 557506Stjones1@inf.ed.ac.uk * Authors: Gabe Black 567506Stjones1@inf.ed.ac.uk */ 577506Stjones1@inf.ed.ac.uk 587720Sgblack@eecs.umich.edu#include "arch/x86/intregs.hh" 597506Stjones1@inf.ed.ac.uk#include "arch/x86/miscregs.hh" 607506Stjones1@inf.ed.ac.uk#include "arch/x86/segmentregs.hh" 618787Sgblack@eecs.umich.edu#include "arch/x86/utility.hh" 628787Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 638787Sgblack@eecs.umich.edu 648787Sgblack@eecs.umich.edunamespace X86ISA { 658787Sgblack@eecs.umich.edu 668787Sgblack@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int number, bool fp) { 678787Sgblack@eecs.umich.edu#if FULL_SYSTEM 687693SAli.Saidi@ARM.com panic("getArgument() not implemented for x86!\n"); 697693SAli.Saidi@ARM.com#else 707693SAli.Saidi@ARM.com panic("getArgument() only implemented for FULL_SYSTEM\n"); 717693SAli.Saidi@ARM.com M5_DUMMY_RETURN 727693SAli.Saidi@ARM.com#endif 737693SAli.Saidi@ARM.com} 748791Sgblack@eecs.umich.edu 758791Sgblack@eecs.umich.edu# if FULL_SYSTEM 768791Sgblack@eecs.umich.eduvoid initCPU(ThreadContext *tc, int cpuId) 778791Sgblack@eecs.umich.edu{ 788791Sgblack@eecs.umich.edu // TODO Figure out what the attribute registers should be set to. How this 798791Sgblack@eecs.umich.edu // information is stored isn't specified, but it's values are in table 807693SAli.Saidi@ARM.com // 14.2. 817811Ssteve.reinhardt@amd.com 82 // The otherwise unmodified integer registers should be set to 0. 83 for (int index = 0; index < NUM_INTREGS; index++) { 84 tc->setIntReg(index, 0); 85 } 86 87 // These next two loops zero internal microcode and implicit registers. 88 // They aren't specified by the ISA but are used internally by M5's 89 // implementation. 90 for (int index = 0; index < NumMicroIntRegs; index++) { 91 tc->setIntReg(INTREG_MICRO(index), 0); 92 } 93 94 for (int index = 0; index < NumImplicitIntRegs; index++) { 95 tc->setIntReg(INTREG_IMPLICIT(index), 0); 96 } 97 98 // Set integer register EAX to 0 to indicate that the optional BIST 99 // passed. No BIST actually runs, but software may still check this 100 // register for errors. 101 tc->setIntReg(INTREG_RAX, 0); 102 103 //The following values are dictated by the architecture for after a RESET# 104 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010); 105 tc->setMiscReg(MISCREG_CR2, 0); 106 tc->setMiscReg(MISCREG_CR3, 0); 107 tc->setMiscReg(MISCREG_CR4, 0); 108 tc->setMiscReg(MISCREG_CR8, 0); 109 110 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002); 111 112 tc->setMiscReg(MISCREG_EFER, 0); 113 114 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) { 115 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0); 116 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0); 117 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff); 118 tc->setMiscReg(MISCREG_SEG_ATTR(seg), 0); 119 } 120 121 tc->setMiscReg(MISCREG_CS, 0xf000); 122 tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000); 123 // This has the base value pre-added. 124 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff); 125 tc->setMiscReg(MISCREG_CS_ATTR, 0); 126 127 tc->setPC(0x000000000000fff0 + 128 tc->readMiscReg(MISCREG_CS_BASE)); 129 tc->setNextPC(tc->readPC() + sizeof(MachInst)); 130 131 tc->setMiscReg(MISCREG_GDTR_BASE, 0); 132 tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff); 133 134 tc->setMiscReg(MISCREG_IDTR_BASE, 0); 135 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); 136 137 tc->setMiscReg(MISCREG_LDTR, 0); 138 tc->setMiscReg(MISCREG_LDTR_BASE, 0); 139 tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff); 140 tc->setMiscReg(MISCREG_LDTR_ATTR, 0); 141 142 tc->setMiscReg(MISCREG_TR, 0); 143 tc->setMiscReg(MISCREG_TR_BASE, 0); 144 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff); 145 tc->setMiscReg(MISCREG_TR_ATTR, 0); 146 147 // This value should be the family/model/stepping of the processor. 148 // (page 418). It should be consistent with the value from CPUID, but the 149 // actual value probably doesn't matter much. 150 tc->setIntReg(INTREG_RDX, 0); 151 152 // TODO initialize x87, 64 bit, and 128 bit media state 153 154 // TODO Set up MTRRs (page 512) 155 156 // TODO Set up machine check registers (page 515) 157 158 tc->setMiscReg(MISCREG_DR0, 0); 159 tc->setMiscReg(MISCREG_DR1, 0); 160 tc->setMiscReg(MISCREG_DR2, 0); 161 tc->setMiscReg(MISCREG_DR3, 0); 162 163 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0); 164 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400); 165 166 // TODO Set time stamp counter to 0 167 168 // TODO Set up performance monitoring registers (page 517) 169 170 // TODO Set up the rest of the MSRs (page 507) 171 172 // Invalidate the caches (this should already be done for us) 173 174 // TODO Turn on the APIC. This should be handled elsewhere but it isn't 175 // currently being handled at all. 176 177 // Set the SMRAM base address (SMBASE) to 0x00030000 178} 179 180#endif 181 182void startupCPU(ThreadContext *tc, int cpuId) 183{ 184 if (cpuId == 0) { 185 // This is the boot strap processor (BSP). Initialize it to look like 186 // the boot loader has just turned control over to the 64 bit OS. 187 188 // Enable paging, turn on long mode, etc. 189 190 tc->activate(0); 191 } else { 192 // This is an application processor (AP). It should be initialized to 193 // look like only the BIOS POST has run on it and put then put it into 194 // a halted state. 195 } 196} 197 198} //namespace X86_ISA 199