utility.cc revision 11709
12810Srdreslin@umich.edu/* 212500Snikos.nikoleris@arm.com * Copyright (c) 2007 The Hewlett-Packard Development Company 311051Sandreas.hansson@arm.com * Copyright (c) 2011 Advanced Micro Devices, Inc. 411051Sandreas.hansson@arm.com * All rights reserved. 511051Sandreas.hansson@arm.com * 611051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 711051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 811051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 911051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 1011051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1111051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1211051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1311051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1411051Sandreas.hansson@arm.com * 1511051Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 162810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 172810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 182810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 192810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 212810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 222810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 232810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 242810Srdreslin@umich.edu * this software without specific prior written permission. 252810Srdreslin@umich.edu * 262810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 272810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 282810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 292810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 302810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 312810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 322810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 332810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 342810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 352810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 362810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 372810Srdreslin@umich.edu * 382810Srdreslin@umich.edu * Authors: Gabe Black 392810Srdreslin@umich.edu */ 402810Srdreslin@umich.edu 412810Srdreslin@umich.edu#include "arch/x86/interrupts.hh" 4211051Sandreas.hansson@arm.com#include "arch/x86/registers.hh" 4311051Sandreas.hansson@arm.com#include "arch/x86/tlb.hh" 442810Srdreslin@umich.edu#include "arch/x86/utility.hh" 4511051Sandreas.hansson@arm.com#include "arch/x86/x86_traits.hh" 4611051Sandreas.hansson@arm.com#include "cpu/base.hh" 4712349Snikos.nikoleris@arm.com#include "fputils/fp80.h" 482810Srdreslin@umich.edu#include "sim/system.hh" 492810Srdreslin@umich.edu 502810Srdreslin@umich.edunamespace X86ISA { 512810Srdreslin@umich.edu 5211051Sandreas.hansson@arm.comuint64_t 532810Srdreslin@umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 542810Srdreslin@umich.edu{ 5511051Sandreas.hansson@arm.com if (fp) { 562810Srdreslin@umich.edu panic("getArgument(): Floating point arguments not implemented\n"); 5712724Snikos.nikoleris@arm.com } else if (size != 8) { 5812724Snikos.nikoleris@arm.com panic("getArgument(): Can only handle 64-bit arguments.\n"); 5912724Snikos.nikoleris@arm.com } 6012334Sgabeblack@google.com 6112724Snikos.nikoleris@arm.com // The first 6 integer arguments are passed in registers, the rest 6211051Sandreas.hansson@arm.com // are passed on the stack. 6311051Sandreas.hansson@arm.com const int int_reg_map[] = { 6411051Sandreas.hansson@arm.com INTREG_RDI, INTREG_RSI, INTREG_RDX, 6511288Ssteve.reinhardt@amd.com INTREG_RCX, INTREG_R8, INTREG_R9 6612724Snikos.nikoleris@arm.com }; 6713223Sodanrc@yahoo.com.br if (number < sizeof(int_reg_map) / sizeof(*int_reg_map)) { 6811051Sandreas.hansson@arm.com return tc->readIntReg(int_reg_map[number]); 6912724Snikos.nikoleris@arm.com } else { 7012724Snikos.nikoleris@arm.com panic("getArgument(): Don't know how to handle stack arguments.\n"); 7112724Snikos.nikoleris@arm.com } 7212724Snikos.nikoleris@arm.com} 7311051Sandreas.hansson@arm.com 7411053Sandreas.hansson@arm.comvoid initCPU(ThreadContext *tc, int cpuId) 7511053Sandreas.hansson@arm.com{ 7612724Snikos.nikoleris@arm.com // This function is essentially performing a reset. The actual INIT 7711051Sandreas.hansson@arm.com // interrupt does a subset of this, so we'll piggyback on some of its 7811051Sandreas.hansson@arm.com // functionality. 7911051Sandreas.hansson@arm.com InitInterrupt init(0); 8011051Sandreas.hansson@arm.com init.invoke(tc); 8111601Sandreas.hansson@arm.com 8211601Sandreas.hansson@arm.com PCState pc = tc->pcState(); 8311051Sandreas.hansson@arm.com pc.upc(0); 8412724Snikos.nikoleris@arm.com pc.nupc(1); 8511051Sandreas.hansson@arm.com tc->pcState(pc); 8612724Snikos.nikoleris@arm.com 8711600Sandreas.hansson@arm.com // These next two loops zero internal microcode and implicit registers. 8811600Sandreas.hansson@arm.com // They aren't specified by the ISA but are used internally by M5's 8911051Sandreas.hansson@arm.com // implementation. 9011051Sandreas.hansson@arm.com for (int index = 0; index < NumMicroIntRegs; index++) { 9111051Sandreas.hansson@arm.com tc->setIntReg(INTREG_MICRO(index), 0); 9211284Sandreas.hansson@arm.com } 9311051Sandreas.hansson@arm.com 9411051Sandreas.hansson@arm.com for (int index = 0; index < NumImplicitIntRegs; index++) { 9511051Sandreas.hansson@arm.com tc->setIntReg(INTREG_IMPLICIT(index), 0); 9611602Sandreas.hansson@arm.com } 9711051Sandreas.hansson@arm.com 9811051Sandreas.hansson@arm.com // Set integer register EAX to 0 to indicate that the optional BIST 9911284Sandreas.hansson@arm.com // passed. No BIST actually runs, but software may still check this 10011051Sandreas.hansson@arm.com // register for errors. 10111284Sandreas.hansson@arm.com tc->setIntReg(INTREG_RAX, 0); 10211602Sandreas.hansson@arm.com 10311051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL); 10411051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_CR8, 0); 10511284Sandreas.hansson@arm.com 10611051Sandreas.hansson@arm.com // TODO initialize x87, 64 bit, and 128 bit media state 10711284Sandreas.hansson@arm.com 10811284Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRRCAP, 0x0508); 10911284Sandreas.hansson@arm.com for (int i = 0; i < 8; i++) { 11011051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0); 11111051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0); 11211051Sandreas.hansson@arm.com } 11311284Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0); 11411284Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0); 11511284Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0); 11611284Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0); 11711051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0); 11811051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0); 11911051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0); 12011284Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0); 12111284Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0); 12211284Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0); 12311197Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0); 12411601Sandreas.hansson@arm.com 12511601Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_DEF_TYPE, 0); 12611601Sandreas.hansson@arm.com 12711601Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MCG_CAP, 0x104); 12811601Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MCG_STATUS, 0); 12911601Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MCG_CTL, 0); 13011601Sandreas.hansson@arm.com 13111601Sandreas.hansson@arm.com for (int i = 0; i < 5; i++) { 13211197Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MC_CTL(i), 0); 13311601Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MC_STATUS(i), 0); 13411601Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MC_ADDR(i), 0); 13511601Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_MC_MISC(i), 0); 13611601Sandreas.hansson@arm.com } 13711601Sandreas.hansson@arm.com 13811601Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_TSC, 0); 13911601Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_TSC_AUX, 0); 14011051Sandreas.hansson@arm.com 14111051Sandreas.hansson@arm.com for (int i = 0; i < 4; i++) { 14211051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0); 14311051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0); 14411051Sandreas.hansson@arm.com } 14511284Sandreas.hansson@arm.com 14611284Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_STAR, 0); 14711051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_LSTAR, 0); 14811051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_CSTAR, 0); 14911051Sandreas.hansson@arm.com 15011051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_SF_MASK, 0); 15111284Sandreas.hansson@arm.com 15211051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0); 15311051Sandreas.hansson@arm.com 15411051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_SYSENTER_CS, 0); 15511051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_SYSENTER_ESP, 0); 15611051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_SYSENTER_EIP, 0); 15711051Sandreas.hansson@arm.com 15811051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL); 15911051Sandreas.hansson@arm.com 16011051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_SYSCFG, 0x20601); 16111051Sandreas.hansson@arm.com 16211051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_IORR_BASE0, 0); 16311051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_IORR_BASE1, 0); 16411051Sandreas.hansson@arm.com 16511051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_IORR_MASK0, 0); 16611051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_IORR_MASK1, 0); 16711051Sandreas.hansson@arm.com 16811051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000); 16912724Snikos.nikoleris@arm.com tc->setMiscReg(MISCREG_TOP_MEM2, 0x0); 17012724Snikos.nikoleris@arm.com 17112724Snikos.nikoleris@arm.com tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0); 17212724Snikos.nikoleris@arm.com tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0); 17312724Snikos.nikoleris@arm.com tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0); 17412724Snikos.nikoleris@arm.com tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0); 17512724Snikos.nikoleris@arm.com tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0); 17611051Sandreas.hansson@arm.com 17711051Sandreas.hansson@arm.com // Invalidate the caches (this should already be done for us) 17811051Sandreas.hansson@arm.com 17911051Sandreas.hansson@arm.com LocalApicBase lApicBase = 0; 18012723Snikos.nikoleris@arm.com lApicBase.base = 0xFEE00000 >> 12; 18111051Sandreas.hansson@arm.com lApicBase.enable = 1; 18211051Sandreas.hansson@arm.com lApicBase.bsp = (cpuId == 0); 18311484Snikos.nikoleris@arm.com tc->setMiscReg(MISCREG_APIC_BASE, lApicBase); 18411051Sandreas.hansson@arm.com 18511051Sandreas.hansson@arm.com Interrupts * interrupts = dynamic_cast<Interrupts *>( 18611051Sandreas.hansson@arm.com tc->getCpuPtr()->getInterruptController(0)); 18711051Sandreas.hansson@arm.com assert(interrupts); 18811051Sandreas.hansson@arm.com 18912724Snikos.nikoleris@arm.com interrupts->setRegNoEffect(APIC_ID, cpuId << 24); 19011601Sandreas.hansson@arm.com 19111601Sandreas.hansson@arm.com interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14); 19211601Sandreas.hansson@arm.com 19311051Sandreas.hansson@arm.com // TODO Set the SMRAM base address (SMBASE) to 0x00030000 19411051Sandreas.hansson@arm.com 19511051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_VM_CR, 0); 19611051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_IGNNE, 0); 19711051Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_SMM_CTL, 0); 19812345Snikos.nikoleris@arm.com tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0); 19912345Snikos.nikoleris@arm.com} 20012345Snikos.nikoleris@arm.com 20112345Snikos.nikoleris@arm.comvoid startupCPU(ThreadContext *tc, int cpuId) 20211051Sandreas.hansson@arm.com{ 20311051Sandreas.hansson@arm.com if (cpuId == 0 || !FullSystem) { 20411051Sandreas.hansson@arm.com tc->activate(); 20511051Sandreas.hansson@arm.com } else { 20611051Sandreas.hansson@arm.com // This is an application processor (AP). It should be initialized to 20711051Sandreas.hansson@arm.com // look like only the BIOS POST has run on it and put then put it into 20811051Sandreas.hansson@arm.com // a halted state. 20911199Sandreas.hansson@arm.com tc->suspend(); 21011199Sandreas.hansson@arm.com } 21111199Sandreas.hansson@arm.com} 21211199Sandreas.hansson@arm.com 21311199Sandreas.hansson@arm.comvoid 21411051Sandreas.hansson@arm.comcopyMiscRegs(ThreadContext *src, ThreadContext *dest) 21512345Snikos.nikoleris@arm.com{ 21612345Snikos.nikoleris@arm.com // This function assumes no side effects other than TLB invalidation 21711051Sandreas.hansson@arm.com // need to be considered while copying state. That will likely not be 21811051Sandreas.hansson@arm.com // true in the future. 21911051Sandreas.hansson@arm.com for (int i = 0; i < NUM_MISCREGS; ++i) { 22011051Sandreas.hansson@arm.com if (!isValidMiscReg(i)) 22111051Sandreas.hansson@arm.com continue; 22211051Sandreas.hansson@arm.com 22311051Sandreas.hansson@arm.com dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 22411051Sandreas.hansson@arm.com } 22511051Sandreas.hansson@arm.com 22611051Sandreas.hansson@arm.com // The TSC has to be updated with side-effects if the CPUs in a 22711051Sandreas.hansson@arm.com // CPU switch have different frequencies. 22811051Sandreas.hansson@arm.com dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC)); 22911051Sandreas.hansson@arm.com 23011051Sandreas.hansson@arm.com dest->getITBPtr()->flushAll(); 23111051Sandreas.hansson@arm.com dest->getDTBPtr()->flushAll(); 23211051Sandreas.hansson@arm.com} 23311051Sandreas.hansson@arm.com 23411130Sali.jafri@arm.comvoid 23511130Sali.jafri@arm.comcopyRegs(ThreadContext *src, ThreadContext *dest) 23611130Sali.jafri@arm.com{ 23711130Sali.jafri@arm.com //copy int regs 23811130Sali.jafri@arm.com for (int i = 0; i < NumIntRegs; ++i) 23911130Sali.jafri@arm.com dest->setIntRegFlat(i, src->readIntRegFlat(i)); 24011130Sali.jafri@arm.com //copy float regs 24111130Sali.jafri@arm.com for (int i = 0; i < NumFloatRegs; ++i) 24211130Sali.jafri@arm.com dest->setFloatRegBitsFlat(i, src->readFloatRegBitsFlat(i)); 24312345Snikos.nikoleris@arm.com //copy condition-code regs 24412345Snikos.nikoleris@arm.com for (int i = 0; i < NumCCRegs; ++i) 24511130Sali.jafri@arm.com dest->setCCRegFlat(i, src->readCCRegFlat(i)); 24611130Sali.jafri@arm.com copyMiscRegs(src, dest); 24711130Sali.jafri@arm.com dest->pcState(src->pcState()); 24811130Sali.jafri@arm.com} 24911130Sali.jafri@arm.com 25011130Sali.jafri@arm.comvoid 25112724Snikos.nikoleris@arm.comskipFunction(ThreadContext *tc) 25211130Sali.jafri@arm.com{ 25311130Sali.jafri@arm.com panic("Not implemented for x86\n"); 25411130Sali.jafri@arm.com} 25511130Sali.jafri@arm.com 25611130Sali.jafri@arm.comuint64_t 25711130Sali.jafri@arm.comgetRFlags(ThreadContext *tc) 25812724Snikos.nikoleris@arm.com{ 25911130Sali.jafri@arm.com const uint64_t ncc_flags(tc->readMiscRegNoEffect(MISCREG_RFLAGS)); 26011130Sali.jafri@arm.com const uint64_t cc_flags(tc->readCCReg(X86ISA::CCREG_ZAPS)); 26111130Sali.jafri@arm.com const uint64_t cfof_bits(tc->readCCReg(X86ISA::CCREG_CFOF)); 26211130Sali.jafri@arm.com const uint64_t df_bit(tc->readCCReg(X86ISA::CCREG_DF)); 26311130Sali.jafri@arm.com // ecf (PSEUDO(3)) & ezf (PSEUDO(4)) are only visible to 26411130Sali.jafri@arm.com // microcode, so we can safely ignore them. 26511130Sali.jafri@arm.com 26611130Sali.jafri@arm.com // Reconstruct the real rflags state, mask out internal flags, and 26711130Sali.jafri@arm.com // make sure reserved bits have the expected values. 26811051Sandreas.hansson@arm.com return ((ncc_flags | cc_flags | cfof_bits | df_bit) & 0x3F7FD5) 26911051Sandreas.hansson@arm.com | 0x2; 27011051Sandreas.hansson@arm.com} 27111051Sandreas.hansson@arm.com 27211744Snikos.nikoleris@arm.comvoid 27311051Sandreas.hansson@arm.comsetRFlags(ThreadContext *tc, uint64_t val) 27411276Sandreas.hansson@arm.com{ 27511276Sandreas.hansson@arm.com tc->setCCReg(X86ISA::CCREG_ZAPS, val & ccFlagMask); 27611276Sandreas.hansson@arm.com tc->setCCReg(X86ISA::CCREG_CFOF, val & cfofMask); 27711276Sandreas.hansson@arm.com tc->setCCReg(X86ISA::CCREG_DF, val & DFBit); 27811276Sandreas.hansson@arm.com 27911276Sandreas.hansson@arm.com // Internal microcode registers (ECF & EZF) 28011276Sandreas.hansson@arm.com tc->setCCReg(X86ISA::CCREG_ECF, 0); 28111276Sandreas.hansson@arm.com tc->setCCReg(X86ISA::CCREG_EZF, 0); 28211276Sandreas.hansson@arm.com 28311051Sandreas.hansson@arm.com // Update the RFLAGS misc reg with whatever didn't go into the 28411276Sandreas.hansson@arm.com // magic registers. 28511276Sandreas.hansson@arm.com tc->setMiscReg(MISCREG_RFLAGS, val & ~(ccFlagMask | cfofMask | DFBit)); 28611276Sandreas.hansson@arm.com} 28711276Sandreas.hansson@arm.com 28811276Sandreas.hansson@arm.comuint8_t 28911051Sandreas.hansson@arm.comconvX87TagsToXTags(uint16_t ftw) 29011051Sandreas.hansson@arm.com{ 29111051Sandreas.hansson@arm.com uint8_t ftwx(0); 29211051Sandreas.hansson@arm.com for (int i = 0; i < 8; ++i) { 29311051Sandreas.hansson@arm.com // Extract the tag for the current element on the FP stack 29411051Sandreas.hansson@arm.com const unsigned tag((ftw >> (2 * i)) & 0x3); 29511051Sandreas.hansson@arm.com 29611051Sandreas.hansson@arm.com /* 29711051Sandreas.hansson@arm.com * Check the type of the current FP element. Valid values are: 29811051Sandreas.hansson@arm.com * 0 == Valid 29911051Sandreas.hansson@arm.com * 1 == Zero 30012724Snikos.nikoleris@arm.com * 2 == Special (Nan, unsupported, infinity, denormal) 30111051Sandreas.hansson@arm.com * 3 == Empty 30211051Sandreas.hansson@arm.com */ 30311051Sandreas.hansson@arm.com // The xsave version of the tag word only keeps track of 30411051Sandreas.hansson@arm.com // whether the element is empty or not. Set the corresponding 30511051Sandreas.hansson@arm.com // bit in the ftwx if it's not empty, 30611051Sandreas.hansson@arm.com if (tag != 0x3) 30711051Sandreas.hansson@arm.com ftwx |= 1 << i; 30811051Sandreas.hansson@arm.com } 30911051Sandreas.hansson@arm.com 31011051Sandreas.hansson@arm.com return ftwx; 31111051Sandreas.hansson@arm.com} 31211051Sandreas.hansson@arm.com 31311051Sandreas.hansson@arm.comuint16_t 31412630Snikos.nikoleris@arm.comconvX87XTagsToTags(uint8_t ftwx) 31512720Snikos.nikoleris@arm.com{ 31612720Snikos.nikoleris@arm.com uint16_t ftw(0); 31712720Snikos.nikoleris@arm.com for (int i = 0; i < 8; ++i) { 31812720Snikos.nikoleris@arm.com const unsigned xtag(((ftwx >> i) & 0x1)); 31912720Snikos.nikoleris@arm.com 32012720Snikos.nikoleris@arm.com // The xtag for an x87 stack position is 0 for empty stack positions. 32112720Snikos.nikoleris@arm.com if (!xtag) { 32212724Snikos.nikoleris@arm.com // Set the tag word to 3 (empty) for the current element. 32312720Snikos.nikoleris@arm.com ftw |= 0x3 << (2 * i); 32412720Snikos.nikoleris@arm.com } else { 32512720Snikos.nikoleris@arm.com // TODO: We currently assume that non-empty elements are 32612720Snikos.nikoleris@arm.com // valid (0x0), but we should ideally reconstruct the full 32712720Snikos.nikoleris@arm.com // state (valid/zero/special). 32812720Snikos.nikoleris@arm.com } 32912724Snikos.nikoleris@arm.com } 33012724Snikos.nikoleris@arm.com 33112724Snikos.nikoleris@arm.com return ftw; 33212724Snikos.nikoleris@arm.com} 33312724Snikos.nikoleris@arm.com 33412724Snikos.nikoleris@arm.comuint16_t 33512724Snikos.nikoleris@arm.comgenX87Tags(uint16_t ftw, uint8_t top, int8_t spm) 33612724Snikos.nikoleris@arm.com{ 33712724Snikos.nikoleris@arm.com const uint8_t new_top((top + spm + 8) % 8); 33812724Snikos.nikoleris@arm.com 33912724Snikos.nikoleris@arm.com if (spm > 0) { 34012724Snikos.nikoleris@arm.com // Removing elements from the stack. Flag the elements as empty. 34112724Snikos.nikoleris@arm.com for (int i = top; i != new_top; i = (i + 1 + 8) % 8) 34212724Snikos.nikoleris@arm.com ftw |= 0x3 << (2 * i); 34312724Snikos.nikoleris@arm.com } else if (spm < 0) { 34412724Snikos.nikoleris@arm.com // Adding elements to the stack. Flag the new elements as 34512724Snikos.nikoleris@arm.com // valid. We should ideally decode them and "do the right 34612724Snikos.nikoleris@arm.com // thing". 34712724Snikos.nikoleris@arm.com for (int i = new_top; i != top; i = (i + 1 + 8) % 8) 34812724Snikos.nikoleris@arm.com ftw &= ~(0x3 << (2 * i)); 34912724Snikos.nikoleris@arm.com } 35012724Snikos.nikoleris@arm.com 35112724Snikos.nikoleris@arm.com return ftw; 35212724Snikos.nikoleris@arm.com} 35312724Snikos.nikoleris@arm.com 35412720Snikos.nikoleris@arm.comdouble 35512720Snikos.nikoleris@arm.comloadFloat80(const void *_mem) 35612724Snikos.nikoleris@arm.com{ 35712720Snikos.nikoleris@arm.com fp80_t fp80; 35812720Snikos.nikoleris@arm.com memcpy(fp80.bits, _mem, 10); 35912720Snikos.nikoleris@arm.com 36012720Snikos.nikoleris@arm.com return fp80_cvtd(fp80); 36112720Snikos.nikoleris@arm.com} 36212720Snikos.nikoleris@arm.com 36312720Snikos.nikoleris@arm.comvoid 36412720Snikos.nikoleris@arm.comstoreFloat80(void *_mem, double value) 36512720Snikos.nikoleris@arm.com{ 36612720Snikos.nikoleris@arm.com fp80_t fp80 = fp80_cvfd(value); 36712720Snikos.nikoleris@arm.com memcpy(_mem, fp80.bits, 10); 36812720Snikos.nikoleris@arm.com} 36912720Snikos.nikoleris@arm.com 37012720Snikos.nikoleris@arm.com} // namespace X86_ISA 37112720Snikos.nikoleris@arm.com