tlb.hh revision 12455
19617Sandreas.hansson@arm.com/* 29617Sandreas.hansson@arm.com * Copyright (c) 2007 The Hewlett-Packard Development Company 310065Sandreas.hansson@arm.com * All rights reserved. 49617Sandreas.hansson@arm.com * 59617Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 69617Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 79617Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 89617Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 99617Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 109617Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 119617Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 129617Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 139617Sandreas.hansson@arm.com * 149617Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 159617Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 169617Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 179617Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 189617Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 199617Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 209617Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 219617Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 229617Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 239617Sandreas.hansson@arm.com * this software without specific prior written permission. 249617Sandreas.hansson@arm.com * 259617Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 269617Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 279617Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 289617Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 299617Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 309617Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 319617Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 329617Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 339617Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 349617Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 359617Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 369617Sandreas.hansson@arm.com * 379617Sandreas.hansson@arm.com * Authors: Gabe Black 389617Sandreas.hansson@arm.com */ 399617Sandreas.hansson@arm.com 409617Sandreas.hansson@arm.com#ifndef __ARCH_X86_TLB_HH__ 419617Sandreas.hansson@arm.com#define __ARCH_X86_TLB_HH__ 429617Sandreas.hansson@arm.com 439617Sandreas.hansson@arm.com#include <list> 449617Sandreas.hansson@arm.com#include <vector> 459617Sandreas.hansson@arm.com 469617Sandreas.hansson@arm.com#include "arch/generic/tlb.hh" 479617Sandreas.hansson@arm.com#include "arch/x86/pagetable.hh" 489617Sandreas.hansson@arm.com#include "base/trie.hh" 499617Sandreas.hansson@arm.com#include "mem/request.hh" 509617Sandreas.hansson@arm.com#include "params/X86TLB.hh" 5110107Sradhika.jagtap@ARM.com 529617Sandreas.hansson@arm.comclass ThreadContext; 539706Sandreas.hansson@arm.com 549706Sandreas.hansson@arm.comnamespace X86ISA 559706Sandreas.hansson@arm.com{ 569706Sandreas.hansson@arm.com class Walker; 579706Sandreas.hansson@arm.com 589706Sandreas.hansson@arm.com class TLB : public BaseTLB 599706Sandreas.hansson@arm.com { 609706Sandreas.hansson@arm.com protected: 619706Sandreas.hansson@arm.com friend class Walker; 629706Sandreas.hansson@arm.com 639706Sandreas.hansson@arm.com typedef std::list<TlbEntry *> EntryList; 649706Sandreas.hansson@arm.com 6510065Sandreas.hansson@arm.com uint32_t configAddress; 6610065Sandreas.hansson@arm.com 6710065Sandreas.hansson@arm.com public: 6810065Sandreas.hansson@arm.com 6910065Sandreas.hansson@arm.com typedef X86TLBParams Params; 7010065Sandreas.hansson@arm.com TLB(const Params *p); 7110065Sandreas.hansson@arm.com 7210065Sandreas.hansson@arm.com void takeOverFrom(BaseTLB *otlb) override {} 739706Sandreas.hansson@arm.com 749706Sandreas.hansson@arm.com TlbEntry *lookup(Addr va, bool update_lru = true); 759706Sandreas.hansson@arm.com 769706Sandreas.hansson@arm.com void setConfigAddress(uint32_t addr); 779617Sandreas.hansson@arm.com 789617Sandreas.hansson@arm.com protected: 799617Sandreas.hansson@arm.com 809617Sandreas.hansson@arm.com EntryList::iterator lookupIt(Addr va, bool update_lru = true); 819617Sandreas.hansson@arm.com 829617Sandreas.hansson@arm.com Walker * walker; 8310269Sradhika.jagtap@ARM.com 8410269Sradhika.jagtap@ARM.com public: 859617Sandreas.hansson@arm.com Walker *getWalker(); 869617Sandreas.hansson@arm.com 879617Sandreas.hansson@arm.com void flushAll() override; 889617Sandreas.hansson@arm.com 899617Sandreas.hansson@arm.com void flushNonGlobal(); 909617Sandreas.hansson@arm.com 919617Sandreas.hansson@arm.com void demapPage(Addr va, uint64_t asn) override; 929617Sandreas.hansson@arm.com 939617Sandreas.hansson@arm.com protected: 949617Sandreas.hansson@arm.com uint32_t size; 959617Sandreas.hansson@arm.com 9610132Sandreas.hansson@arm.com std::vector<TlbEntry> tlb; 979617Sandreas.hansson@arm.com 989617Sandreas.hansson@arm.com EntryList freeList; 999617Sandreas.hansson@arm.com 1009617Sandreas.hansson@arm.com TlbEntryTrie trie; 1019617Sandreas.hansson@arm.com uint64_t lruSeq; 1029617Sandreas.hansson@arm.com 10310107Sradhika.jagtap@ARM.com // Statistics 1049617Sandreas.hansson@arm.com Stats::Scalar rdAccesses; 1059617Sandreas.hansson@arm.com Stats::Scalar wrAccesses; 1069617Sandreas.hansson@arm.com Stats::Scalar rdMisses; 1079617Sandreas.hansson@arm.com Stats::Scalar wrMisses; 1089617Sandreas.hansson@arm.com 1099617Sandreas.hansson@arm.com Fault translateInt(RequestPtr req, ThreadContext *tc); 1109617Sandreas.hansson@arm.com 1119617Sandreas.hansson@arm.com Fault translate(RequestPtr req, ThreadContext *tc, 1129617Sandreas.hansson@arm.com Translation *translation, Mode mode, 1139617Sandreas.hansson@arm.com bool &delayedResponse, bool timing); 11410107Sradhika.jagtap@ARM.com 1159617Sandreas.hansson@arm.com public: 1169617Sandreas.hansson@arm.com 1179617Sandreas.hansson@arm.com void evictLRU(); 11810107Sradhika.jagtap@ARM.com 11910107Sradhika.jagtap@ARM.com uint64_t 1209617Sandreas.hansson@arm.com nextSeq() 12110107Sradhika.jagtap@ARM.com { 12210107Sradhika.jagtap@ARM.com return ++lruSeq; 12310107Sradhika.jagtap@ARM.com } 12410107Sradhika.jagtap@ARM.com 1259617Sandreas.hansson@arm.com Fault translateAtomic( 1269617Sandreas.hansson@arm.com RequestPtr req, ThreadContext *tc, Mode mode) override; 1279617Sandreas.hansson@arm.com void translateTiming( 1289617Sandreas.hansson@arm.com RequestPtr req, ThreadContext *tc, 1299617Sandreas.hansson@arm.com Translation *translation, Mode mode) override; 1309617Sandreas.hansson@arm.com 1319617Sandreas.hansson@arm.com /** 1329617Sandreas.hansson@arm.com * Do post-translation physical address finalization. 1339617Sandreas.hansson@arm.com * 1349617Sandreas.hansson@arm.com * Some addresses, for example requests going to the APIC, 135 * need post-translation updates. Such physical addresses are 136 * remapped into a "magic" part of the physical address space 137 * by this method. 138 * 139 * @param req Request to updated in-place. 140 * @param tc Thread context that created the request. 141 * @param mode Request type (read/write/execute). 142 * @return A fault on failure, NoFault otherwise. 143 */ 144 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, 145 Mode mode) const override; 146 147 TlbEntry *insert(Addr vpn, const TlbEntry &entry); 148 149 /* 150 * Function to register Stats 151 */ 152 void regStats() override; 153 154 // Checkpointing 155 void serialize(CheckpointOut &cp) const override; 156 void unserialize(CheckpointIn &cp) override; 157 158 /** 159 * Get the table walker master port. This is used for 160 * migrating port connections during a CPU takeOverFrom() 161 * call. For architectures that do not have a table walker, 162 * NULL is returned, hence the use of a pointer rather than a 163 * reference. For X86 this method will always return a valid 164 * port pointer. 165 * 166 * @return A pointer to the walker master port 167 */ 168 BaseMasterPort *getMasterPort() override; 169 }; 170} 171 172#endif // __ARCH_X86_TLB_HH__ 173