tlb.cc revision 9898:2935441b0870
1/* 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#include <cstring> 41 42#include "arch/generic/mmapped_ipr.hh" 43#include "arch/x86/insts/microldstop.hh" 44#include "arch/x86/regs/misc.hh" 45#include "arch/x86/regs/msr.hh" 46#include "arch/x86/faults.hh" 47#include "arch/x86/pagetable.hh" 48#include "arch/x86/pagetable_walker.hh" 49#include "arch/x86/tlb.hh" 50#include "arch/x86/x86_traits.hh" 51#include "base/bitfield.hh" 52#include "base/trace.hh" 53#include "cpu/base.hh" 54#include "cpu/thread_context.hh" 55#include "debug/TLB.hh" 56#include "mem/packet_access.hh" 57#include "mem/page_table.hh" 58#include "mem/request.hh" 59#include "sim/full_system.hh" 60#include "sim/process.hh" 61 62namespace X86ISA { 63 64TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size), 65 lruSeq(0) 66{ 67 if (!size) 68 fatal("TLBs must have a non-zero size.\n"); 69 tlb = new TlbEntry[size]; 70 std::memset(tlb, 0, sizeof(TlbEntry) * size); 71 72 for (int x = 0; x < size; x++) { 73 tlb[x].trieHandle = NULL; 74 freeList.push_back(&tlb[x]); 75 } 76 77 walker = p->walker; 78 walker->setTLB(this); 79} 80 81void 82TLB::evictLRU() 83{ 84 // Find the entry with the lowest (and hence least recently updated) 85 // sequence number. 86 87 unsigned lru = 0; 88 for (unsigned i = 1; i < size; i++) { 89 if (tlb[i].lruSeq < tlb[lru].lruSeq) 90 lru = i; 91 } 92 93 assert(tlb[lru].trieHandle); 94 trie.remove(tlb[lru].trieHandle); 95 tlb[lru].trieHandle = NULL; 96 freeList.push_back(&tlb[lru]); 97} 98 99TlbEntry * 100TLB::insert(Addr vpn, TlbEntry &entry) 101{ 102 // If somebody beat us to it, just use that existing entry. 103 TlbEntry *newEntry = trie.lookup(vpn); 104 if (newEntry) { 105 assert(newEntry->vaddr == vpn); 106 return newEntry; 107 } 108 109 if (freeList.empty()) 110 evictLRU(); 111 112 newEntry = freeList.front(); 113 freeList.pop_front(); 114 115 *newEntry = entry; 116 newEntry->lruSeq = nextSeq(); 117 newEntry->vaddr = vpn; 118 newEntry->trieHandle = 119 trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry); 120 return newEntry; 121} 122 123TlbEntry * 124TLB::lookup(Addr va, bool update_lru) 125{ 126 TlbEntry *entry = trie.lookup(va); 127 if (entry && update_lru) 128 entry->lruSeq = nextSeq(); 129 return entry; 130} 131 132void 133TLB::flushAll() 134{ 135 DPRINTF(TLB, "Invalidating all entries.\n"); 136 for (unsigned i = 0; i < size; i++) { 137 if (tlb[i].trieHandle) { 138 trie.remove(tlb[i].trieHandle); 139 tlb[i].trieHandle = NULL; 140 freeList.push_back(&tlb[i]); 141 } 142 } 143} 144 145void 146TLB::setConfigAddress(uint32_t addr) 147{ 148 configAddress = addr; 149} 150 151void 152TLB::flushNonGlobal() 153{ 154 DPRINTF(TLB, "Invalidating all non global entries.\n"); 155 for (unsigned i = 0; i < size; i++) { 156 if (tlb[i].trieHandle && !tlb[i].global) { 157 trie.remove(tlb[i].trieHandle); 158 tlb[i].trieHandle = NULL; 159 freeList.push_back(&tlb[i]); 160 } 161 } 162} 163 164void 165TLB::demapPage(Addr va, uint64_t asn) 166{ 167 TlbEntry *entry = trie.lookup(va); 168 if (entry) { 169 trie.remove(entry->trieHandle); 170 entry->trieHandle = NULL; 171 freeList.push_back(entry); 172 } 173} 174 175Fault 176TLB::translateInt(RequestPtr req, ThreadContext *tc) 177{ 178 DPRINTF(TLB, "Addresses references internal memory.\n"); 179 Addr vaddr = req->getVaddr(); 180 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 181 if (prefix == IntAddrPrefixCPUID) { 182 panic("CPUID memory space not yet implemented!\n"); 183 } else if (prefix == IntAddrPrefixMSR) { 184 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask; 185 req->setFlags(Request::MMAPPED_IPR); 186 187 MiscRegIndex regNum; 188 if (!msrAddrToIndex(regNum, vaddr)) 189 return new GeneralProtection(0); 190 191 //The index is multiplied by the size of a MiscReg so that 192 //any memory dependence calculations will not see these as 193 //overlapping. 194 req->setPaddr((Addr)regNum * sizeof(MiscReg)); 195 return NoFault; 196 } else if (prefix == IntAddrPrefixIO) { 197 // TODO If CPL > IOPL or in virtual mode, check the I/O permission 198 // bitmap in the TSS. 199 200 Addr IOPort = vaddr & ~IntAddrPrefixMask; 201 // Make sure the address fits in the expected 16 bit IO address 202 // space. 203 assert(!(IOPort & ~0xFFFF)); 204 if (IOPort == 0xCF8 && req->getSize() == 4) { 205 req->setFlags(Request::MMAPPED_IPR); 206 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 207 } else if ((IOPort & ~mask(2)) == 0xCFC) { 208 req->setFlags(Request::UNCACHEABLE); 209 Addr configAddress = 210 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 211 if (bits(configAddress, 31, 31)) { 212 req->setPaddr(PhysAddrPrefixPciConfig | 213 mbits(configAddress, 30, 2) | 214 (IOPort & mask(2))); 215 } else { 216 req->setPaddr(PhysAddrPrefixIO | IOPort); 217 } 218 } else { 219 req->setFlags(Request::UNCACHEABLE); 220 req->setPaddr(PhysAddrPrefixIO | IOPort); 221 } 222 return NoFault; 223 } else { 224 panic("Access to unrecognized internal address space %#x.\n", 225 prefix); 226 } 227} 228 229Fault 230TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 231{ 232 Addr paddr = req->getPaddr(); 233 234 // Check for an access to the local APIC 235 if (FullSystem) { 236 LocalApicBase localApicBase = 237 tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 238 AddrRange apicRange(localApicBase.base * PageBytes, 239 (localApicBase.base + 1) * PageBytes - 1); 240 241 AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF); 242 243 if (apicRange.contains(paddr)) { 244 // The Intel developer's manuals say the below restrictions apply, 245 // but the linux kernel, because of a compiler optimization, breaks 246 // them. 247 /* 248 // Check alignment 249 if (paddr & ((32/8) - 1)) 250 return new GeneralProtection(0); 251 // Check access size 252 if (req->getSize() != (32/8)) 253 return new GeneralProtection(0); 254 */ 255 // Force the access to be uncacheable. 256 req->setFlags(Request::UNCACHEABLE); 257 req->setPaddr(x86LocalAPICAddress(tc->contextId(), 258 paddr - apicRange.start())); 259 } else if (m5opRange.contains(paddr)) { 260 req->setFlags(Request::MMAPPED_IPR); 261 req->setPaddr(GenericISA::iprAddressPseudoInst( 262 (paddr >> 8) & 0xFF, 263 paddr & 0xFF)); 264 } 265 } 266 267 return NoFault; 268} 269 270Fault 271TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, 272 Mode mode, bool &delayedResponse, bool timing) 273{ 274 uint32_t flags = req->getFlags(); 275 int seg = flags & SegmentFlagMask; 276 bool storeCheck = flags & (StoreCheck << FlagShift); 277 278 delayedResponse = false; 279 280 // If this is true, we're dealing with a request to a non-memory address 281 // space. 282 if (seg == SEGMENT_REG_MS) { 283 return translateInt(req, tc); 284 } 285 286 Addr vaddr = req->getVaddr(); 287 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 288 289 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 290 291 // If protected mode has been enabled... 292 if (m5Reg.prot) { 293 DPRINTF(TLB, "In protected mode.\n"); 294 // If we're not in 64-bit mode, do protection/limit checks 295 if (m5Reg.mode != LongMode) { 296 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 297 // Check for a NULL segment selector. 298 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 299 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 300 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 301 return new GeneralProtection(0); 302 bool expandDown = false; 303 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 304 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 305 if (!attr.writable && (mode == Write || storeCheck)) 306 return new GeneralProtection(0); 307 if (!attr.readable && mode == Read) 308 return new GeneralProtection(0); 309 expandDown = attr.expandDown; 310 311 } 312 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 313 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 314 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 315 unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr 316 : (unsigned)m5Reg.defAddr; 317 int size = (1 << logSize) * 8; 318 Addr offset = bits(vaddr - base, size - 1, 0); 319 Addr endOffset = offset + req->getSize() - 1; 320 if (expandDown) { 321 DPRINTF(TLB, "Checking an expand down segment.\n"); 322 warn_once("Expand down segments are untested.\n"); 323 if (offset <= limit || endOffset <= limit) 324 return new GeneralProtection(0); 325 } else { 326 if (offset > limit || endOffset > limit) 327 return new GeneralProtection(0); 328 } 329 } 330 if (m5Reg.submode != SixtyFourBitMode || 331 (flags & (AddrSizeFlagBit << FlagShift))) 332 vaddr &= mask(32); 333 // If paging is enabled, do the translation. 334 if (m5Reg.paging) { 335 DPRINTF(TLB, "Paging enabled.\n"); 336 // The vaddr already has the segment base applied. 337 TlbEntry *entry = lookup(vaddr); 338 if (!entry) { 339 if (FullSystem) { 340 Fault fault = walker->start(tc, translation, req, mode); 341 if (timing || fault != NoFault) { 342 // This gets ignored in atomic mode. 343 delayedResponse = true; 344 return fault; 345 } 346 entry = lookup(vaddr); 347 assert(entry); 348 } else { 349 DPRINTF(TLB, "Handling a TLB miss for " 350 "address %#x at pc %#x.\n", 351 vaddr, tc->instAddr()); 352 353 Process *p = tc->getProcessPtr(); 354 TlbEntry newEntry; 355 bool success = p->pTable->lookup(vaddr, newEntry); 356 if (!success && mode != Execute) { 357 // Check if we just need to grow the stack. 358 if (p->fixupStackFault(vaddr)) { 359 // If we did, lookup the entry for the new page. 360 success = p->pTable->lookup(vaddr, newEntry); 361 } 362 } 363 if (!success) { 364 return new PageFault(vaddr, true, mode, true, false); 365 } else { 366 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 367 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 368 newEntry.pageStart()); 369 entry = insert(alignedVaddr, newEntry); 370 } 371 DPRINTF(TLB, "Miss was serviced.\n"); 372 } 373 } 374 375 DPRINTF(TLB, "Entry found with paddr %#x, " 376 "doing protection checks.\n", entry->paddr); 377 // Do paging protection checks. 378 bool inUser = (m5Reg.cpl == 3 && 379 !(flags & (CPL0FlagBit << FlagShift))); 380 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 381 bool badWrite = (!entry->writable && (inUser || cr0.wp)); 382 if ((inUser && !entry->user) || (mode == Write && badWrite)) { 383 // The page must have been present to get into the TLB in 384 // the first place. We'll assume the reserved bits are 385 // fine even though we're not checking them. 386 return new PageFault(vaddr, true, mode, inUser, false); 387 } 388 if (storeCheck && badWrite) { 389 // This would fault if this were a write, so return a page 390 // fault that reflects that happening. 391 return new PageFault(vaddr, true, Write, inUser, false); 392 } 393 394 Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes)); 395 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 396 req->setPaddr(paddr); 397 if (entry->uncacheable) 398 req->setFlags(Request::UNCACHEABLE); 399 } else { 400 //Use the address which already has segmentation applied. 401 DPRINTF(TLB, "Paging disabled.\n"); 402 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 403 req->setPaddr(vaddr); 404 } 405 } else { 406 // Real mode 407 DPRINTF(TLB, "In real mode.\n"); 408 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 409 req->setPaddr(vaddr); 410 } 411 412 return finalizePhysical(req, tc, mode); 413} 414 415Fault 416TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 417{ 418 bool delayedResponse; 419 return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 420} 421 422void 423TLB::translateTiming(RequestPtr req, ThreadContext *tc, 424 Translation *translation, Mode mode) 425{ 426 bool delayedResponse; 427 assert(translation); 428 Fault fault = 429 TLB::translate(req, tc, translation, mode, delayedResponse, true); 430 if (!delayedResponse) 431 translation->finish(fault, req, tc, mode); 432} 433 434Fault 435TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 436{ 437 panic("Not implemented\n"); 438 return NoFault; 439} 440 441Walker * 442TLB::getWalker() 443{ 444 return walker; 445} 446 447void 448TLB::serialize(std::ostream &os) 449{ 450 // Only store the entries in use. 451 uint32_t _size = size - freeList.size(); 452 SERIALIZE_SCALAR(_size); 453 SERIALIZE_SCALAR(lruSeq); 454 455 uint32_t _count = 0; 456 457 for (uint32_t x = 0; x < size; x++) { 458 if (tlb[x].trieHandle != NULL) { 459 os << "\n[" << csprintf("%s.Entry%d", name(), _count) << "]\n"; 460 tlb[x].serialize(os); 461 _count++; 462 } 463 } 464} 465 466void 467TLB::unserialize(Checkpoint *cp, const std::string §ion) 468{ 469 // Do not allow to restore with a smaller tlb. 470 uint32_t _size; 471 UNSERIALIZE_SCALAR(_size); 472 if (_size > size) { 473 fatal("TLB size less than the one in checkpoint!"); 474 } 475 476 UNSERIALIZE_SCALAR(lruSeq); 477 478 for (uint32_t x = 0; x < _size; x++) { 479 TlbEntry *newEntry = freeList.front(); 480 freeList.pop_front(); 481 482 newEntry->unserialize(cp, csprintf("%s.Entry%d", name(), x)); 483 newEntry->trieHandle = trie.insert(newEntry->vaddr, 484 TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry); 485 } 486} 487 488BaseMasterPort * 489TLB::getMasterPort() 490{ 491 return &walker->getMasterPort("port"); 492} 493 494} // namespace X86ISA 495 496X86ISA::TLB * 497X86TLBParams::create() 498{ 499 return new X86ISA::TLB(this); 500} 501