tlb.cc revision 7775:8e8fa2f28f2e 
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41
42#include "config/full_system.hh"
43
44#include "arch/x86/faults.hh"
45#include "arch/x86/insts/microldstop.hh"
46#include "arch/x86/pagetable.hh"
47#include "arch/x86/regs/misc.hh"
48#include "arch/x86/tlb.hh"
49#include "arch/x86/x86_traits.hh"
50#include "base/bitfield.hh"
51#include "base/trace.hh"
52#include "config/full_system.hh"
53#include "cpu/thread_context.hh"
54#include "cpu/base.hh"
55#include "mem/packet_access.hh"
56#include "mem/request.hh"
57
58#if FULL_SYSTEM
59#include "arch/x86/pagetable_walker.hh"
60#else
61#include "mem/page_table.hh"
62#include "sim/process.hh"
63#endif
64
65namespace X86ISA {
66
67TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
68{
69    tlb = new TlbEntry[size];
70    std::memset(tlb, 0, sizeof(TlbEntry) * size);
71
72    for (int x = 0; x < size; x++)
73        freeList.push_back(&tlb[x]);
74
75#if FULL_SYSTEM
76    walker = p->walker;
77    walker->setTLB(this);
78#endif
79}
80
81TlbEntry *
82TLB::insert(Addr vpn, TlbEntry &entry)
83{
84    //TODO Deal with conflicting entries
85
86    TlbEntry *newEntry = NULL;
87    if (!freeList.empty()) {
88        newEntry = freeList.front();
89        freeList.pop_front();
90    } else {
91        newEntry = entryList.back();
92        entryList.pop_back();
93    }
94    *newEntry = entry;
95    newEntry->vaddr = vpn;
96    entryList.push_front(newEntry);
97    return newEntry;
98}
99
100TLB::EntryList::iterator
101TLB::lookupIt(Addr va, bool update_lru)
102{
103    //TODO make this smarter at some point
104    EntryList::iterator entry;
105    for (entry = entryList.begin(); entry != entryList.end(); entry++) {
106        if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
107            DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
108                    "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
109            if (update_lru) {
110                entryList.push_front(*entry);
111                entryList.erase(entry);
112                entry = entryList.begin();
113            }
114            break;
115        }
116    }
117    return entry;
118}
119
120TlbEntry *
121TLB::lookup(Addr va, bool update_lru)
122{
123    EntryList::iterator entry = lookupIt(va, update_lru);
124    if (entry == entryList.end())
125        return NULL;
126    else
127        return *entry;
128}
129
130void
131TLB::invalidateAll()
132{
133    DPRINTF(TLB, "Invalidating all entries.\n");
134    while (!entryList.empty()) {
135        TlbEntry *entry = entryList.front();
136        entryList.pop_front();
137        freeList.push_back(entry);
138    }
139}
140
141void
142TLB::setConfigAddress(uint32_t addr)
143{
144    configAddress = addr;
145}
146
147void
148TLB::invalidateNonGlobal()
149{
150    DPRINTF(TLB, "Invalidating all non global entries.\n");
151    EntryList::iterator entryIt;
152    for (entryIt = entryList.begin(); entryIt != entryList.end();) {
153        if (!(*entryIt)->global) {
154            freeList.push_back(*entryIt);
155            entryList.erase(entryIt++);
156        } else {
157            entryIt++;
158        }
159    }
160}
161
162void
163TLB::demapPage(Addr va, uint64_t asn)
164{
165    EntryList::iterator entry = lookupIt(va, false);
166    if (entry != entryList.end()) {
167        freeList.push_back(*entry);
168        entryList.erase(entry);
169    }
170}
171
172Fault
173TLB::translateInt(RequestPtr req, ThreadContext *tc)
174{
175    DPRINTF(TLB, "Addresses references internal memory.\n");
176    Addr vaddr = req->getVaddr();
177    Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
178    if (prefix == IntAddrPrefixCPUID) {
179        panic("CPUID memory space not yet implemented!\n");
180    } else if (prefix == IntAddrPrefixMSR) {
181        vaddr = vaddr >> 3;
182        req->setFlags(Request::MMAPED_IPR);
183        Addr regNum = 0;
184        switch (vaddr & ~IntAddrPrefixMask) {
185          case 0x10:
186            regNum = MISCREG_TSC;
187            break;
188          case 0x1B:
189            regNum = MISCREG_APIC_BASE;
190            break;
191          case 0xFE:
192            regNum = MISCREG_MTRRCAP;
193            break;
194          case 0x174:
195            regNum = MISCREG_SYSENTER_CS;
196            break;
197          case 0x175:
198            regNum = MISCREG_SYSENTER_ESP;
199            break;
200          case 0x176:
201            regNum = MISCREG_SYSENTER_EIP;
202            break;
203          case 0x179:
204            regNum = MISCREG_MCG_CAP;
205            break;
206          case 0x17A:
207            regNum = MISCREG_MCG_STATUS;
208            break;
209          case 0x17B:
210            regNum = MISCREG_MCG_CTL;
211            break;
212          case 0x1D9:
213            regNum = MISCREG_DEBUG_CTL_MSR;
214            break;
215          case 0x1DB:
216            regNum = MISCREG_LAST_BRANCH_FROM_IP;
217            break;
218          case 0x1DC:
219            regNum = MISCREG_LAST_BRANCH_TO_IP;
220            break;
221          case 0x1DD:
222            regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
223            break;
224          case 0x1DE:
225            regNum = MISCREG_LAST_EXCEPTION_TO_IP;
226            break;
227          case 0x200:
228            regNum = MISCREG_MTRR_PHYS_BASE_0;
229            break;
230          case 0x201:
231            regNum = MISCREG_MTRR_PHYS_MASK_0;
232            break;
233          case 0x202:
234            regNum = MISCREG_MTRR_PHYS_BASE_1;
235            break;
236          case 0x203:
237            regNum = MISCREG_MTRR_PHYS_MASK_1;
238            break;
239          case 0x204:
240            regNum = MISCREG_MTRR_PHYS_BASE_2;
241            break;
242          case 0x205:
243            regNum = MISCREG_MTRR_PHYS_MASK_2;
244            break;
245          case 0x206:
246            regNum = MISCREG_MTRR_PHYS_BASE_3;
247            break;
248          case 0x207:
249            regNum = MISCREG_MTRR_PHYS_MASK_3;
250            break;
251          case 0x208:
252            regNum = MISCREG_MTRR_PHYS_BASE_4;
253            break;
254          case 0x209:
255            regNum = MISCREG_MTRR_PHYS_MASK_4;
256            break;
257          case 0x20A:
258            regNum = MISCREG_MTRR_PHYS_BASE_5;
259            break;
260          case 0x20B:
261            regNum = MISCREG_MTRR_PHYS_MASK_5;
262            break;
263          case 0x20C:
264            regNum = MISCREG_MTRR_PHYS_BASE_6;
265            break;
266          case 0x20D:
267            regNum = MISCREG_MTRR_PHYS_MASK_6;
268            break;
269          case 0x20E:
270            regNum = MISCREG_MTRR_PHYS_BASE_7;
271            break;
272          case 0x20F:
273            regNum = MISCREG_MTRR_PHYS_MASK_7;
274            break;
275          case 0x250:
276            regNum = MISCREG_MTRR_FIX_64K_00000;
277            break;
278          case 0x258:
279            regNum = MISCREG_MTRR_FIX_16K_80000;
280            break;
281          case 0x259:
282            regNum = MISCREG_MTRR_FIX_16K_A0000;
283            break;
284          case 0x268:
285            regNum = MISCREG_MTRR_FIX_4K_C0000;
286            break;
287          case 0x269:
288            regNum = MISCREG_MTRR_FIX_4K_C8000;
289            break;
290          case 0x26A:
291            regNum = MISCREG_MTRR_FIX_4K_D0000;
292            break;
293          case 0x26B:
294            regNum = MISCREG_MTRR_FIX_4K_D8000;
295            break;
296          case 0x26C:
297            regNum = MISCREG_MTRR_FIX_4K_E0000;
298            break;
299          case 0x26D:
300            regNum = MISCREG_MTRR_FIX_4K_E8000;
301            break;
302          case 0x26E:
303            regNum = MISCREG_MTRR_FIX_4K_F0000;
304            break;
305          case 0x26F:
306            regNum = MISCREG_MTRR_FIX_4K_F8000;
307            break;
308          case 0x277:
309            regNum = MISCREG_PAT;
310            break;
311          case 0x2FF:
312            regNum = MISCREG_DEF_TYPE;
313            break;
314          case 0x400:
315            regNum = MISCREG_MC0_CTL;
316            break;
317          case 0x404:
318            regNum = MISCREG_MC1_CTL;
319            break;
320          case 0x408:
321            regNum = MISCREG_MC2_CTL;
322            break;
323          case 0x40C:
324            regNum = MISCREG_MC3_CTL;
325            break;
326          case 0x410:
327            regNum = MISCREG_MC4_CTL;
328            break;
329          case 0x414:
330            regNum = MISCREG_MC5_CTL;
331            break;
332          case 0x418:
333            regNum = MISCREG_MC6_CTL;
334            break;
335          case 0x41C:
336            regNum = MISCREG_MC7_CTL;
337            break;
338          case 0x401:
339            regNum = MISCREG_MC0_STATUS;
340            break;
341          case 0x405:
342            regNum = MISCREG_MC1_STATUS;
343            break;
344          case 0x409:
345            regNum = MISCREG_MC2_STATUS;
346            break;
347          case 0x40D:
348            regNum = MISCREG_MC3_STATUS;
349            break;
350          case 0x411:
351            regNum = MISCREG_MC4_STATUS;
352            break;
353          case 0x415:
354            regNum = MISCREG_MC5_STATUS;
355            break;
356          case 0x419:
357            regNum = MISCREG_MC6_STATUS;
358            break;
359          case 0x41D:
360            regNum = MISCREG_MC7_STATUS;
361            break;
362          case 0x402:
363            regNum = MISCREG_MC0_ADDR;
364            break;
365          case 0x406:
366            regNum = MISCREG_MC1_ADDR;
367            break;
368          case 0x40A:
369            regNum = MISCREG_MC2_ADDR;
370            break;
371          case 0x40E:
372            regNum = MISCREG_MC3_ADDR;
373            break;
374          case 0x412:
375            regNum = MISCREG_MC4_ADDR;
376            break;
377          case 0x416:
378            regNum = MISCREG_MC5_ADDR;
379            break;
380          case 0x41A:
381            regNum = MISCREG_MC6_ADDR;
382            break;
383          case 0x41E:
384            regNum = MISCREG_MC7_ADDR;
385            break;
386          case 0x403:
387            regNum = MISCREG_MC0_MISC;
388            break;
389          case 0x407:
390            regNum = MISCREG_MC1_MISC;
391            break;
392          case 0x40B:
393            regNum = MISCREG_MC2_MISC;
394            break;
395          case 0x40F:
396            regNum = MISCREG_MC3_MISC;
397            break;
398          case 0x413:
399            regNum = MISCREG_MC4_MISC;
400            break;
401          case 0x417:
402            regNum = MISCREG_MC5_MISC;
403            break;
404          case 0x41B:
405            regNum = MISCREG_MC6_MISC;
406            break;
407          case 0x41F:
408            regNum = MISCREG_MC7_MISC;
409            break;
410          case 0xC0000080:
411            regNum = MISCREG_EFER;
412            break;
413          case 0xC0000081:
414            regNum = MISCREG_STAR;
415            break;
416          case 0xC0000082:
417            regNum = MISCREG_LSTAR;
418            break;
419          case 0xC0000083:
420            regNum = MISCREG_CSTAR;
421            break;
422          case 0xC0000084:
423            regNum = MISCREG_SF_MASK;
424            break;
425          case 0xC0000100:
426            regNum = MISCREG_FS_BASE;
427            break;
428          case 0xC0000101:
429            regNum = MISCREG_GS_BASE;
430            break;
431          case 0xC0000102:
432            regNum = MISCREG_KERNEL_GS_BASE;
433            break;
434          case 0xC0000103:
435            regNum = MISCREG_TSC_AUX;
436            break;
437          case 0xC0010000:
438            regNum = MISCREG_PERF_EVT_SEL0;
439            break;
440          case 0xC0010001:
441            regNum = MISCREG_PERF_EVT_SEL1;
442            break;
443          case 0xC0010002:
444            regNum = MISCREG_PERF_EVT_SEL2;
445            break;
446          case 0xC0010003:
447            regNum = MISCREG_PERF_EVT_SEL3;
448            break;
449          case 0xC0010004:
450            regNum = MISCREG_PERF_EVT_CTR0;
451            break;
452          case 0xC0010005:
453            regNum = MISCREG_PERF_EVT_CTR1;
454            break;
455          case 0xC0010006:
456            regNum = MISCREG_PERF_EVT_CTR2;
457            break;
458          case 0xC0010007:
459            regNum = MISCREG_PERF_EVT_CTR3;
460            break;
461          case 0xC0010010:
462            regNum = MISCREG_SYSCFG;
463            break;
464          case 0xC0010016:
465            regNum = MISCREG_IORR_BASE0;
466            break;
467          case 0xC0010017:
468            regNum = MISCREG_IORR_BASE1;
469            break;
470          case 0xC0010018:
471            regNum = MISCREG_IORR_MASK0;
472            break;
473          case 0xC0010019:
474            regNum = MISCREG_IORR_MASK1;
475            break;
476          case 0xC001001A:
477            regNum = MISCREG_TOP_MEM;
478            break;
479          case 0xC001001D:
480            regNum = MISCREG_TOP_MEM2;
481            break;
482          case 0xC0010114:
483            regNum = MISCREG_VM_CR;
484            break;
485          case 0xC0010115:
486            regNum = MISCREG_IGNNE;
487            break;
488          case 0xC0010116:
489            regNum = MISCREG_SMM_CTL;
490            break;
491          case 0xC0010117:
492            regNum = MISCREG_VM_HSAVE_PA;
493            break;
494          default:
495            return new GeneralProtection(0);
496        }
497        //The index is multiplied by the size of a MiscReg so that
498        //any memory dependence calculations will not see these as
499        //overlapping.
500        req->setPaddr(regNum * sizeof(MiscReg));
501        return NoFault;
502    } else if (prefix == IntAddrPrefixIO) {
503        // TODO If CPL > IOPL or in virtual mode, check the I/O permission
504        // bitmap in the TSS.
505
506        Addr IOPort = vaddr & ~IntAddrPrefixMask;
507        // Make sure the address fits in the expected 16 bit IO address
508        // space.
509        assert(!(IOPort & ~0xFFFF));
510        if (IOPort == 0xCF8 && req->getSize() == 4) {
511            req->setFlags(Request::MMAPED_IPR);
512            req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
513        } else if ((IOPort & ~mask(2)) == 0xCFC) {
514            req->setFlags(Request::UNCACHEABLE);
515            Addr configAddress =
516                tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
517            if (bits(configAddress, 31, 31)) {
518                req->setPaddr(PhysAddrPrefixPciConfig |
519                        mbits(configAddress, 30, 2) |
520                        (IOPort & mask(2)));
521            }
522        } else {
523            req->setFlags(Request::UNCACHEABLE);
524            req->setPaddr(PhysAddrPrefixIO | IOPort);
525        }
526        return NoFault;
527    } else {
528        panic("Access to unrecognized internal address space %#x.\n",
529                prefix);
530    }
531}
532
533Fault
534TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
535        Mode mode, bool &delayedResponse, bool timing)
536{
537    uint32_t flags = req->getFlags();
538    int seg = flags & SegmentFlagMask;
539    bool storeCheck = flags & (StoreCheck << FlagShift);
540
541    // If this is true, we're dealing with a request to a non-memory address
542    // space.
543    if (seg == SEGMENT_REG_MS) {
544        return translateInt(req, tc);
545    }
546
547    delayedResponse = false;
548    Addr vaddr = req->getVaddr();
549    DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
550
551    HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
552
553    // If protected mode has been enabled...
554    if (m5Reg.prot) {
555        DPRINTF(TLB, "In protected mode.\n");
556        // If we're not in 64-bit mode, do protection/limit checks
557        if (m5Reg.mode != LongMode) {
558            DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
559            // Check for a NULL segment selector.
560            if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
561                        seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
562                    && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
563                return new GeneralProtection(0);
564            bool expandDown = false;
565            SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
566            if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
567                if (!attr.writable && (mode == Write || storeCheck))
568                    return new GeneralProtection(0);
569                if (!attr.readable && mode == Read)
570                    return new GeneralProtection(0);
571                expandDown = attr.expandDown;
572
573            }
574            Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
575            Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
576            // This assumes we're not in 64 bit mode. If we were, the default
577            // address size is 64 bits, overridable to 32.
578            int size = 32;
579            bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
580            SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
581            if ((csAttr.defaultSize && sizeOverride) ||
582                    (!csAttr.defaultSize && !sizeOverride))
583                size = 16;
584            Addr offset = bits(vaddr - base, size-1, 0);
585            Addr endOffset = offset + req->getSize() - 1;
586            if (expandDown) {
587                DPRINTF(TLB, "Checking an expand down segment.\n");
588                warn_once("Expand down segments are untested.\n");
589                if (offset <= limit || endOffset <= limit)
590                    return new GeneralProtection(0);
591            } else {
592                if (offset > limit || endOffset > limit)
593                    return new GeneralProtection(0);
594            }
595        }
596        // If paging is enabled, do the translation.
597        if (m5Reg.paging) {
598            DPRINTF(TLB, "Paging enabled.\n");
599            // The vaddr already has the segment base applied.
600            TlbEntry *entry = lookup(vaddr);
601            if (!entry) {
602#if FULL_SYSTEM
603                Fault fault = walker->start(tc, translation, req, mode);
604                if (timing || fault != NoFault) {
605                    // This gets ignored in atomic mode.
606                    delayedResponse = true;
607                    return fault;
608                }
609                entry = lookup(vaddr);
610                assert(entry);
611#else
612                DPRINTF(TLB, "Handling a TLB miss for "
613                        "address %#x at pc %#x.\n",
614                        vaddr, tc->instAddr());
615
616                Process *p = tc->getProcessPtr();
617                TlbEntry newEntry;
618                bool success = p->pTable->lookup(vaddr, newEntry);
619                if (!success && mode != Execute) {
620                    p->checkAndAllocNextPage(vaddr);
621                    success = p->pTable->lookup(vaddr, newEntry);
622                }
623                if (!success) {
624                    return new PageFault(vaddr, true, mode, true, false);
625                } else {
626                    Addr alignedVaddr = p->pTable->pageAlign(vaddr);
627                    DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
628                            newEntry.pageStart());
629                    entry = insert(alignedVaddr, newEntry);
630                }
631                DPRINTF(TLB, "Miss was serviced.\n");
632#endif
633            }
634            // Do paging protection checks.
635            bool inUser = (m5Reg.cpl == 3 &&
636                    !(flags & (CPL0FlagBit << FlagShift)));
637            if ((inUser && !entry->user) ||
638                (mode == Write && !entry->writable)) {
639                // The page must have been present to get into the TLB in
640                // the first place. We'll assume the reserved bits are
641                // fine even though we're not checking them.
642                return new PageFault(vaddr, true, mode, inUser, false);
643            }
644            if (storeCheck && !entry->writable) {
645                // This would fault if this were a write, so return a page
646                // fault that reflects that happening.
647                return new PageFault(vaddr, true, Write, inUser, false);
648            }
649
650
651            DPRINTF(TLB, "Entry found with paddr %#x, "
652                    "doing protection checks.\n", entry->paddr);
653            Addr paddr = entry->paddr | (vaddr & (entry->size-1));
654            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
655            req->setPaddr(paddr);
656            if (entry->uncacheable)
657                req->setFlags(Request::UNCACHEABLE);
658        } else {
659            //Use the address which already has segmentation applied.
660            DPRINTF(TLB, "Paging disabled.\n");
661            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
662            req->setPaddr(vaddr);
663        }
664    } else {
665        // Real mode
666        DPRINTF(TLB, "In real mode.\n");
667        DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
668        req->setPaddr(vaddr);
669    }
670    // Check for an access to the local APIC
671#if FULL_SYSTEM
672    LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
673    Addr baseAddr = localApicBase.base * PageBytes;
674    Addr paddr = req->getPaddr();
675    if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
676        // The Intel developer's manuals say the below restrictions apply,
677        // but the linux kernel, because of a compiler optimization, breaks
678        // them.
679        /*
680        // Check alignment
681        if (paddr & ((32/8) - 1))
682            return new GeneralProtection(0);
683        // Check access size
684        if (req->getSize() != (32/8))
685            return new GeneralProtection(0);
686        */
687        // Force the access to be uncacheable.
688        req->setFlags(Request::UNCACHEABLE);
689        req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
690    }
691#endif
692    return NoFault;
693};
694
695Fault
696TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
697{
698    bool delayedResponse;
699    return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
700}
701
702void
703TLB::translateTiming(RequestPtr req, ThreadContext *tc,
704        Translation *translation, Mode mode)
705{
706    bool delayedResponse;
707    assert(translation);
708    Fault fault =
709        TLB::translate(req, tc, translation, mode, delayedResponse, true);
710    if (!delayedResponse)
711        translation->finish(fault, req, tc, mode);
712}
713
714#if FULL_SYSTEM
715
716Tick
717TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
718{
719    return tc->getCpuPtr()->ticks(1);
720}
721
722Tick
723TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
724{
725    return tc->getCpuPtr()->ticks(1);
726}
727
728#endif
729
730void
731TLB::serialize(std::ostream &os)
732{
733}
734
735void
736TLB::unserialize(Checkpoint *cp, const std::string &section)
737{
738}
739
740/* end namespace X86ISA */ }
741
742X86ISA::TLB *
743X86TLBParams::create()
744{
745    return new X86ISA::TLB(this);
746}
747