tlb.cc revision 6313:95f69a436c82 
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
21 *     Office of Strategy and Technology
22 *     Hewlett-Packard Company
23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution.  Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include <cstring>
59
60#include "config/full_system.hh"
61
62#include "arch/x86/insts/microldstop.hh"
63#include "arch/x86/miscregs.hh"
64#include "arch/x86/pagetable.hh"
65#include "arch/x86/tlb.hh"
66#include "arch/x86/x86_traits.hh"
67#include "base/bitfield.hh"
68#include "base/trace.hh"
69#include "config/full_system.hh"
70#include "cpu/thread_context.hh"
71#include "cpu/base.hh"
72#include "mem/packet_access.hh"
73#include "mem/request.hh"
74
75#if FULL_SYSTEM
76#include "arch/x86/pagetable_walker.hh"
77#else
78#include "mem/page_table.hh"
79#include "sim/process.hh"
80#endif
81
82namespace X86ISA {
83
84TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
85{
86    tlb = new TlbEntry[size];
87    std::memset(tlb, 0, sizeof(TlbEntry) * size);
88
89    for (int x = 0; x < size; x++)
90        freeList.push_back(&tlb[x]);
91
92#if FULL_SYSTEM
93    walker = p->walker;
94    walker->setTLB(this);
95#endif
96}
97
98TlbEntry *
99TLB::insert(Addr vpn, TlbEntry &entry)
100{
101    //TODO Deal with conflicting entries
102
103    TlbEntry *newEntry = NULL;
104    if (!freeList.empty()) {
105        newEntry = freeList.front();
106        freeList.pop_front();
107    } else {
108        newEntry = entryList.back();
109        entryList.pop_back();
110    }
111    *newEntry = entry;
112    newEntry->vaddr = vpn;
113    entryList.push_front(newEntry);
114    return newEntry;
115}
116
117TLB::EntryList::iterator
118TLB::lookupIt(Addr va, bool update_lru)
119{
120    //TODO make this smarter at some point
121    EntryList::iterator entry;
122    for (entry = entryList.begin(); entry != entryList.end(); entry++) {
123        if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
124            DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
125                    "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
126            if (update_lru) {
127                entryList.push_front(*entry);
128                entryList.erase(entry);
129                entry = entryList.begin();
130            }
131            break;
132        }
133    }
134    return entry;
135}
136
137TlbEntry *
138TLB::lookup(Addr va, bool update_lru)
139{
140    EntryList::iterator entry = lookupIt(va, update_lru);
141    if (entry == entryList.end())
142        return NULL;
143    else
144        return *entry;
145}
146
147void
148TLB::invalidateAll()
149{
150    DPRINTF(TLB, "Invalidating all entries.\n");
151    while (!entryList.empty()) {
152        TlbEntry *entry = entryList.front();
153        entryList.pop_front();
154        freeList.push_back(entry);
155    }
156}
157
158void
159TLB::setConfigAddress(uint32_t addr)
160{
161    configAddress = addr;
162}
163
164void
165TLB::invalidateNonGlobal()
166{
167    DPRINTF(TLB, "Invalidating all non global entries.\n");
168    EntryList::iterator entryIt;
169    for (entryIt = entryList.begin(); entryIt != entryList.end();) {
170        if (!(*entryIt)->global) {
171            freeList.push_back(*entryIt);
172            entryList.erase(entryIt++);
173        } else {
174            entryIt++;
175        }
176    }
177}
178
179void
180TLB::demapPage(Addr va, uint64_t asn)
181{
182    EntryList::iterator entry = lookupIt(va, false);
183    if (entry != entryList.end()) {
184        freeList.push_back(*entry);
185        entryList.erase(entry);
186    }
187}
188
189Fault
190TLB::translateInt(RequestPtr req, ThreadContext *tc)
191{
192    DPRINTF(TLB, "Addresses references internal memory.\n");
193    Addr vaddr = req->getVaddr();
194    Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
195    if (prefix == IntAddrPrefixCPUID) {
196        panic("CPUID memory space not yet implemented!\n");
197    } else if (prefix == IntAddrPrefixMSR) {
198        vaddr = vaddr >> 3;
199        req->setMmapedIpr(true);
200        Addr regNum = 0;
201        switch (vaddr & ~IntAddrPrefixMask) {
202          case 0x10:
203            regNum = MISCREG_TSC;
204            break;
205          case 0x1B:
206            regNum = MISCREG_APIC_BASE;
207            break;
208          case 0xFE:
209            regNum = MISCREG_MTRRCAP;
210            break;
211          case 0x174:
212            regNum = MISCREG_SYSENTER_CS;
213            break;
214          case 0x175:
215            regNum = MISCREG_SYSENTER_ESP;
216            break;
217          case 0x176:
218            regNum = MISCREG_SYSENTER_EIP;
219            break;
220          case 0x179:
221            regNum = MISCREG_MCG_CAP;
222            break;
223          case 0x17A:
224            regNum = MISCREG_MCG_STATUS;
225            break;
226          case 0x17B:
227            regNum = MISCREG_MCG_CTL;
228            break;
229          case 0x1D9:
230            regNum = MISCREG_DEBUG_CTL_MSR;
231            break;
232          case 0x1DB:
233            regNum = MISCREG_LAST_BRANCH_FROM_IP;
234            break;
235          case 0x1DC:
236            regNum = MISCREG_LAST_BRANCH_TO_IP;
237            break;
238          case 0x1DD:
239            regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
240            break;
241          case 0x1DE:
242            regNum = MISCREG_LAST_EXCEPTION_TO_IP;
243            break;
244          case 0x200:
245            regNum = MISCREG_MTRR_PHYS_BASE_0;
246            break;
247          case 0x201:
248            regNum = MISCREG_MTRR_PHYS_MASK_0;
249            break;
250          case 0x202:
251            regNum = MISCREG_MTRR_PHYS_BASE_1;
252            break;
253          case 0x203:
254            regNum = MISCREG_MTRR_PHYS_MASK_1;
255            break;
256          case 0x204:
257            regNum = MISCREG_MTRR_PHYS_BASE_2;
258            break;
259          case 0x205:
260            regNum = MISCREG_MTRR_PHYS_MASK_2;
261            break;
262          case 0x206:
263            regNum = MISCREG_MTRR_PHYS_BASE_3;
264            break;
265          case 0x207:
266            regNum = MISCREG_MTRR_PHYS_MASK_3;
267            break;
268          case 0x208:
269            regNum = MISCREG_MTRR_PHYS_BASE_4;
270            break;
271          case 0x209:
272            regNum = MISCREG_MTRR_PHYS_MASK_4;
273            break;
274          case 0x20A:
275            regNum = MISCREG_MTRR_PHYS_BASE_5;
276            break;
277          case 0x20B:
278            regNum = MISCREG_MTRR_PHYS_MASK_5;
279            break;
280          case 0x20C:
281            regNum = MISCREG_MTRR_PHYS_BASE_6;
282            break;
283          case 0x20D:
284            regNum = MISCREG_MTRR_PHYS_MASK_6;
285            break;
286          case 0x20E:
287            regNum = MISCREG_MTRR_PHYS_BASE_7;
288            break;
289          case 0x20F:
290            regNum = MISCREG_MTRR_PHYS_MASK_7;
291            break;
292          case 0x250:
293            regNum = MISCREG_MTRR_FIX_64K_00000;
294            break;
295          case 0x258:
296            regNum = MISCREG_MTRR_FIX_16K_80000;
297            break;
298          case 0x259:
299            regNum = MISCREG_MTRR_FIX_16K_A0000;
300            break;
301          case 0x268:
302            regNum = MISCREG_MTRR_FIX_4K_C0000;
303            break;
304          case 0x269:
305            regNum = MISCREG_MTRR_FIX_4K_C8000;
306            break;
307          case 0x26A:
308            regNum = MISCREG_MTRR_FIX_4K_D0000;
309            break;
310          case 0x26B:
311            regNum = MISCREG_MTRR_FIX_4K_D8000;
312            break;
313          case 0x26C:
314            regNum = MISCREG_MTRR_FIX_4K_E0000;
315            break;
316          case 0x26D:
317            regNum = MISCREG_MTRR_FIX_4K_E8000;
318            break;
319          case 0x26E:
320            regNum = MISCREG_MTRR_FIX_4K_F0000;
321            break;
322          case 0x26F:
323            regNum = MISCREG_MTRR_FIX_4K_F8000;
324            break;
325          case 0x277:
326            regNum = MISCREG_PAT;
327            break;
328          case 0x2FF:
329            regNum = MISCREG_DEF_TYPE;
330            break;
331          case 0x400:
332            regNum = MISCREG_MC0_CTL;
333            break;
334          case 0x404:
335            regNum = MISCREG_MC1_CTL;
336            break;
337          case 0x408:
338            regNum = MISCREG_MC2_CTL;
339            break;
340          case 0x40C:
341            regNum = MISCREG_MC3_CTL;
342            break;
343          case 0x410:
344            regNum = MISCREG_MC4_CTL;
345            break;
346          case 0x414:
347            regNum = MISCREG_MC5_CTL;
348            break;
349          case 0x418:
350            regNum = MISCREG_MC6_CTL;
351            break;
352          case 0x41C:
353            regNum = MISCREG_MC7_CTL;
354            break;
355          case 0x401:
356            regNum = MISCREG_MC0_STATUS;
357            break;
358          case 0x405:
359            regNum = MISCREG_MC1_STATUS;
360            break;
361          case 0x409:
362            regNum = MISCREG_MC2_STATUS;
363            break;
364          case 0x40D:
365            regNum = MISCREG_MC3_STATUS;
366            break;
367          case 0x411:
368            regNum = MISCREG_MC4_STATUS;
369            break;
370          case 0x415:
371            regNum = MISCREG_MC5_STATUS;
372            break;
373          case 0x419:
374            regNum = MISCREG_MC6_STATUS;
375            break;
376          case 0x41D:
377            regNum = MISCREG_MC7_STATUS;
378            break;
379          case 0x402:
380            regNum = MISCREG_MC0_ADDR;
381            break;
382          case 0x406:
383            regNum = MISCREG_MC1_ADDR;
384            break;
385          case 0x40A:
386            regNum = MISCREG_MC2_ADDR;
387            break;
388          case 0x40E:
389            regNum = MISCREG_MC3_ADDR;
390            break;
391          case 0x412:
392            regNum = MISCREG_MC4_ADDR;
393            break;
394          case 0x416:
395            regNum = MISCREG_MC5_ADDR;
396            break;
397          case 0x41A:
398            regNum = MISCREG_MC6_ADDR;
399            break;
400          case 0x41E:
401            regNum = MISCREG_MC7_ADDR;
402            break;
403          case 0x403:
404            regNum = MISCREG_MC0_MISC;
405            break;
406          case 0x407:
407            regNum = MISCREG_MC1_MISC;
408            break;
409          case 0x40B:
410            regNum = MISCREG_MC2_MISC;
411            break;
412          case 0x40F:
413            regNum = MISCREG_MC3_MISC;
414            break;
415          case 0x413:
416            regNum = MISCREG_MC4_MISC;
417            break;
418          case 0x417:
419            regNum = MISCREG_MC5_MISC;
420            break;
421          case 0x41B:
422            regNum = MISCREG_MC6_MISC;
423            break;
424          case 0x41F:
425            regNum = MISCREG_MC7_MISC;
426            break;
427          case 0xC0000080:
428            regNum = MISCREG_EFER;
429            break;
430          case 0xC0000081:
431            regNum = MISCREG_STAR;
432            break;
433          case 0xC0000082:
434            regNum = MISCREG_LSTAR;
435            break;
436          case 0xC0000083:
437            regNum = MISCREG_CSTAR;
438            break;
439          case 0xC0000084:
440            regNum = MISCREG_SF_MASK;
441            break;
442          case 0xC0000100:
443            regNum = MISCREG_FS_BASE;
444            break;
445          case 0xC0000101:
446            regNum = MISCREG_GS_BASE;
447            break;
448          case 0xC0000102:
449            regNum = MISCREG_KERNEL_GS_BASE;
450            break;
451          case 0xC0000103:
452            regNum = MISCREG_TSC_AUX;
453            break;
454          case 0xC0010000:
455            regNum = MISCREG_PERF_EVT_SEL0;
456            break;
457          case 0xC0010001:
458            regNum = MISCREG_PERF_EVT_SEL1;
459            break;
460          case 0xC0010002:
461            regNum = MISCREG_PERF_EVT_SEL2;
462            break;
463          case 0xC0010003:
464            regNum = MISCREG_PERF_EVT_SEL3;
465            break;
466          case 0xC0010004:
467            regNum = MISCREG_PERF_EVT_CTR0;
468            break;
469          case 0xC0010005:
470            regNum = MISCREG_PERF_EVT_CTR1;
471            break;
472          case 0xC0010006:
473            regNum = MISCREG_PERF_EVT_CTR2;
474            break;
475          case 0xC0010007:
476            regNum = MISCREG_PERF_EVT_CTR3;
477            break;
478          case 0xC0010010:
479            regNum = MISCREG_SYSCFG;
480            break;
481          case 0xC0010016:
482            regNum = MISCREG_IORR_BASE0;
483            break;
484          case 0xC0010017:
485            regNum = MISCREG_IORR_BASE1;
486            break;
487          case 0xC0010018:
488            regNum = MISCREG_IORR_MASK0;
489            break;
490          case 0xC0010019:
491            regNum = MISCREG_IORR_MASK1;
492            break;
493          case 0xC001001A:
494            regNum = MISCREG_TOP_MEM;
495            break;
496          case 0xC001001D:
497            regNum = MISCREG_TOP_MEM2;
498            break;
499          case 0xC0010114:
500            regNum = MISCREG_VM_CR;
501            break;
502          case 0xC0010115:
503            regNum = MISCREG_IGNNE;
504            break;
505          case 0xC0010116:
506            regNum = MISCREG_SMM_CTL;
507            break;
508          case 0xC0010117:
509            regNum = MISCREG_VM_HSAVE_PA;
510            break;
511          default:
512            return new GeneralProtection(0);
513        }
514        //The index is multiplied by the size of a MiscReg so that
515        //any memory dependence calculations will not see these as
516        //overlapping.
517        req->setPaddr(regNum * sizeof(MiscReg));
518        return NoFault;
519    } else if (prefix == IntAddrPrefixIO) {
520        // TODO If CPL > IOPL or in virtual mode, check the I/O permission
521        // bitmap in the TSS.
522
523        Addr IOPort = vaddr & ~IntAddrPrefixMask;
524        // Make sure the address fits in the expected 16 bit IO address
525        // space.
526        assert(!(IOPort & ~0xFFFF));
527        if (IOPort == 0xCF8 && req->getSize() == 4) {
528            req->setMmapedIpr(true);
529            req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
530        } else if ((IOPort & ~mask(2)) == 0xCFC) {
531            Addr configAddress =
532                tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
533            if (bits(configAddress, 31, 31)) {
534                req->setPaddr(PhysAddrPrefixPciConfig |
535                        mbits(configAddress, 30, 2) |
536                        (IOPort & mask(2)));
537            }
538        } else {
539            req->setPaddr(PhysAddrPrefixIO | IOPort);
540        }
541        return NoFault;
542    } else {
543        panic("Access to unrecognized internal address space %#x.\n",
544                prefix);
545    }
546}
547
548Fault
549TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
550        Mode mode, bool &delayedResponse, bool timing)
551{
552    uint32_t flags = req->getFlags();
553    int seg = flags & SegmentFlagMask;
554    bool storeCheck = flags & (StoreCheck << FlagShift);
555
556    // If this is true, we're dealing with a request to a non-memory address
557    // space.
558    if (seg == SEGMENT_REG_MS) {
559        return translateInt(req, tc);
560    }
561
562    delayedResponse = false;
563    Addr vaddr = req->getVaddr();
564    DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
565
566    HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
567
568    // If protected mode has been enabled...
569    if (m5Reg.prot) {
570        DPRINTF(TLB, "In protected mode.\n");
571        // If we're not in 64-bit mode, do protection/limit checks
572        if (m5Reg.mode != LongMode) {
573            DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
574            // Check for a NULL segment selector.
575            if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
576                        seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
577                    && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
578                return new GeneralProtection(0);
579            bool expandDown = false;
580            SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
581            if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
582                if (!attr.writable && (mode == Write || storeCheck))
583                    return new GeneralProtection(0);
584                if (!attr.readable && mode == Read)
585                    return new GeneralProtection(0);
586                expandDown = attr.expandDown;
587
588            }
589            Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
590            Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
591            // This assumes we're not in 64 bit mode. If we were, the default
592            // address size is 64 bits, overridable to 32.
593            int size = 32;
594            bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
595            SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
596            if ((csAttr.defaultSize && sizeOverride) ||
597                    (!csAttr.defaultSize && !sizeOverride))
598                size = 16;
599            Addr offset = bits(vaddr - base, size-1, 0);
600            Addr endOffset = offset + req->getSize() - 1;
601            if (expandDown) {
602                DPRINTF(TLB, "Checking an expand down segment.\n");
603                warn_once("Expand down segments are untested.\n");
604                if (offset <= limit || endOffset <= limit)
605                    return new GeneralProtection(0);
606            } else {
607                if (offset > limit || endOffset > limit)
608                    return new GeneralProtection(0);
609            }
610        }
611        // If paging is enabled, do the translation.
612        if (m5Reg.paging) {
613            DPRINTF(TLB, "Paging enabled.\n");
614            // The vaddr already has the segment base applied.
615            TlbEntry *entry = lookup(vaddr);
616            if (!entry) {
617#if FULL_SYSTEM
618                Fault fault = walker->start(tc, translation, req, mode);
619                if (timing || fault != NoFault) {
620                    // This gets ignored in atomic mode.
621                    delayedResponse = true;
622                    return fault;
623                }
624                entry = lookup(vaddr);
625                assert(entry);
626#else
627                DPRINTF(TLB, "Handling a TLB miss for "
628                        "address %#x at pc %#x.\n",
629                        vaddr, tc->readPC());
630
631                Process *p = tc->getProcessPtr();
632                TlbEntry newEntry;
633                bool success = p->pTable->lookup(vaddr, newEntry);
634                if(!success && mode != Execute) {
635                    p->checkAndAllocNextPage(vaddr);
636                    success = p->pTable->lookup(vaddr, newEntry);
637                }
638                if(!success) {
639                    panic("Tried to execute unmapped address %#x.\n", vaddr);
640                } else {
641                    Addr alignedVaddr = p->pTable->pageAlign(vaddr);
642                    DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
643                            newEntry.pageStart());
644                    entry = insert(alignedVaddr, newEntry);
645                }
646                DPRINTF(TLB, "Miss was serviced.\n");
647#endif
648            }
649            // Do paging protection checks.
650            bool inUser = (m5Reg.cpl == 3 &&
651                    !(flags & (CPL0FlagBit << FlagShift)));
652            if ((inUser && !entry->user) ||
653                (mode == Write && !entry->writable)) {
654                // The page must have been present to get into the TLB in
655                // the first place. We'll assume the reserved bits are
656                // fine even though we're not checking them.
657                return new PageFault(vaddr, true, mode, inUser, false);
658            }
659            if (storeCheck && !entry->writable) {
660                // This would fault if this were a write, so return a page
661                // fault that reflects that happening.
662                return new PageFault(vaddr, true, Write, inUser, false);
663            }
664
665
666            DPRINTF(TLB, "Entry found with paddr %#x, "
667                    "doing protection checks.\n", entry->paddr);
668            Addr paddr = entry->paddr | (vaddr & (entry->size-1));
669            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
670            req->setPaddr(paddr);
671        } else {
672            //Use the address which already has segmentation applied.
673            DPRINTF(TLB, "Paging disabled.\n");
674            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
675            req->setPaddr(vaddr);
676        }
677    } else {
678        // Real mode
679        DPRINTF(TLB, "In real mode.\n");
680        DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
681        req->setPaddr(vaddr);
682    }
683    // Check for an access to the local APIC
684#if FULL_SYSTEM
685    LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
686    Addr baseAddr = localApicBase.base * PageBytes;
687    Addr paddr = req->getPaddr();
688    if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
689        // The Intel developer's manuals say the below restrictions apply,
690        // but the linux kernel, because of a compiler optimization, breaks
691        // them.
692        /*
693        // Check alignment
694        if (paddr & ((32/8) - 1))
695            return new GeneralProtection(0);
696        // Check access size
697        if (req->getSize() != (32/8))
698            return new GeneralProtection(0);
699        */
700        // Force the access to be uncacheable.
701        req->setFlags(Request::UNCACHEABLE);
702        req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
703    }
704#endif
705    return NoFault;
706};
707
708Fault
709TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
710{
711    bool delayedResponse;
712    return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
713}
714
715void
716TLB::translateTiming(RequestPtr req, ThreadContext *tc,
717        Translation *translation, Mode mode)
718{
719    bool delayedResponse;
720    assert(translation);
721    Fault fault =
722        TLB::translate(req, tc, translation, mode, delayedResponse, true);
723    if (!delayedResponse)
724        translation->finish(fault, req, tc, mode);
725}
726
727#if FULL_SYSTEM
728
729Tick
730TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
731{
732    return tc->getCpuPtr()->ticks(1);
733}
734
735Tick
736TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
737{
738    return tc->getCpuPtr()->ticks(1);
739}
740
741#endif
742
743void
744TLB::serialize(std::ostream &os)
745{
746}
747
748void
749TLB::unserialize(Checkpoint *cp, const std::string &section)
750{
751}
752
753/* end namespace X86ISA */ }
754
755X86ISA::TLB *
756X86TLBParams::create()
757{
758    return new X86ISA::TLB(this);
759}
760