tlb.cc revision 6141:5babc3f3d8c8
1/* 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary 11 * compensation for, or commercial advantage from such use. Illustrative 12 * examples of non-commercial use are academic research, personal study, 13 * teaching, education and corporate research & development. 14 * Illustrative examples of commercial use are distributing products for 15 * commercial advantage and providing services using the software for 16 * commercial advantage. 17 * 18 * If you wish to use this software or functionality therein that may be 19 * covered by patents for commercial use, please contact: 20 * Director of Intellectual Property Licensing 21 * Office of Strategy and Technology 22 * Hewlett-Packard Company 23 * 1501 Page Mill Road 24 * Palo Alto, California 94304 25 * 26 * Redistributions of source code must retain the above copyright notice, 27 * this list of conditions and the following disclaimer. Redistributions 28 * in binary form must reproduce the above copyright notice, this list of 29 * conditions and the following disclaimer in the documentation and/or 30 * other materials provided with the distribution. Neither the name of 31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 32 * contributors may be used to endorse or promote products derived from 33 * this software without specific prior written permission. No right of 34 * sublicense is granted herewith. Derivatives of the software and 35 * output created using the software may be prepared, but only for 36 * Non-Commercial Uses. Derivatives of the software may be shared with 37 * others provided: (i) the others agree to abide by the list of 38 * conditions herein which includes the Non-Commercial Use restrictions; 39 * and (ii) such Derivatives of the software include the above copyright 40 * notice to acknowledge the contribution from this software where 41 * applicable, this list of conditions and the disclaimer below. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#include <cstring> 59 60#include "config/full_system.hh" 61 62#include "arch/x86/insts/microldstop.hh" 63#include "arch/x86/pagetable.hh" 64#include "arch/x86/tlb.hh" 65#include "arch/x86/x86_traits.hh" 66#include "base/bitfield.hh" 67#include "base/trace.hh" 68#include "config/full_system.hh" 69#include "cpu/thread_context.hh" 70#include "cpu/base.hh" 71#include "mem/packet_access.hh" 72#include "mem/request.hh" 73 74#if FULL_SYSTEM 75#include "arch/x86/pagetable_walker.hh" 76#else 77#include "mem/page_table.hh" 78#include "sim/process.hh" 79#endif 80 81namespace X86ISA { 82 83TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size) 84{ 85 tlb = new TlbEntry[size]; 86 std::memset(tlb, 0, sizeof(TlbEntry) * size); 87 88 for (int x = 0; x < size; x++) 89 freeList.push_back(&tlb[x]); 90 91#if FULL_SYSTEM 92 walker = p->walker; 93 walker->setTLB(this); 94#endif 95} 96 97TlbEntry * 98TLB::insert(Addr vpn, TlbEntry &entry) 99{ 100 //TODO Deal with conflicting entries 101 102 TlbEntry *newEntry = NULL; 103 if (!freeList.empty()) { 104 newEntry = freeList.front(); 105 freeList.pop_front(); 106 } else { 107 newEntry = entryList.back(); 108 entryList.pop_back(); 109 } 110 *newEntry = entry; 111 newEntry->vaddr = vpn; 112 entryList.push_front(newEntry); 113 return newEntry; 114} 115 116TLB::EntryList::iterator 117TLB::lookupIt(Addr va, bool update_lru) 118{ 119 //TODO make this smarter at some point 120 EntryList::iterator entry; 121 for (entry = entryList.begin(); entry != entryList.end(); entry++) { 122 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) { 123 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x " 124 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size); 125 if (update_lru) { 126 entryList.push_front(*entry); 127 entryList.erase(entry); 128 entry = entryList.begin(); 129 } 130 break; 131 } 132 } 133 return entry; 134} 135 136TlbEntry * 137TLB::lookup(Addr va, bool update_lru) 138{ 139 EntryList::iterator entry = lookupIt(va, update_lru); 140 if (entry == entryList.end()) 141 return NULL; 142 else 143 return *entry; 144} 145 146void 147TLB::invalidateAll() 148{ 149 DPRINTF(TLB, "Invalidating all entries.\n"); 150 while (!entryList.empty()) { 151 TlbEntry *entry = entryList.front(); 152 entryList.pop_front(); 153 freeList.push_back(entry); 154 } 155} 156 157void 158TLB::setConfigAddress(uint32_t addr) 159{ 160 configAddress = addr; 161} 162 163void 164TLB::invalidateNonGlobal() 165{ 166 DPRINTF(TLB, "Invalidating all non global entries.\n"); 167 EntryList::iterator entryIt; 168 for (entryIt = entryList.begin(); entryIt != entryList.end();) { 169 if (!(*entryIt)->global) { 170 freeList.push_back(*entryIt); 171 entryList.erase(entryIt++); 172 } else { 173 entryIt++; 174 } 175 } 176} 177 178void 179TLB::demapPage(Addr va, uint64_t asn) 180{ 181 EntryList::iterator entry = lookupIt(va, false); 182 if (entry != entryList.end()) { 183 freeList.push_back(*entry); 184 entryList.erase(entry); 185 } 186} 187 188Fault 189TLB::translateInt(RequestPtr req, ThreadContext *tc) 190{ 191 DPRINTF(TLB, "Addresses references internal memory.\n"); 192 Addr vaddr = req->getVaddr(); 193 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 194 if (prefix == IntAddrPrefixCPUID) { 195 panic("CPUID memory space not yet implemented!\n"); 196 } else if (prefix == IntAddrPrefixMSR) { 197 vaddr = vaddr >> 3; 198 req->setMmapedIpr(true); 199 Addr regNum = 0; 200 switch (vaddr & ~IntAddrPrefixMask) { 201 case 0x10: 202 regNum = MISCREG_TSC; 203 break; 204 case 0x1B: 205 regNum = MISCREG_APIC_BASE; 206 break; 207 case 0xFE: 208 regNum = MISCREG_MTRRCAP; 209 break; 210 case 0x174: 211 regNum = MISCREG_SYSENTER_CS; 212 break; 213 case 0x175: 214 regNum = MISCREG_SYSENTER_ESP; 215 break; 216 case 0x176: 217 regNum = MISCREG_SYSENTER_EIP; 218 break; 219 case 0x179: 220 regNum = MISCREG_MCG_CAP; 221 break; 222 case 0x17A: 223 regNum = MISCREG_MCG_STATUS; 224 break; 225 case 0x17B: 226 regNum = MISCREG_MCG_CTL; 227 break; 228 case 0x1D9: 229 regNum = MISCREG_DEBUG_CTL_MSR; 230 break; 231 case 0x1DB: 232 regNum = MISCREG_LAST_BRANCH_FROM_IP; 233 break; 234 case 0x1DC: 235 regNum = MISCREG_LAST_BRANCH_TO_IP; 236 break; 237 case 0x1DD: 238 regNum = MISCREG_LAST_EXCEPTION_FROM_IP; 239 break; 240 case 0x1DE: 241 regNum = MISCREG_LAST_EXCEPTION_TO_IP; 242 break; 243 case 0x200: 244 regNum = MISCREG_MTRR_PHYS_BASE_0; 245 break; 246 case 0x201: 247 regNum = MISCREG_MTRR_PHYS_MASK_0; 248 break; 249 case 0x202: 250 regNum = MISCREG_MTRR_PHYS_BASE_1; 251 break; 252 case 0x203: 253 regNum = MISCREG_MTRR_PHYS_MASK_1; 254 break; 255 case 0x204: 256 regNum = MISCREG_MTRR_PHYS_BASE_2; 257 break; 258 case 0x205: 259 regNum = MISCREG_MTRR_PHYS_MASK_2; 260 break; 261 case 0x206: 262 regNum = MISCREG_MTRR_PHYS_BASE_3; 263 break; 264 case 0x207: 265 regNum = MISCREG_MTRR_PHYS_MASK_3; 266 break; 267 case 0x208: 268 regNum = MISCREG_MTRR_PHYS_BASE_4; 269 break; 270 case 0x209: 271 regNum = MISCREG_MTRR_PHYS_MASK_4; 272 break; 273 case 0x20A: 274 regNum = MISCREG_MTRR_PHYS_BASE_5; 275 break; 276 case 0x20B: 277 regNum = MISCREG_MTRR_PHYS_MASK_5; 278 break; 279 case 0x20C: 280 regNum = MISCREG_MTRR_PHYS_BASE_6; 281 break; 282 case 0x20D: 283 regNum = MISCREG_MTRR_PHYS_MASK_6; 284 break; 285 case 0x20E: 286 regNum = MISCREG_MTRR_PHYS_BASE_7; 287 break; 288 case 0x20F: 289 regNum = MISCREG_MTRR_PHYS_MASK_7; 290 break; 291 case 0x250: 292 regNum = MISCREG_MTRR_FIX_64K_00000; 293 break; 294 case 0x258: 295 regNum = MISCREG_MTRR_FIX_16K_80000; 296 break; 297 case 0x259: 298 regNum = MISCREG_MTRR_FIX_16K_A0000; 299 break; 300 case 0x268: 301 regNum = MISCREG_MTRR_FIX_4K_C0000; 302 break; 303 case 0x269: 304 regNum = MISCREG_MTRR_FIX_4K_C8000; 305 break; 306 case 0x26A: 307 regNum = MISCREG_MTRR_FIX_4K_D0000; 308 break; 309 case 0x26B: 310 regNum = MISCREG_MTRR_FIX_4K_D8000; 311 break; 312 case 0x26C: 313 regNum = MISCREG_MTRR_FIX_4K_E0000; 314 break; 315 case 0x26D: 316 regNum = MISCREG_MTRR_FIX_4K_E8000; 317 break; 318 case 0x26E: 319 regNum = MISCREG_MTRR_FIX_4K_F0000; 320 break; 321 case 0x26F: 322 regNum = MISCREG_MTRR_FIX_4K_F8000; 323 break; 324 case 0x277: 325 regNum = MISCREG_PAT; 326 break; 327 case 0x2FF: 328 regNum = MISCREG_DEF_TYPE; 329 break; 330 case 0x400: 331 regNum = MISCREG_MC0_CTL; 332 break; 333 case 0x404: 334 regNum = MISCREG_MC1_CTL; 335 break; 336 case 0x408: 337 regNum = MISCREG_MC2_CTL; 338 break; 339 case 0x40C: 340 regNum = MISCREG_MC3_CTL; 341 break; 342 case 0x410: 343 regNum = MISCREG_MC4_CTL; 344 break; 345 case 0x414: 346 regNum = MISCREG_MC5_CTL; 347 break; 348 case 0x418: 349 regNum = MISCREG_MC6_CTL; 350 break; 351 case 0x41C: 352 regNum = MISCREG_MC7_CTL; 353 break; 354 case 0x401: 355 regNum = MISCREG_MC0_STATUS; 356 break; 357 case 0x405: 358 regNum = MISCREG_MC1_STATUS; 359 break; 360 case 0x409: 361 regNum = MISCREG_MC2_STATUS; 362 break; 363 case 0x40D: 364 regNum = MISCREG_MC3_STATUS; 365 break; 366 case 0x411: 367 regNum = MISCREG_MC4_STATUS; 368 break; 369 case 0x415: 370 regNum = MISCREG_MC5_STATUS; 371 break; 372 case 0x419: 373 regNum = MISCREG_MC6_STATUS; 374 break; 375 case 0x41D: 376 regNum = MISCREG_MC7_STATUS; 377 break; 378 case 0x402: 379 regNum = MISCREG_MC0_ADDR; 380 break; 381 case 0x406: 382 regNum = MISCREG_MC1_ADDR; 383 break; 384 case 0x40A: 385 regNum = MISCREG_MC2_ADDR; 386 break; 387 case 0x40E: 388 regNum = MISCREG_MC3_ADDR; 389 break; 390 case 0x412: 391 regNum = MISCREG_MC4_ADDR; 392 break; 393 case 0x416: 394 regNum = MISCREG_MC5_ADDR; 395 break; 396 case 0x41A: 397 regNum = MISCREG_MC6_ADDR; 398 break; 399 case 0x41E: 400 regNum = MISCREG_MC7_ADDR; 401 break; 402 case 0x403: 403 regNum = MISCREG_MC0_MISC; 404 break; 405 case 0x407: 406 regNum = MISCREG_MC1_MISC; 407 break; 408 case 0x40B: 409 regNum = MISCREG_MC2_MISC; 410 break; 411 case 0x40F: 412 regNum = MISCREG_MC3_MISC; 413 break; 414 case 0x413: 415 regNum = MISCREG_MC4_MISC; 416 break; 417 case 0x417: 418 regNum = MISCREG_MC5_MISC; 419 break; 420 case 0x41B: 421 regNum = MISCREG_MC6_MISC; 422 break; 423 case 0x41F: 424 regNum = MISCREG_MC7_MISC; 425 break; 426 case 0xC0000080: 427 regNum = MISCREG_EFER; 428 break; 429 case 0xC0000081: 430 regNum = MISCREG_STAR; 431 break; 432 case 0xC0000082: 433 regNum = MISCREG_LSTAR; 434 break; 435 case 0xC0000083: 436 regNum = MISCREG_CSTAR; 437 break; 438 case 0xC0000084: 439 regNum = MISCREG_SF_MASK; 440 break; 441 case 0xC0000100: 442 regNum = MISCREG_FS_BASE; 443 break; 444 case 0xC0000101: 445 regNum = MISCREG_GS_BASE; 446 break; 447 case 0xC0000102: 448 regNum = MISCREG_KERNEL_GS_BASE; 449 break; 450 case 0xC0000103: 451 regNum = MISCREG_TSC_AUX; 452 break; 453 case 0xC0010000: 454 regNum = MISCREG_PERF_EVT_SEL0; 455 break; 456 case 0xC0010001: 457 regNum = MISCREG_PERF_EVT_SEL1; 458 break; 459 case 0xC0010002: 460 regNum = MISCREG_PERF_EVT_SEL2; 461 break; 462 case 0xC0010003: 463 regNum = MISCREG_PERF_EVT_SEL3; 464 break; 465 case 0xC0010004: 466 regNum = MISCREG_PERF_EVT_CTR0; 467 break; 468 case 0xC0010005: 469 regNum = MISCREG_PERF_EVT_CTR1; 470 break; 471 case 0xC0010006: 472 regNum = MISCREG_PERF_EVT_CTR2; 473 break; 474 case 0xC0010007: 475 regNum = MISCREG_PERF_EVT_CTR3; 476 break; 477 case 0xC0010010: 478 regNum = MISCREG_SYSCFG; 479 break; 480 case 0xC0010016: 481 regNum = MISCREG_IORR_BASE0; 482 break; 483 case 0xC0010017: 484 regNum = MISCREG_IORR_BASE1; 485 break; 486 case 0xC0010018: 487 regNum = MISCREG_IORR_MASK0; 488 break; 489 case 0xC0010019: 490 regNum = MISCREG_IORR_MASK1; 491 break; 492 case 0xC001001A: 493 regNum = MISCREG_TOP_MEM; 494 break; 495 case 0xC001001D: 496 regNum = MISCREG_TOP_MEM2; 497 break; 498 case 0xC0010114: 499 regNum = MISCREG_VM_CR; 500 break; 501 case 0xC0010115: 502 regNum = MISCREG_IGNNE; 503 break; 504 case 0xC0010116: 505 regNum = MISCREG_SMM_CTL; 506 break; 507 case 0xC0010117: 508 regNum = MISCREG_VM_HSAVE_PA; 509 break; 510 default: 511 return new GeneralProtection(0); 512 } 513 //The index is multiplied by the size of a MiscReg so that 514 //any memory dependence calculations will not see these as 515 //overlapping. 516 req->setPaddr(regNum * sizeof(MiscReg)); 517 return NoFault; 518 } else if (prefix == IntAddrPrefixIO) { 519 // TODO If CPL > IOPL or in virtual mode, check the I/O permission 520 // bitmap in the TSS. 521 522 Addr IOPort = vaddr & ~IntAddrPrefixMask; 523 // Make sure the address fits in the expected 16 bit IO address 524 // space. 525 assert(!(IOPort & ~0xFFFF)); 526 if (IOPort == 0xCF8 && req->getSize() == 4) { 527 req->setMmapedIpr(true); 528 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 529 } else if ((IOPort & ~mask(2)) == 0xCFC) { 530 Addr configAddress = 531 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 532 if (bits(configAddress, 31, 31)) { 533 req->setPaddr(PhysAddrPrefixPciConfig | 534 mbits(configAddress, 30, 2) | 535 (IOPort & mask(2))); 536 } 537 } else { 538 req->setPaddr(PhysAddrPrefixIO | IOPort); 539 } 540 return NoFault; 541 } else { 542 panic("Access to unrecognized internal address space %#x.\n", 543 prefix); 544 } 545} 546 547Fault 548TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, 549 Mode mode, bool &delayedResponse, bool timing) 550{ 551 uint32_t flags = req->getFlags(); 552 int seg = flags & SegmentFlagMask; 553 bool storeCheck = flags & (StoreCheck << FlagShift); 554 555 // If this is true, we're dealing with a request to a non-memory address 556 // space. 557 if (seg == SEGMENT_REG_MS) { 558 return translateInt(req, tc); 559 } 560 561 delayedResponse = false; 562 Addr vaddr = req->getVaddr(); 563 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 564 565 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 566 567 // If protected mode has been enabled... 568 if (m5Reg.prot) { 569 DPRINTF(TLB, "In protected mode.\n"); 570 // If we're not in 64-bit mode, do protection/limit checks 571 if (m5Reg.mode != LongMode) { 572 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 573 // Check for a NULL segment selector. 574 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 575 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 576 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 577 return new GeneralProtection(0); 578 bool expandDown = false; 579 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 580 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 581 if (!attr.writable && (mode == Write || storeCheck)) 582 return new GeneralProtection(0); 583 if (!attr.readable && mode == Read) 584 return new GeneralProtection(0); 585 expandDown = attr.expandDown; 586 587 } 588 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 589 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 590 // This assumes we're not in 64 bit mode. If we were, the default 591 // address size is 64 bits, overridable to 32. 592 int size = 32; 593 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 594 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR); 595 if ((csAttr.defaultSize && sizeOverride) || 596 (!csAttr.defaultSize && !sizeOverride)) 597 size = 16; 598 Addr offset = bits(vaddr - base, size-1, 0); 599 Addr endOffset = offset + req->getSize() - 1; 600 if (expandDown) { 601 DPRINTF(TLB, "Checking an expand down segment.\n"); 602 warn_once("Expand down segments are untested.\n"); 603 if (offset <= limit || endOffset <= limit) 604 return new GeneralProtection(0); 605 } else { 606 if (offset > limit || endOffset > limit) 607 return new GeneralProtection(0); 608 } 609 } 610 // If paging is enabled, do the translation. 611 if (m5Reg.paging) { 612 DPRINTF(TLB, "Paging enabled.\n"); 613 // The vaddr already has the segment base applied. 614 TlbEntry *entry = lookup(vaddr); 615 if (!entry) { 616#if FULL_SYSTEM 617 Fault fault = walker->start(tc, translation, req, mode); 618 if (timing || fault != NoFault) { 619 // This gets ignored in atomic mode. 620 delayedResponse = true; 621 return fault; 622 } 623 entry = lookup(vaddr); 624 assert(entry); 625#else 626 DPRINTF(TLB, "Handling a TLB miss for " 627 "address %#x at pc %#x.\n", 628 vaddr, tc->readPC()); 629 630 Process *p = tc->getProcessPtr(); 631 TlbEntry newEntry; 632 bool success = p->pTable->lookup(vaddr, newEntry); 633 if(!success && mode != Execute) { 634 p->checkAndAllocNextPage(vaddr); 635 success = p->pTable->lookup(vaddr, newEntry); 636 } 637 if(!success) { 638 panic("Tried to execute unmapped address %#x.\n", vaddr); 639 } else { 640 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 641 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 642 newEntry.pageStart()); 643 entry = insert(alignedVaddr, newEntry); 644 } 645 DPRINTF(TLB, "Miss was serviced.\n"); 646#endif 647 } 648 // Do paging protection checks. 649 bool inUser = (m5Reg.cpl == 3 && 650 !(flags & (CPL0FlagBit << FlagShift))); 651 if ((inUser && !entry->user) || 652 (mode == Write && !entry->writable)) { 653 // The page must have been present to get into the TLB in 654 // the first place. We'll assume the reserved bits are 655 // fine even though we're not checking them. 656 return new PageFault(vaddr, true, mode, inUser, false); 657 } 658 if (storeCheck && !entry->writable) { 659 // This would fault if this were a write, so return a page 660 // fault that reflects that happening. 661 return new PageFault(vaddr, true, Write, inUser, false); 662 } 663 664 665 DPRINTF(TLB, "Entry found with paddr %#x, " 666 "doing protection checks.\n", entry->paddr); 667 Addr paddr = entry->paddr | (vaddr & (entry->size-1)); 668 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 669 req->setPaddr(paddr); 670 } else { 671 //Use the address which already has segmentation applied. 672 DPRINTF(TLB, "Paging disabled.\n"); 673 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 674 req->setPaddr(vaddr); 675 } 676 } else { 677 // Real mode 678 DPRINTF(TLB, "In real mode.\n"); 679 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 680 req->setPaddr(vaddr); 681 } 682 // Check for an access to the local APIC 683#if FULL_SYSTEM 684 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 685 Addr baseAddr = localApicBase.base * PageBytes; 686 Addr paddr = req->getPaddr(); 687 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) { 688 // The Intel developer's manuals say the below restrictions apply, 689 // but the linux kernel, because of a compiler optimization, breaks 690 // them. 691 /* 692 // Check alignment 693 if (paddr & ((32/8) - 1)) 694 return new GeneralProtection(0); 695 // Check access size 696 if (req->getSize() != (32/8)) 697 return new GeneralProtection(0); 698 */ 699 // Force the access to be uncacheable. 700 req->setFlags(Request::UNCACHEABLE); 701 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr)); 702 } 703#endif 704 return NoFault; 705}; 706 707Fault 708TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 709{ 710 bool delayedResponse; 711 return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 712} 713 714void 715TLB::translateTiming(RequestPtr req, ThreadContext *tc, 716 Translation *translation, Mode mode) 717{ 718 bool delayedResponse; 719 assert(translation); 720 Fault fault = 721 TLB::translate(req, tc, translation, mode, delayedResponse, true); 722 if (!delayedResponse) 723 translation->finish(fault, req, tc, mode); 724} 725 726#if FULL_SYSTEM 727 728Tick 729TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 730{ 731 return tc->getCpuPtr()->ticks(1); 732} 733 734Tick 735TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 736{ 737 return tc->getCpuPtr()->ticks(1); 738} 739 740#endif 741 742void 743TLB::serialize(std::ostream &os) 744{ 745} 746 747void 748TLB::unserialize(Checkpoint *cp, const std::string §ion) 749{ 750} 751 752/* end namespace X86ISA */ } 753 754X86ISA::TLB * 755X86TLBParams::create() 756{ 757 return new X86ISA::TLB(this); 758} 759