tlb.cc revision 5357:eecb5fd0be62
1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary 11 * compensation for, or commercial advantage from such use. Illustrative 12 * examples of non-commercial use are academic research, personal study, 13 * teaching, education and corporate research & development. 14 * Illustrative examples of commercial use are distributing products for 15 * commercial advantage and providing services using the software for 16 * commercial advantage. 17 * 18 * If you wish to use this software or functionality therein that may be 19 * covered by patents for commercial use, please contact: 20 * Director of Intellectual Property Licensing 21 * Office of Strategy and Technology 22 * Hewlett-Packard Company 23 * 1501 Page Mill Road 24 * Palo Alto, California 94304 25 * 26 * Redistributions of source code must retain the above copyright notice, 27 * this list of conditions and the following disclaimer. Redistributions 28 * in binary form must reproduce the above copyright notice, this list of 29 * conditions and the following disclaimer in the documentation and/or 30 * other materials provided with the distribution. Neither the name of 31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 32 * contributors may be used to endorse or promote products derived from 33 * this software without specific prior written permission. No right of 34 * sublicense is granted herewith. Derivatives of the software and 35 * output created using the software may be prepared, but only for 36 * Non-Commercial Uses. Derivatives of the software may be shared with 37 * others provided: (i) the others agree to abide by the list of 38 * conditions herein which includes the Non-Commercial Use restrictions; 39 * and (ii) such Derivatives of the software include the above copyright 40 * notice to acknowledge the contribution from this software where 41 * applicable, this list of conditions and the disclaimer below. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#include <cstring> 59 60#include "config/full_system.hh" 61 62#include "arch/x86/pagetable.hh" 63#include "arch/x86/tlb.hh" 64#include "arch/x86/x86_traits.hh" 65#include "base/bitfield.hh" 66#include "base/trace.hh" 67#include "config/full_system.hh" 68#include "cpu/thread_context.hh" 69#include "cpu/base.hh" 70#include "mem/packet_access.hh" 71#include "mem/request.hh" 72 73#if FULL_SYSTEM 74#include "arch/x86/pagetable_walker.hh" 75#endif 76 77namespace X86ISA { 78 79TLB::TLB(const Params *p) : SimObject(p), configAddress(0), size(p->size) 80{ 81 tlb = new TlbEntry[size]; 82 std::memset(tlb, 0, sizeof(TlbEntry) * size); 83 84 for (int x = 0; x < size; x++) 85 freeList.push_back(&tlb[x]); 86 87#if FULL_SYSTEM 88 walker = p->walker; 89 walker->setTLB(this); 90#endif 91} 92 93void 94TLB::insert(Addr vpn, TlbEntry &entry) 95{ 96 //TODO Deal with conflicting entries 97 98 TlbEntry *newEntry = NULL; 99 if (!freeList.empty()) { 100 newEntry = freeList.front(); 101 freeList.pop_front(); 102 } else { 103 newEntry = entryList.back(); 104 entryList.pop_back(); 105 } 106 *newEntry = entry; 107 newEntry->vaddr = vpn; 108 entryList.push_front(newEntry); 109} 110 111TlbEntry * 112TLB::lookup(Addr va, bool update_lru) 113{ 114 //TODO make this smarter at some point 115 EntryList::iterator entry; 116 for (entry = entryList.begin(); entry != entryList.end(); entry++) { 117 if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) { 118 DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x " 119 "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size); 120 TlbEntry *e = *entry; 121 if (update_lru) { 122 entryList.erase(entry); 123 entryList.push_front(e); 124 } 125 return e; 126 } 127 } 128 return NULL; 129} 130 131#if FULL_SYSTEM 132void 133TLB::walk(ThreadContext * _tc, Addr vaddr) 134{ 135 walker->start(_tc, vaddr); 136} 137#endif 138 139void 140TLB::invalidateAll() 141{ 142 DPRINTF(TLB, "Invalidating all entries.\n"); 143 while (!entryList.empty()) { 144 TlbEntry *entry = entryList.front(); 145 entryList.pop_front(); 146 freeList.push_back(entry); 147 } 148} 149 150void 151TLB::setConfigAddress(uint32_t addr) 152{ 153 configAddress = addr; 154} 155 156void 157TLB::invalidateNonGlobal() 158{ 159 DPRINTF(TLB, "Invalidating all non global entries.\n"); 160 EntryList::iterator entryIt; 161 for (entryIt = entryList.begin(); entryIt != entryList.end();) { 162 if (!(*entryIt)->global) { 163 freeList.push_back(*entryIt); 164 entryList.erase(entryIt++); 165 } else { 166 entryIt++; 167 } 168 } 169} 170 171void 172TLB::demapPage(Addr va) 173{ 174} 175 176template<class TlbFault> 177Fault 178TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute) 179{ 180 Addr vaddr = req->getVaddr(); 181 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 182 uint32_t flags = req->getFlags(); 183 bool storeCheck = flags & StoreCheck; 184 185 int seg = flags & mask(4); 186 187 //XXX Junk code to surpress the warning 188 if (storeCheck); 189 190 // If this is true, we're dealing with a request to read an internal 191 // value. 192 if (seg == SEGMENT_REG_MS) { 193 DPRINTF(TLB, "Addresses references internal memory.\n"); 194 Addr prefix = vaddr & IntAddrPrefixMask; 195 if (prefix == IntAddrPrefixCPUID) { 196 panic("CPUID memory space not yet implemented!\n"); 197 } else if (prefix == IntAddrPrefixMSR) { 198 req->setMmapedIpr(true); 199 Addr regNum = 0; 200 switch (vaddr & ~IntAddrPrefixMask) { 201 case 0x10: 202 regNum = MISCREG_TSC; 203 break; 204 case 0xFE: 205 regNum = MISCREG_MTRRCAP; 206 break; 207 case 0x174: 208 regNum = MISCREG_SYSENTER_CS; 209 break; 210 case 0x175: 211 regNum = MISCREG_SYSENTER_ESP; 212 break; 213 case 0x176: 214 regNum = MISCREG_SYSENTER_EIP; 215 break; 216 case 0x179: 217 regNum = MISCREG_MCG_CAP; 218 break; 219 case 0x17A: 220 regNum = MISCREG_MCG_STATUS; 221 break; 222 case 0x17B: 223 regNum = MISCREG_MCG_CTL; 224 break; 225 case 0x1D9: 226 regNum = MISCREG_DEBUG_CTL_MSR; 227 break; 228 case 0x1DB: 229 regNum = MISCREG_LAST_BRANCH_FROM_IP; 230 break; 231 case 0x1DC: 232 regNum = MISCREG_LAST_BRANCH_TO_IP; 233 break; 234 case 0x1DD: 235 regNum = MISCREG_LAST_EXCEPTION_FROM_IP; 236 break; 237 case 0x1DE: 238 regNum = MISCREG_LAST_EXCEPTION_TO_IP; 239 break; 240 case 0x200: 241 regNum = MISCREG_MTRR_PHYS_BASE_0; 242 break; 243 case 0x201: 244 regNum = MISCREG_MTRR_PHYS_MASK_0; 245 break; 246 case 0x202: 247 regNum = MISCREG_MTRR_PHYS_BASE_1; 248 break; 249 case 0x203: 250 regNum = MISCREG_MTRR_PHYS_MASK_1; 251 break; 252 case 0x204: 253 regNum = MISCREG_MTRR_PHYS_BASE_2; 254 break; 255 case 0x205: 256 regNum = MISCREG_MTRR_PHYS_MASK_2; 257 break; 258 case 0x206: 259 regNum = MISCREG_MTRR_PHYS_BASE_3; 260 break; 261 case 0x207: 262 regNum = MISCREG_MTRR_PHYS_MASK_3; 263 break; 264 case 0x208: 265 regNum = MISCREG_MTRR_PHYS_BASE_4; 266 break; 267 case 0x209: 268 regNum = MISCREG_MTRR_PHYS_MASK_4; 269 break; 270 case 0x20A: 271 regNum = MISCREG_MTRR_PHYS_BASE_5; 272 break; 273 case 0x20B: 274 regNum = MISCREG_MTRR_PHYS_MASK_5; 275 break; 276 case 0x20C: 277 regNum = MISCREG_MTRR_PHYS_BASE_6; 278 break; 279 case 0x20D: 280 regNum = MISCREG_MTRR_PHYS_MASK_6; 281 break; 282 case 0x20E: 283 regNum = MISCREG_MTRR_PHYS_BASE_7; 284 break; 285 case 0x20F: 286 regNum = MISCREG_MTRR_PHYS_MASK_7; 287 break; 288 case 0x250: 289 regNum = MISCREG_MTRR_FIX_64K_00000; 290 break; 291 case 0x258: 292 regNum = MISCREG_MTRR_FIX_16K_80000; 293 break; 294 case 0x259: 295 regNum = MISCREG_MTRR_FIX_16K_A0000; 296 break; 297 case 0x268: 298 regNum = MISCREG_MTRR_FIX_4K_C0000; 299 break; 300 case 0x269: 301 regNum = MISCREG_MTRR_FIX_4K_C8000; 302 break; 303 case 0x26A: 304 regNum = MISCREG_MTRR_FIX_4K_D0000; 305 break; 306 case 0x26B: 307 regNum = MISCREG_MTRR_FIX_4K_D8000; 308 break; 309 case 0x26C: 310 regNum = MISCREG_MTRR_FIX_4K_E0000; 311 break; 312 case 0x26D: 313 regNum = MISCREG_MTRR_FIX_4K_E8000; 314 break; 315 case 0x26E: 316 regNum = MISCREG_MTRR_FIX_4K_F0000; 317 break; 318 case 0x26F: 319 regNum = MISCREG_MTRR_FIX_4K_F8000; 320 break; 321 case 0x277: 322 regNum = MISCREG_PAT; 323 break; 324 case 0x2FF: 325 regNum = MISCREG_DEF_TYPE; 326 break; 327 case 0x400: 328 regNum = MISCREG_MC0_CTL; 329 break; 330 case 0x404: 331 regNum = MISCREG_MC1_CTL; 332 break; 333 case 0x408: 334 regNum = MISCREG_MC2_CTL; 335 break; 336 case 0x40C: 337 regNum = MISCREG_MC3_CTL; 338 break; 339 case 0x410: 340 regNum = MISCREG_MC4_CTL; 341 break; 342 case 0x401: 343 regNum = MISCREG_MC0_STATUS; 344 break; 345 case 0x405: 346 regNum = MISCREG_MC1_STATUS; 347 break; 348 case 0x409: 349 regNum = MISCREG_MC2_STATUS; 350 break; 351 case 0x40D: 352 regNum = MISCREG_MC3_STATUS; 353 break; 354 case 0x411: 355 regNum = MISCREG_MC4_STATUS; 356 break; 357 case 0x402: 358 regNum = MISCREG_MC0_ADDR; 359 break; 360 case 0x406: 361 regNum = MISCREG_MC1_ADDR; 362 break; 363 case 0x40A: 364 regNum = MISCREG_MC2_ADDR; 365 break; 366 case 0x40E: 367 regNum = MISCREG_MC3_ADDR; 368 break; 369 case 0x412: 370 regNum = MISCREG_MC4_ADDR; 371 break; 372 case 0x403: 373 regNum = MISCREG_MC0_MISC; 374 break; 375 case 0x407: 376 regNum = MISCREG_MC1_MISC; 377 break; 378 case 0x40B: 379 regNum = MISCREG_MC2_MISC; 380 break; 381 case 0x40F: 382 regNum = MISCREG_MC3_MISC; 383 break; 384 case 0x413: 385 regNum = MISCREG_MC4_MISC; 386 break; 387 case 0xC0000080: 388 regNum = MISCREG_EFER; 389 break; 390 case 0xC0000081: 391 regNum = MISCREG_STAR; 392 break; 393 case 0xC0000082: 394 regNum = MISCREG_LSTAR; 395 break; 396 case 0xC0000083: 397 regNum = MISCREG_CSTAR; 398 break; 399 case 0xC0000084: 400 regNum = MISCREG_SF_MASK; 401 break; 402 case 0xC0000100: 403 regNum = MISCREG_FS_BASE; 404 break; 405 case 0xC0000101: 406 regNum = MISCREG_GS_BASE; 407 break; 408 case 0xC0000102: 409 regNum = MISCREG_KERNEL_GS_BASE; 410 break; 411 case 0xC0000103: 412 regNum = MISCREG_TSC_AUX; 413 break; 414 case 0xC0010000: 415 regNum = MISCREG_PERF_EVT_SEL0; 416 break; 417 case 0xC0010001: 418 regNum = MISCREG_PERF_EVT_SEL1; 419 break; 420 case 0xC0010002: 421 regNum = MISCREG_PERF_EVT_SEL2; 422 break; 423 case 0xC0010003: 424 regNum = MISCREG_PERF_EVT_SEL3; 425 break; 426 case 0xC0010004: 427 regNum = MISCREG_PERF_EVT_CTR0; 428 break; 429 case 0xC0010005: 430 regNum = MISCREG_PERF_EVT_CTR1; 431 break; 432 case 0xC0010006: 433 regNum = MISCREG_PERF_EVT_CTR2; 434 break; 435 case 0xC0010007: 436 regNum = MISCREG_PERF_EVT_CTR3; 437 break; 438 case 0xC0010010: 439 regNum = MISCREG_SYSCFG; 440 break; 441 case 0xC0010016: 442 regNum = MISCREG_IORR_BASE0; 443 break; 444 case 0xC0010017: 445 regNum = MISCREG_IORR_BASE1; 446 break; 447 case 0xC0010018: 448 regNum = MISCREG_IORR_MASK0; 449 break; 450 case 0xC0010019: 451 regNum = MISCREG_IORR_MASK1; 452 break; 453 case 0xC001001A: 454 regNum = MISCREG_TOP_MEM; 455 break; 456 case 0xC001001D: 457 regNum = MISCREG_TOP_MEM2; 458 break; 459 case 0xC0010114: 460 regNum = MISCREG_VM_CR; 461 break; 462 case 0xC0010115: 463 regNum = MISCREG_IGNNE; 464 break; 465 case 0xC0010116: 466 regNum = MISCREG_SMM_CTL; 467 break; 468 case 0xC0010117: 469 regNum = MISCREG_VM_HSAVE_PA; 470 break; 471 default: 472 return new GeneralProtection(0); 473 } 474 //The index is multiplied by the size of a MiscReg so that 475 //any memory dependence calculations will not see these as 476 //overlapping. 477 req->setPaddr(regNum * sizeof(MiscReg)); 478 return NoFault; 479 } else if (prefix == IntAddrPrefixIO) { 480 // TODO If CPL > IOPL or in virtual mode, check the I/O permission 481 // bitmap in the TSS. 482 483 Addr IOPort = vaddr & ~IntAddrPrefixMask; 484 // Make sure the address fits in the expected 16 bit IO address 485 // space. 486 assert(!(IOPort & ~0xFFFF)); 487 if (IOPort == 0xCF8 && req->getSize() == 4) { 488 req->setMmapedIpr(true); 489 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 490 } else if ((IOPort & ~mask(2)) == 0xCFC) { 491 Addr configAddress = 492 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 493 if (bits(configAddress, 31, 31)) { 494 req->setPaddr(PhysAddrPrefixPciConfig | 495 bits(configAddress, 30, 0)); 496 } 497 } else { 498 req->setPaddr(PhysAddrPrefixIO | IOPort); 499 } 500 return NoFault; 501 } else { 502 panic("Access to unrecognized internal address space %#x.\n", 503 prefix); 504 } 505 } 506 507 // Get cr0. This will tell us how to do translation. We'll assume it was 508 // verified to be correct and consistent when set. 509 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 510 511 // If protected mode has been enabled... 512 if (cr0.pe) { 513 DPRINTF(TLB, "In protected mode.\n"); 514 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 515 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR); 516 // If we're not in 64-bit mode, do protection/limit checks 517 if (!efer.lma || !csAttr.longMode) { 518 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 519 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 520 if (!attr.writable && write) 521 return new GeneralProtection(0); 522 if (!attr.readable && !write && !execute) 523 return new GeneralProtection(0); 524 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 525 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 526 if (!attr.expandDown) { 527 DPRINTF(TLB, "Checking an expand down segment.\n"); 528 // We don't have to worry about the access going around the 529 // end of memory because accesses will be broken up into 530 // pieces at boundaries aligned on sizes smaller than an 531 // entire address space. We do have to worry about the limit 532 // being less than the base. 533 if (limit < base) { 534 if (limit < vaddr + req->getSize() && vaddr < base) 535 return new GeneralProtection(0); 536 } else { 537 if (limit < vaddr + req->getSize()) 538 return new GeneralProtection(0); 539 } 540 } else { 541 if (limit < base) { 542 if (vaddr <= limit || vaddr + req->getSize() >= base) 543 return new GeneralProtection(0); 544 } else { 545 if (vaddr <= limit && vaddr + req->getSize() >= base) 546 return new GeneralProtection(0); 547 } 548 } 549 } 550 // If paging is enabled, do the translation. 551 if (cr0.pg) { 552 DPRINTF(TLB, "Paging enabled.\n"); 553 // The vaddr already has the segment base applied. 554 TlbEntry *entry = lookup(vaddr); 555 if (!entry) { 556 return new TlbFault(vaddr); 557 } else { 558 // Do paging protection checks. 559 DPRINTF(TLB, "Entry found with paddr %#x, doing protection checks.\n", entry->paddr); 560 Addr paddr = entry->paddr | (vaddr & (entry->size-1)); 561 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 562 req->setPaddr(paddr); 563 } 564 } else { 565 //Use the address which already has segmentation applied. 566 DPRINTF(TLB, "Paging disabled.\n"); 567 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 568 req->setPaddr(vaddr); 569 } 570 } else { 571 // Real mode 572 DPRINTF(TLB, "In real mode.\n"); 573 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 574 req->setPaddr(vaddr); 575 } 576 return NoFault; 577}; 578 579Fault 580DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 581{ 582 return TLB::translate<FakeDTLBFault>(req, tc, write, false); 583} 584 585Fault 586ITB::translate(RequestPtr &req, ThreadContext *tc) 587{ 588 return TLB::translate<FakeITLBFault>(req, tc, false, true); 589} 590 591#if FULL_SYSTEM 592 593Tick 594DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 595{ 596 return tc->getCpuPtr()->ticks(1); 597} 598 599Tick 600DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 601{ 602 return tc->getCpuPtr()->ticks(1); 603} 604 605#endif 606 607void 608TLB::serialize(std::ostream &os) 609{ 610} 611 612void 613TLB::unserialize(Checkpoint *cp, const std::string §ion) 614{ 615} 616 617void 618DTB::serialize(std::ostream &os) 619{ 620 TLB::serialize(os); 621} 622 623void 624DTB::unserialize(Checkpoint *cp, const std::string §ion) 625{ 626 TLB::unserialize(cp, section); 627} 628 629/* end namespace X86ISA */ } 630 631X86ISA::ITB * 632X86ITBParams::create() 633{ 634 return new X86ISA::ITB(this); 635} 636 637X86ISA::DTB * 638X86DTBParams::create() 639{ 640 return new X86ISA::DTB(this); 641} 642