tlb.cc revision 5140:2fd7f8477b4c 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
21 *     Office of Strategy and Technology
22 *     Hewlett-Packard Company
23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution.  Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include <cstring>
59
60#include "config/full_system.hh"
61
62#include "arch/x86/pagetable.hh"
63#include "arch/x86/tlb.hh"
64#include "base/bitfield.hh"
65#include "base/trace.hh"
66#include "cpu/thread_context.hh"
67#include "cpu/base.hh"
68#include "mem/packet_access.hh"
69#include "mem/request.hh"
70#include "sim/system.hh"
71
72namespace X86ISA {
73
74TLB::TLB(const Params *p) : SimObject(p), size(p->size)
75{
76    tlb = new TlbEntry[size];
77    std::memset(tlb, 0, sizeof(TlbEntry) * size);
78
79    for (int x = 0; x < size; x++)
80        freeList.push_back(&tlb[x]);
81}
82
83void
84TLB::insert(Addr vpn, TlbEntry &entry)
85{
86    //TODO Deal with conflicting entries
87
88    TlbEntry *newEntry = NULL;
89    if (!freeList.empty()) {
90        newEntry = freeList.front();
91        freeList.pop_front();
92    } else {
93        newEntry = entryList.back();
94        entryList.pop_back();
95    }
96    *newEntry = entry;
97    newEntry->vaddr = vpn;
98    entryList.push_front(newEntry);
99}
100
101TlbEntry *
102TLB::lookup(Addr va, bool update_lru)
103{
104    //TODO make this smarter at some point
105    EntryList::iterator entry;
106    for (entry = entryList.begin(); entry != entryList.end(); entry++) {
107        if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
108            DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
109                    "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
110            TlbEntry *e = *entry;
111            if (update_lru) {
112                entryList.erase(entry);
113                entryList.push_front(e);
114            }
115            return e;
116        }
117    }
118    return NULL;
119}
120
121void
122TLB::invalidateAll()
123{
124}
125
126void
127TLB::invalidateNonGlobal()
128{
129}
130
131void
132TLB::demapPage(Addr va)
133{
134}
135
136template<class TlbFault>
137Fault
138TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
139{
140    Addr vaddr = req->getVaddr();
141    DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
142    uint32_t flags = req->getFlags();
143    bool storeCheck = flags & StoreCheck;
144
145    int seg = flags & (mask(NUM_SEGMENTREGS));
146
147    //XXX Junk code to surpress the warning
148    if (storeCheck) seg = seg;
149
150    // Get cr0. This will tell us how to do translation. We'll assume it was
151    // verified to be correct and consistent when set.
152    CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
153
154    // If protected mode has been enabled...
155    if (cr0.pe) {
156        Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
157        SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
158        // If we're not in 64-bit mode, do protection/limit checks
159        if (!efer.lma || !csAttr.longMode) {
160            SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
161            if (!attr.writable && write)
162                return new GeneralProtection(0);
163            if (!attr.readable && !write && !execute)
164                return new GeneralProtection(0);
165            Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
166            Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
167            if (!attr.expandDown) {
168                // We don't have to worry about the access going around the
169                // end of memory because accesses will be broken up into
170                // pieces at boundaries aligned on sizes smaller than an
171                // entire address space. We do have to worry about the limit
172                // being less than the base.
173                if (limit < base) {
174                    if (limit < vaddr + req->getSize() && vaddr < base)
175                        return new GeneralProtection(0);
176                } else {
177                    if (limit < vaddr + req->getSize())
178                        return new GeneralProtection(0);
179                }
180            } else {
181                if (limit < base) {
182                    if (vaddr <= limit || vaddr + req->getSize() >= base)
183                        return new GeneralProtection(0);
184                } else {
185                    if (vaddr <= limit && vaddr + req->getSize() >= base)
186                        return new GeneralProtection(0);
187                }
188            }
189        }
190        // If paging is enabled, do the translation.
191        if (cr0.pg) {
192            // The vaddr already has the segment base applied.
193            TlbEntry *entry = lookup(vaddr);
194            if (!entry) {
195#if FULL_SYSTEM
196                return new TlbFault();
197#else
198                return new TlbFault(vaddr);
199#endif
200            } else {
201                // Do paging protection checks.
202                Addr paddr = entry->pageStart | (vaddr & mask(12));
203                req->setPaddr(paddr);
204            }
205        } else {
206            //Use the address which already has segmentation applied.
207            req->setPaddr(vaddr);
208        }
209    } else {
210        // Real mode
211        req->setPaddr(vaddr);
212    }
213    return NoFault;
214};
215
216Fault
217DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
218{
219    return TLB::translate<FakeDTLBFault>(req, tc, write, false);
220}
221
222Fault
223ITB::translate(RequestPtr &req, ThreadContext *tc)
224{
225    return TLB::translate<FakeITLBFault>(req, tc, false, true);
226}
227
228#if FULL_SYSTEM
229
230Tick
231DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
232{
233    return tc->getCpuPtr()->ticks(1);
234}
235
236Tick
237DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
238{
239    return tc->getCpuPtr()->ticks(1);
240}
241
242#endif
243
244void
245TLB::serialize(std::ostream &os)
246{
247}
248
249void
250TLB::unserialize(Checkpoint *cp, const std::string &section)
251{
252}
253
254void
255DTB::serialize(std::ostream &os)
256{
257    TLB::serialize(os);
258}
259
260void
261DTB::unserialize(Checkpoint *cp, const std::string &section)
262{
263    TLB::unserialize(cp, section);
264}
265
266/* end namespace X86ISA */ }
267
268X86ISA::ITB *
269X86ITBParams::create()
270{
271    return new X86ISA::ITB(this);
272}
273
274X86ISA::DTB *
275X86DTBParams::create()
276{
277    return new X86ISA::DTB(this);
278}
279