tlb.cc revision 11800:54436a1784dc
1/* 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#include "arch/x86/tlb.hh" 41 42#include <cstring> 43#include <memory> 44 45#include "arch/generic/mmapped_ipr.hh" 46#include "arch/x86/faults.hh" 47#include "arch/x86/insts/microldstop.hh" 48#include "arch/x86/pagetable_walker.hh" 49#include "arch/x86/regs/misc.hh" 50#include "arch/x86/regs/msr.hh" 51#include "arch/x86/x86_traits.hh" 52#include "base/trace.hh" 53#include "cpu/thread_context.hh" 54#include "debug/TLB.hh" 55#include "mem/page_table.hh" 56#include "mem/request.hh" 57#include "sim/full_system.hh" 58#include "sim/process.hh" 59 60namespace X86ISA { 61 62TLB::TLB(const Params *p) 63 : BaseTLB(p), configAddress(0), size(p->size), 64 tlb(size), lruSeq(0) 65{ 66 if (!size) 67 fatal("TLBs must have a non-zero size.\n"); 68 69 for (int x = 0; x < size; x++) { 70 tlb[x].trieHandle = NULL; 71 freeList.push_back(&tlb[x]); 72 } 73 74 walker = p->walker; 75 walker->setTLB(this); 76} 77 78void 79TLB::evictLRU() 80{ 81 // Find the entry with the lowest (and hence least recently updated) 82 // sequence number. 83 84 unsigned lru = 0; 85 for (unsigned i = 1; i < size; i++) { 86 if (tlb[i].lruSeq < tlb[lru].lruSeq) 87 lru = i; 88 } 89 90 assert(tlb[lru].trieHandle); 91 trie.remove(tlb[lru].trieHandle); 92 tlb[lru].trieHandle = NULL; 93 freeList.push_back(&tlb[lru]); 94} 95 96TlbEntry * 97TLB::insert(Addr vpn, TlbEntry &entry) 98{ 99 // If somebody beat us to it, just use that existing entry. 100 TlbEntry *newEntry = trie.lookup(vpn); 101 if (newEntry) { 102 assert(newEntry->vaddr == vpn); 103 return newEntry; 104 } 105 106 if (freeList.empty()) 107 evictLRU(); 108 109 newEntry = freeList.front(); 110 freeList.pop_front(); 111 112 *newEntry = entry; 113 newEntry->lruSeq = nextSeq(); 114 newEntry->vaddr = vpn; 115 newEntry->trieHandle = 116 trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry); 117 return newEntry; 118} 119 120TlbEntry * 121TLB::lookup(Addr va, bool update_lru) 122{ 123 TlbEntry *entry = trie.lookup(va); 124 if (entry && update_lru) 125 entry->lruSeq = nextSeq(); 126 return entry; 127} 128 129void 130TLB::flushAll() 131{ 132 DPRINTF(TLB, "Invalidating all entries.\n"); 133 for (unsigned i = 0; i < size; i++) { 134 if (tlb[i].trieHandle) { 135 trie.remove(tlb[i].trieHandle); 136 tlb[i].trieHandle = NULL; 137 freeList.push_back(&tlb[i]); 138 } 139 } 140} 141 142void 143TLB::setConfigAddress(uint32_t addr) 144{ 145 configAddress = addr; 146} 147 148void 149TLB::flushNonGlobal() 150{ 151 DPRINTF(TLB, "Invalidating all non global entries.\n"); 152 for (unsigned i = 0; i < size; i++) { 153 if (tlb[i].trieHandle && !tlb[i].global) { 154 trie.remove(tlb[i].trieHandle); 155 tlb[i].trieHandle = NULL; 156 freeList.push_back(&tlb[i]); 157 } 158 } 159} 160 161void 162TLB::demapPage(Addr va, uint64_t asn) 163{ 164 TlbEntry *entry = trie.lookup(va); 165 if (entry) { 166 trie.remove(entry->trieHandle); 167 entry->trieHandle = NULL; 168 freeList.push_back(entry); 169 } 170} 171 172Fault 173TLB::translateInt(RequestPtr req, ThreadContext *tc) 174{ 175 DPRINTF(TLB, "Addresses references internal memory.\n"); 176 Addr vaddr = req->getVaddr(); 177 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 178 if (prefix == IntAddrPrefixCPUID) { 179 panic("CPUID memory space not yet implemented!\n"); 180 } else if (prefix == IntAddrPrefixMSR) { 181 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask; 182 req->setFlags(Request::MMAPPED_IPR); 183 184 MiscRegIndex regNum; 185 if (!msrAddrToIndex(regNum, vaddr)) 186 return std::make_shared<GeneralProtection>(0); 187 188 //The index is multiplied by the size of a MiscReg so that 189 //any memory dependence calculations will not see these as 190 //overlapping. 191 req->setPaddr((Addr)regNum * sizeof(MiscReg)); 192 return NoFault; 193 } else if (prefix == IntAddrPrefixIO) { 194 // TODO If CPL > IOPL or in virtual mode, check the I/O permission 195 // bitmap in the TSS. 196 197 Addr IOPort = vaddr & ~IntAddrPrefixMask; 198 // Make sure the address fits in the expected 16 bit IO address 199 // space. 200 assert(!(IOPort & ~0xFFFF)); 201 if (IOPort == 0xCF8 && req->getSize() == 4) { 202 req->setFlags(Request::MMAPPED_IPR); 203 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 204 } else if ((IOPort & ~mask(2)) == 0xCFC) { 205 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 206 Addr configAddress = 207 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 208 if (bits(configAddress, 31, 31)) { 209 req->setPaddr(PhysAddrPrefixPciConfig | 210 mbits(configAddress, 30, 2) | 211 (IOPort & mask(2))); 212 } else { 213 req->setPaddr(PhysAddrPrefixIO | IOPort); 214 } 215 } else { 216 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 217 req->setPaddr(PhysAddrPrefixIO | IOPort); 218 } 219 return NoFault; 220 } else { 221 panic("Access to unrecognized internal address space %#x.\n", 222 prefix); 223 } 224} 225 226Fault 227TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 228{ 229 Addr paddr = req->getPaddr(); 230 231 AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF); 232 233 if (m5opRange.contains(paddr)) { 234 if (m5opRange.contains(paddr)) { 235 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR | 236 Request::STRICT_ORDER); 237 req->setPaddr(GenericISA::iprAddressPseudoInst( 238 (paddr >> 8) & 0xFF, 239 paddr & 0xFF)); 240 } 241 } else if (FullSystem) { 242 // Check for an access to the local APIC 243 LocalApicBase localApicBase = 244 tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 245 AddrRange apicRange(localApicBase.base * PageBytes, 246 (localApicBase.base + 1) * PageBytes - 1); 247 248 if (apicRange.contains(paddr)) { 249 // The Intel developer's manuals say the below restrictions apply, 250 // but the linux kernel, because of a compiler optimization, breaks 251 // them. 252 /* 253 // Check alignment 254 if (paddr & ((32/8) - 1)) 255 return new GeneralProtection(0); 256 // Check access size 257 if (req->getSize() != (32/8)) 258 return new GeneralProtection(0); 259 */ 260 // Force the access to be uncacheable. 261 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 262 req->setPaddr(x86LocalAPICAddress(tc->contextId(), 263 paddr - apicRange.start())); 264 } 265 } 266 267 return NoFault; 268} 269 270Fault 271TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, 272 Mode mode, bool &delayedResponse, bool timing) 273{ 274 Request::Flags flags = req->getFlags(); 275 int seg = flags & SegmentFlagMask; 276 bool storeCheck = flags & (StoreCheck << FlagShift); 277 278 delayedResponse = false; 279 280 // If this is true, we're dealing with a request to a non-memory address 281 // space. 282 if (seg == SEGMENT_REG_MS) { 283 return translateInt(req, tc); 284 } 285 286 Addr vaddr = req->getVaddr(); 287 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 288 289 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 290 291 // If protected mode has been enabled... 292 if (m5Reg.prot) { 293 DPRINTF(TLB, "In protected mode.\n"); 294 // If we're not in 64-bit mode, do protection/limit checks 295 if (m5Reg.mode != LongMode) { 296 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 297 // Check for a NULL segment selector. 298 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 299 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 300 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 301 return std::make_shared<GeneralProtection>(0); 302 bool expandDown = false; 303 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 304 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 305 if (!attr.writable && (mode == Write || storeCheck)) 306 return std::make_shared<GeneralProtection>(0); 307 if (!attr.readable && mode == Read) 308 return std::make_shared<GeneralProtection>(0); 309 expandDown = attr.expandDown; 310 311 } 312 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 313 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 314 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 315 unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr 316 : (unsigned)m5Reg.defAddr; 317 int size = (1 << logSize) * 8; 318 Addr offset = bits(vaddr - base, size - 1, 0); 319 Addr endOffset = offset + req->getSize() - 1; 320 if (expandDown) { 321 DPRINTF(TLB, "Checking an expand down segment.\n"); 322 warn_once("Expand down segments are untested.\n"); 323 if (offset <= limit || endOffset <= limit) 324 return std::make_shared<GeneralProtection>(0); 325 } else { 326 if (offset > limit || endOffset > limit) 327 return std::make_shared<GeneralProtection>(0); 328 } 329 } 330 if (m5Reg.submode != SixtyFourBitMode || 331 (flags & (AddrSizeFlagBit << FlagShift))) 332 vaddr &= mask(32); 333 // If paging is enabled, do the translation. 334 if (m5Reg.paging) { 335 DPRINTF(TLB, "Paging enabled.\n"); 336 // The vaddr already has the segment base applied. 337 TlbEntry *entry = lookup(vaddr); 338 if (!entry) { 339 if (FullSystem) { 340 Fault fault = walker->start(tc, translation, req, mode); 341 if (timing || fault != NoFault) { 342 // This gets ignored in atomic mode. 343 delayedResponse = true; 344 return fault; 345 } 346 entry = lookup(vaddr); 347 assert(entry); 348 } else { 349 DPRINTF(TLB, "Handling a TLB miss for " 350 "address %#x at pc %#x.\n", 351 vaddr, tc->instAddr()); 352 353 Process *p = tc->getProcessPtr(); 354 TlbEntry newEntry; 355 bool success = p->pTable->lookup(vaddr, newEntry); 356 if (!success && mode != Execute) { 357 // Check if we just need to grow the stack. 358 if (p->fixupStackFault(vaddr)) { 359 // If we did, lookup the entry for the new page. 360 success = p->pTable->lookup(vaddr, newEntry); 361 } 362 } 363 if (!success) { 364 return std::make_shared<PageFault>(vaddr, true, mode, 365 true, false); 366 } else { 367 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 368 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 369 newEntry.pageStart()); 370 entry = insert(alignedVaddr, newEntry); 371 } 372 DPRINTF(TLB, "Miss was serviced.\n"); 373 } 374 } 375 376 DPRINTF(TLB, "Entry found with paddr %#x, " 377 "doing protection checks.\n", entry->paddr); 378 // Do paging protection checks. 379 bool inUser = (m5Reg.cpl == 3 && 380 !(flags & (CPL0FlagBit << FlagShift))); 381 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 382 bool badWrite = (!entry->writable && (inUser || cr0.wp)); 383 if ((inUser && !entry->user) || (mode == Write && badWrite)) { 384 // The page must have been present to get into the TLB in 385 // the first place. We'll assume the reserved bits are 386 // fine even though we're not checking them. 387 return std::make_shared<PageFault>(vaddr, true, mode, inUser, 388 false); 389 } 390 if (storeCheck && badWrite) { 391 // This would fault if this were a write, so return a page 392 // fault that reflects that happening. 393 return std::make_shared<PageFault>(vaddr, true, Write, inUser, 394 false); 395 } 396 397 Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes)); 398 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 399 req->setPaddr(paddr); 400 if (entry->uncacheable) 401 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 402 } else { 403 //Use the address which already has segmentation applied. 404 DPRINTF(TLB, "Paging disabled.\n"); 405 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 406 req->setPaddr(vaddr); 407 } 408 } else { 409 // Real mode 410 DPRINTF(TLB, "In real mode.\n"); 411 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 412 req->setPaddr(vaddr); 413 } 414 415 return finalizePhysical(req, tc, mode); 416} 417 418Fault 419TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 420{ 421 bool delayedResponse; 422 return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 423} 424 425void 426TLB::translateTiming(RequestPtr req, ThreadContext *tc, 427 Translation *translation, Mode mode) 428{ 429 bool delayedResponse; 430 assert(translation); 431 Fault fault = 432 TLB::translate(req, tc, translation, mode, delayedResponse, true); 433 if (!delayedResponse) 434 translation->finish(fault, req, tc, mode); 435} 436 437Fault 438TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 439{ 440 panic("Not implemented\n"); 441 return NoFault; 442} 443 444Walker * 445TLB::getWalker() 446{ 447 return walker; 448} 449 450void 451TLB::serialize(CheckpointOut &cp) const 452{ 453 // Only store the entries in use. 454 uint32_t _size = size - freeList.size(); 455 SERIALIZE_SCALAR(_size); 456 SERIALIZE_SCALAR(lruSeq); 457 458 uint32_t _count = 0; 459 for (uint32_t x = 0; x < size; x++) { 460 if (tlb[x].trieHandle != NULL) 461 tlb[x].serializeSection(cp, csprintf("Entry%d", _count++)); 462 } 463} 464 465void 466TLB::unserialize(CheckpointIn &cp) 467{ 468 // Do not allow to restore with a smaller tlb. 469 uint32_t _size; 470 UNSERIALIZE_SCALAR(_size); 471 if (_size > size) { 472 fatal("TLB size less than the one in checkpoint!"); 473 } 474 475 UNSERIALIZE_SCALAR(lruSeq); 476 477 for (uint32_t x = 0; x < _size; x++) { 478 TlbEntry *newEntry = freeList.front(); 479 freeList.pop_front(); 480 481 newEntry->unserializeSection(cp, csprintf("Entry%d", x)); 482 newEntry->trieHandle = trie.insert(newEntry->vaddr, 483 TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry); 484 } 485} 486 487BaseMasterPort * 488TLB::getMasterPort() 489{ 490 return &walker->getMasterPort("port"); 491} 492 493} // namespace X86ISA 494 495X86ISA::TLB * 496X86TLBParams::create() 497{ 498 return new X86ISA::TLB(this); 499} 500