tlb.cc revision 9818
14997Sgblack@eecs.umich.edu/* 25417Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 34997Sgblack@eecs.umich.edu * All rights reserved. 44997Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 134997Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 157087Snate@binkert.org * modification, are permitted provided that the following conditions are 167087Snate@binkert.org * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 224997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 244997Sgblack@eecs.umich.edu * 254997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 264997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 274997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 284997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 294997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 304997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 314997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 334997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 354997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 364997Sgblack@eecs.umich.edu * 374997Sgblack@eecs.umich.edu * Authors: Gabe Black 384997Sgblack@eecs.umich.edu */ 394997Sgblack@eecs.umich.edu 404997Sgblack@eecs.umich.edu#include <cstring> 414997Sgblack@eecs.umich.edu 428229Snate@binkert.org#include "arch/x86/insts/microldstop.hh" 438229Snate@binkert.org#include "arch/x86/regs/misc.hh" 448582Sgblack@eecs.umich.edu#include "arch/x86/regs/msr.hh" 456315Sgblack@eecs.umich.edu#include "arch/x86/faults.hh" 465124Sgblack@eecs.umich.edu#include "arch/x86/pagetable.hh" 478752Sgblack@eecs.umich.edu#include "arch/x86/pagetable_walker.hh" 485086Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh" 495149Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 505086Sgblack@eecs.umich.edu#include "base/bitfield.hh" 515086Sgblack@eecs.umich.edu#include "base/trace.hh" 528229Snate@binkert.org#include "cpu/base.hh" 535086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 548232Snate@binkert.org#include "debug/TLB.hh" 555086Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 568767Sgblack@eecs.umich.edu#include "mem/page_table.hh" 575086Sgblack@eecs.umich.edu#include "mem/request.hh" 588767Sgblack@eecs.umich.edu#include "sim/full_system.hh" 595895Sgblack@eecs.umich.edu#include "sim/process.hh" 605086Sgblack@eecs.umich.edu 615086Sgblack@eecs.umich.edunamespace X86ISA { 625086Sgblack@eecs.umich.edu 638953Sgblack@eecs.umich.eduTLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size), 648953Sgblack@eecs.umich.edu lruSeq(0) 655124Sgblack@eecs.umich.edu{ 668953Sgblack@eecs.umich.edu if (!size) 678953Sgblack@eecs.umich.edu fatal("TLBs must have a non-zero size.\n"); 685124Sgblack@eecs.umich.edu tlb = new TlbEntry[size]; 695124Sgblack@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 705124Sgblack@eecs.umich.edu 718953Sgblack@eecs.umich.edu for (int x = 0; x < size; x++) { 728953Sgblack@eecs.umich.edu tlb[x].trieHandle = NULL; 735124Sgblack@eecs.umich.edu freeList.push_back(&tlb[x]); 748953Sgblack@eecs.umich.edu } 755124Sgblack@eecs.umich.edu 765245Sgblack@eecs.umich.edu walker = p->walker; 775245Sgblack@eecs.umich.edu walker->setTLB(this); 785236Sgblack@eecs.umich.edu} 795236Sgblack@eecs.umich.edu 808953Sgblack@eecs.umich.eduvoid 818953Sgblack@eecs.umich.eduTLB::evictLRU() 828953Sgblack@eecs.umich.edu{ 838953Sgblack@eecs.umich.edu // Find the entry with the lowest (and hence least recently updated) 848953Sgblack@eecs.umich.edu // sequence number. 858953Sgblack@eecs.umich.edu 868953Sgblack@eecs.umich.edu unsigned lru = 0; 878953Sgblack@eecs.umich.edu for (unsigned i = 1; i < size; i++) { 888953Sgblack@eecs.umich.edu if (tlb[i].lruSeq < tlb[lru].lruSeq) 898953Sgblack@eecs.umich.edu lru = i; 908953Sgblack@eecs.umich.edu } 918953Sgblack@eecs.umich.edu 928953Sgblack@eecs.umich.edu assert(tlb[lru].trieHandle); 938953Sgblack@eecs.umich.edu trie.remove(tlb[lru].trieHandle); 948953Sgblack@eecs.umich.edu tlb[lru].trieHandle = NULL; 958953Sgblack@eecs.umich.edu freeList.push_back(&tlb[lru]); 968953Sgblack@eecs.umich.edu} 978953Sgblack@eecs.umich.edu 985895Sgblack@eecs.umich.eduTlbEntry * 995124Sgblack@eecs.umich.eduTLB::insert(Addr vpn, TlbEntry &entry) 1005124Sgblack@eecs.umich.edu{ 1018962Sgblack@eecs.umich.edu // If somebody beat us to it, just use that existing entry. 1028962Sgblack@eecs.umich.edu TlbEntry *newEntry = trie.lookup(vpn); 1038962Sgblack@eecs.umich.edu if (newEntry) { 1049064Snilay@cs.wisc.edu assert(newEntry->vaddr == vpn); 1058962Sgblack@eecs.umich.edu return newEntry; 1068962Sgblack@eecs.umich.edu } 1075124Sgblack@eecs.umich.edu 1088953Sgblack@eecs.umich.edu if (freeList.empty()) 1098953Sgblack@eecs.umich.edu evictLRU(); 1108962Sgblack@eecs.umich.edu 1118953Sgblack@eecs.umich.edu newEntry = freeList.front(); 1128953Sgblack@eecs.umich.edu freeList.pop_front(); 1138953Sgblack@eecs.umich.edu 1145124Sgblack@eecs.umich.edu *newEntry = entry; 1158953Sgblack@eecs.umich.edu newEntry->lruSeq = nextSeq(); 1165124Sgblack@eecs.umich.edu newEntry->vaddr = vpn; 1178953Sgblack@eecs.umich.edu newEntry->trieHandle = 1188962Sgblack@eecs.umich.edu trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry); 1195895Sgblack@eecs.umich.edu return newEntry; 1205124Sgblack@eecs.umich.edu} 1215124Sgblack@eecs.umich.edu 1225360Sgblack@eecs.umich.eduTlbEntry * 1235360Sgblack@eecs.umich.eduTLB::lookup(Addr va, bool update_lru) 1245360Sgblack@eecs.umich.edu{ 1258953Sgblack@eecs.umich.edu TlbEntry *entry = trie.lookup(va); 1268953Sgblack@eecs.umich.edu if (entry && update_lru) 1278953Sgblack@eecs.umich.edu entry->lruSeq = nextSeq(); 1288953Sgblack@eecs.umich.edu return entry; 1295124Sgblack@eecs.umich.edu} 1305124Sgblack@eecs.umich.edu 1315124Sgblack@eecs.umich.eduvoid 1329423SAndreas.Sandberg@arm.comTLB::flushAll() 1335124Sgblack@eecs.umich.edu{ 1345242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all entries.\n"); 1358953Sgblack@eecs.umich.edu for (unsigned i = 0; i < size; i++) { 1368953Sgblack@eecs.umich.edu if (tlb[i].trieHandle) { 1378953Sgblack@eecs.umich.edu trie.remove(tlb[i].trieHandle); 1388953Sgblack@eecs.umich.edu tlb[i].trieHandle = NULL; 1398953Sgblack@eecs.umich.edu freeList.push_back(&tlb[i]); 1408953Sgblack@eecs.umich.edu } 1415242Sgblack@eecs.umich.edu } 1425124Sgblack@eecs.umich.edu} 1435124Sgblack@eecs.umich.edu 1445124Sgblack@eecs.umich.eduvoid 1455357Sgblack@eecs.umich.eduTLB::setConfigAddress(uint32_t addr) 1465357Sgblack@eecs.umich.edu{ 1475357Sgblack@eecs.umich.edu configAddress = addr; 1485357Sgblack@eecs.umich.edu} 1495357Sgblack@eecs.umich.edu 1505357Sgblack@eecs.umich.eduvoid 1519423SAndreas.Sandberg@arm.comTLB::flushNonGlobal() 1525124Sgblack@eecs.umich.edu{ 1535242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all non global entries.\n"); 1548953Sgblack@eecs.umich.edu for (unsigned i = 0; i < size; i++) { 1558953Sgblack@eecs.umich.edu if (tlb[i].trieHandle && !tlb[i].global) { 1568953Sgblack@eecs.umich.edu trie.remove(tlb[i].trieHandle); 1578953Sgblack@eecs.umich.edu tlb[i].trieHandle = NULL; 1588953Sgblack@eecs.umich.edu freeList.push_back(&tlb[i]); 1595242Sgblack@eecs.umich.edu } 1605242Sgblack@eecs.umich.edu } 1615124Sgblack@eecs.umich.edu} 1625124Sgblack@eecs.umich.edu 1635124Sgblack@eecs.umich.eduvoid 1645358Sgblack@eecs.umich.eduTLB::demapPage(Addr va, uint64_t asn) 1655086Sgblack@eecs.umich.edu{ 1668953Sgblack@eecs.umich.edu TlbEntry *entry = trie.lookup(va); 1678953Sgblack@eecs.umich.edu if (entry) { 1688953Sgblack@eecs.umich.edu trie.remove(entry->trieHandle); 1698953Sgblack@eecs.umich.edu entry->trieHandle = NULL; 1708953Sgblack@eecs.umich.edu freeList.push_back(entry); 1715359Sgblack@eecs.umich.edu } 1725086Sgblack@eecs.umich.edu} 1735086Sgblack@eecs.umich.edu 1745086Sgblack@eecs.umich.eduFault 1756141Sgblack@eecs.umich.eduTLB::translateInt(RequestPtr req, ThreadContext *tc) 1766141Sgblack@eecs.umich.edu{ 1776141Sgblack@eecs.umich.edu DPRINTF(TLB, "Addresses references internal memory.\n"); 1786141Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 1796141Sgblack@eecs.umich.edu Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 1806141Sgblack@eecs.umich.edu if (prefix == IntAddrPrefixCPUID) { 1816141Sgblack@eecs.umich.edu panic("CPUID memory space not yet implemented!\n"); 1826141Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixMSR) { 1838582Sgblack@eecs.umich.edu vaddr = (vaddr >> 3) & ~IntAddrPrefixMask; 1848105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 1858582Sgblack@eecs.umich.edu 1868582Sgblack@eecs.umich.edu MiscRegIndex regNum; 1878582Sgblack@eecs.umich.edu if (!msrAddrToIndex(regNum, vaddr)) 1886141Sgblack@eecs.umich.edu return new GeneralProtection(0); 1898582Sgblack@eecs.umich.edu 1906141Sgblack@eecs.umich.edu //The index is multiplied by the size of a MiscReg so that 1916141Sgblack@eecs.umich.edu //any memory dependence calculations will not see these as 1926141Sgblack@eecs.umich.edu //overlapping. 1938582Sgblack@eecs.umich.edu req->setPaddr((Addr)regNum * sizeof(MiscReg)); 1946141Sgblack@eecs.umich.edu return NoFault; 1956141Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixIO) { 1966141Sgblack@eecs.umich.edu // TODO If CPL > IOPL or in virtual mode, check the I/O permission 1976141Sgblack@eecs.umich.edu // bitmap in the TSS. 1986141Sgblack@eecs.umich.edu 1996141Sgblack@eecs.umich.edu Addr IOPort = vaddr & ~IntAddrPrefixMask; 2006141Sgblack@eecs.umich.edu // Make sure the address fits in the expected 16 bit IO address 2016141Sgblack@eecs.umich.edu // space. 2026141Sgblack@eecs.umich.edu assert(!(IOPort & ~0xFFFF)); 2036141Sgblack@eecs.umich.edu if (IOPort == 0xCF8 && req->getSize() == 4) { 2048105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 2056141Sgblack@eecs.umich.edu req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 2066141Sgblack@eecs.umich.edu } else if ((IOPort & ~mask(2)) == 0xCFC) { 2077774Sgblack@eecs.umich.edu req->setFlags(Request::UNCACHEABLE); 2086141Sgblack@eecs.umich.edu Addr configAddress = 2096141Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 2106141Sgblack@eecs.umich.edu if (bits(configAddress, 31, 31)) { 2116141Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixPciConfig | 2126141Sgblack@eecs.umich.edu mbits(configAddress, 30, 2) | 2136141Sgblack@eecs.umich.edu (IOPort & mask(2))); 2148098Sgblack@eecs.umich.edu } else { 2158098Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 2166141Sgblack@eecs.umich.edu } 2176141Sgblack@eecs.umich.edu } else { 2187774Sgblack@eecs.umich.edu req->setFlags(Request::UNCACHEABLE); 2196141Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 2206141Sgblack@eecs.umich.edu } 2216141Sgblack@eecs.umich.edu return NoFault; 2226141Sgblack@eecs.umich.edu } else { 2236141Sgblack@eecs.umich.edu panic("Access to unrecognized internal address space %#x.\n", 2246141Sgblack@eecs.umich.edu prefix); 2256141Sgblack@eecs.umich.edu } 2266141Sgblack@eecs.umich.edu} 2276141Sgblack@eecs.umich.edu 2286141Sgblack@eecs.umich.eduFault 2299738Sandreas@sandberg.pp.seTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 2309738Sandreas@sandberg.pp.se{ 2319738Sandreas@sandberg.pp.se Addr paddr = req->getPaddr(); 2329738Sandreas@sandberg.pp.se 2339738Sandreas@sandberg.pp.se // Check for an access to the local APIC 2349738Sandreas@sandberg.pp.se if (FullSystem) { 2359738Sandreas@sandberg.pp.se LocalApicBase localApicBase = 2369738Sandreas@sandberg.pp.se tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 2379738Sandreas@sandberg.pp.se AddrRange apicRange(localApicBase.base * PageBytes, 2389738Sandreas@sandberg.pp.se (localApicBase.base + 1) * PageBytes - 1); 2399738Sandreas@sandberg.pp.se 2409738Sandreas@sandberg.pp.se if (apicRange.contains(paddr)) { 2419738Sandreas@sandberg.pp.se // The Intel developer's manuals say the below restrictions apply, 2429738Sandreas@sandberg.pp.se // but the linux kernel, because of a compiler optimization, breaks 2439738Sandreas@sandberg.pp.se // them. 2449738Sandreas@sandberg.pp.se /* 2459738Sandreas@sandberg.pp.se // Check alignment 2469738Sandreas@sandberg.pp.se if (paddr & ((32/8) - 1)) 2479738Sandreas@sandberg.pp.se return new GeneralProtection(0); 2489738Sandreas@sandberg.pp.se // Check access size 2499738Sandreas@sandberg.pp.se if (req->getSize() != (32/8)) 2509738Sandreas@sandberg.pp.se return new GeneralProtection(0); 2519738Sandreas@sandberg.pp.se */ 2529738Sandreas@sandberg.pp.se // Force the access to be uncacheable. 2539738Sandreas@sandberg.pp.se req->setFlags(Request::UNCACHEABLE); 2549738Sandreas@sandberg.pp.se req->setPaddr(x86LocalAPICAddress(tc->contextId(), 2559738Sandreas@sandberg.pp.se paddr - apicRange.start())); 2569738Sandreas@sandberg.pp.se } 2579738Sandreas@sandberg.pp.se } 2589738Sandreas@sandberg.pp.se 2599738Sandreas@sandberg.pp.se return NoFault; 2609738Sandreas@sandberg.pp.se} 2619738Sandreas@sandberg.pp.se 2629738Sandreas@sandberg.pp.seFault 2636023Snate@binkert.orgTLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, 2646023Snate@binkert.org Mode mode, bool &delayedResponse, bool timing) 2655086Sgblack@eecs.umich.edu{ 2666141Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 2676141Sgblack@eecs.umich.edu int seg = flags & SegmentFlagMask; 2686141Sgblack@eecs.umich.edu bool storeCheck = flags & (StoreCheck << FlagShift); 2696141Sgblack@eecs.umich.edu 2708535Sgblack@eecs.umich.edu delayedResponse = false; 2718535Sgblack@eecs.umich.edu 2726141Sgblack@eecs.umich.edu // If this is true, we're dealing with a request to a non-memory address 2736141Sgblack@eecs.umich.edu // space. 2746141Sgblack@eecs.umich.edu if (seg == SEGMENT_REG_MS) { 2756141Sgblack@eecs.umich.edu return translateInt(req, tc); 2766141Sgblack@eecs.umich.edu } 2776141Sgblack@eecs.umich.edu 2785124Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 2795140Sgblack@eecs.umich.edu DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 2805140Sgblack@eecs.umich.edu 2816141Sgblack@eecs.umich.edu HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 2825140Sgblack@eecs.umich.edu 2835140Sgblack@eecs.umich.edu // If protected mode has been enabled... 2846141Sgblack@eecs.umich.edu if (m5Reg.prot) { 2855237Sgblack@eecs.umich.edu DPRINTF(TLB, "In protected mode.\n"); 2865140Sgblack@eecs.umich.edu // If we're not in 64-bit mode, do protection/limit checks 2876141Sgblack@eecs.umich.edu if (m5Reg.mode != LongMode) { 2885237Sgblack@eecs.umich.edu DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 2895431Sgblack@eecs.umich.edu // Check for a NULL segment selector. 2906059Sgblack@eecs.umich.edu if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 2916141Sgblack@eecs.umich.edu seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 2926059Sgblack@eecs.umich.edu && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 2935431Sgblack@eecs.umich.edu return new GeneralProtection(0); 2945433Sgblack@eecs.umich.edu bool expandDown = false; 2955965Sgblack@eecs.umich.edu SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 2965433Sgblack@eecs.umich.edu if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 2976099Sgblack@eecs.umich.edu if (!attr.writable && (mode == Write || storeCheck)) 2985433Sgblack@eecs.umich.edu return new GeneralProtection(0); 2996023Snate@binkert.org if (!attr.readable && mode == Read) 3005433Sgblack@eecs.umich.edu return new GeneralProtection(0); 3015433Sgblack@eecs.umich.edu expandDown = attr.expandDown; 3025965Sgblack@eecs.umich.edu 3035433Sgblack@eecs.umich.edu } 3045140Sgblack@eecs.umich.edu Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 3055140Sgblack@eecs.umich.edu Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 3065965Sgblack@eecs.umich.edu bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 3079062Sjayneel@cs.wisc.edu unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr 3089062Sjayneel@cs.wisc.edu : (unsigned)m5Reg.defAddr; 3099028Sgblack@eecs.umich.edu int size = (1 << logSize) * 8; 3109028Sgblack@eecs.umich.edu Addr offset = bits(vaddr - base, size - 1, 0); 3115965Sgblack@eecs.umich.edu Addr endOffset = offset + req->getSize() - 1; 3125433Sgblack@eecs.umich.edu if (expandDown) { 3135237Sgblack@eecs.umich.edu DPRINTF(TLB, "Checking an expand down segment.\n"); 3145965Sgblack@eecs.umich.edu warn_once("Expand down segments are untested.\n"); 3155965Sgblack@eecs.umich.edu if (offset <= limit || endOffset <= limit) 3165965Sgblack@eecs.umich.edu return new GeneralProtection(0); 3175140Sgblack@eecs.umich.edu } else { 3185965Sgblack@eecs.umich.edu if (offset > limit || endOffset > limit) 3195965Sgblack@eecs.umich.edu return new GeneralProtection(0); 3205140Sgblack@eecs.umich.edu } 3215140Sgblack@eecs.umich.edu } 3229025Sgblack@eecs.umich.edu if (m5Reg.submode != SixtyFourBitMode || 3238925Sgblack@eecs.umich.edu (flags & (AddrSizeFlagBit << FlagShift))) 3248925Sgblack@eecs.umich.edu vaddr &= mask(32); 3255140Sgblack@eecs.umich.edu // If paging is enabled, do the translation. 3266141Sgblack@eecs.umich.edu if (m5Reg.paging) { 3275237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging enabled.\n"); 3285140Sgblack@eecs.umich.edu // The vaddr already has the segment base applied. 3295140Sgblack@eecs.umich.edu TlbEntry *entry = lookup(vaddr); 3305140Sgblack@eecs.umich.edu if (!entry) { 3318752Sgblack@eecs.umich.edu if (FullSystem) { 3328752Sgblack@eecs.umich.edu Fault fault = walker->start(tc, translation, req, mode); 3338752Sgblack@eecs.umich.edu if (timing || fault != NoFault) { 3348752Sgblack@eecs.umich.edu // This gets ignored in atomic mode. 3358752Sgblack@eecs.umich.edu delayedResponse = true; 3368752Sgblack@eecs.umich.edu return fault; 3378752Sgblack@eecs.umich.edu } 3388752Sgblack@eecs.umich.edu entry = lookup(vaddr); 3398752Sgblack@eecs.umich.edu assert(entry); 3408752Sgblack@eecs.umich.edu } else { 3418752Sgblack@eecs.umich.edu DPRINTF(TLB, "Handling a TLB miss for " 3428752Sgblack@eecs.umich.edu "address %#x at pc %#x.\n", 3438752Sgblack@eecs.umich.edu vaddr, tc->instAddr()); 3448752Sgblack@eecs.umich.edu 3458752Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 3468752Sgblack@eecs.umich.edu TlbEntry newEntry; 3478752Sgblack@eecs.umich.edu bool success = p->pTable->lookup(vaddr, newEntry); 3488752Sgblack@eecs.umich.edu if (!success && mode != Execute) { 3498752Sgblack@eecs.umich.edu // Check if we just need to grow the stack. 3508752Sgblack@eecs.umich.edu if (p->fixupStackFault(vaddr)) { 3518752Sgblack@eecs.umich.edu // If we did, lookup the entry for the new page. 3528752Sgblack@eecs.umich.edu success = p->pTable->lookup(vaddr, newEntry); 3538752Sgblack@eecs.umich.edu } 3548752Sgblack@eecs.umich.edu } 3558752Sgblack@eecs.umich.edu if (!success) { 3568752Sgblack@eecs.umich.edu return new PageFault(vaddr, true, mode, true, false); 3578752Sgblack@eecs.umich.edu } else { 3588752Sgblack@eecs.umich.edu Addr alignedVaddr = p->pTable->pageAlign(vaddr); 3598752Sgblack@eecs.umich.edu DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 3608752Sgblack@eecs.umich.edu newEntry.pageStart()); 3618752Sgblack@eecs.umich.edu entry = insert(alignedVaddr, newEntry); 3628752Sgblack@eecs.umich.edu } 3638752Sgblack@eecs.umich.edu DPRINTF(TLB, "Miss was serviced.\n"); 3645895Sgblack@eecs.umich.edu } 3655140Sgblack@eecs.umich.edu } 3668646Snilay@cs.wisc.edu 3678646Snilay@cs.wisc.edu DPRINTF(TLB, "Entry found with paddr %#x, " 3688646Snilay@cs.wisc.edu "doing protection checks.\n", entry->paddr); 3695895Sgblack@eecs.umich.edu // Do paging protection checks. 3706141Sgblack@eecs.umich.edu bool inUser = (m5Reg.cpl == 3 && 3715917Sgblack@eecs.umich.edu !(flags & (CPL0FlagBit << FlagShift))); 3727933Stharris@microsoft.com CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 3737933Stharris@microsoft.com bool badWrite = (!entry->writable && (inUser || cr0.wp)); 3747933Stharris@microsoft.com if ((inUser && !entry->user) || (mode == Write && badWrite)) { 3755917Sgblack@eecs.umich.edu // The page must have been present to get into the TLB in 3765917Sgblack@eecs.umich.edu // the first place. We'll assume the reserved bits are 3775917Sgblack@eecs.umich.edu // fine even though we're not checking them. 3786023Snate@binkert.org return new PageFault(vaddr, true, mode, inUser, false); 3795917Sgblack@eecs.umich.edu } 3807933Stharris@microsoft.com if (storeCheck && badWrite) { 3816099Sgblack@eecs.umich.edu // This would fault if this were a write, so return a page 3826099Sgblack@eecs.umich.edu // fault that reflects that happening. 3836099Sgblack@eecs.umich.edu return new PageFault(vaddr, true, Write, inUser, false); 3846099Sgblack@eecs.umich.edu } 3855917Sgblack@eecs.umich.edu 3868953Sgblack@eecs.umich.edu Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes)); 3875895Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 3885895Sgblack@eecs.umich.edu req->setPaddr(paddr); 3897775Sgblack@eecs.umich.edu if (entry->uncacheable) 3907775Sgblack@eecs.umich.edu req->setFlags(Request::UNCACHEABLE); 3915140Sgblack@eecs.umich.edu } else { 3925140Sgblack@eecs.umich.edu //Use the address which already has segmentation applied. 3935237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging disabled.\n"); 3945237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 3955140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 3965140Sgblack@eecs.umich.edu } 3975124Sgblack@eecs.umich.edu } else { 3985140Sgblack@eecs.umich.edu // Real mode 3995237Sgblack@eecs.umich.edu DPRINTF(TLB, "In real mode.\n"); 4005237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 4015140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 4025124Sgblack@eecs.umich.edu } 4039738Sandreas@sandberg.pp.se 4049738Sandreas@sandberg.pp.se return finalizePhysical(req, tc, mode); 4058902Sandreas.hansson@arm.com} 4065086Sgblack@eecs.umich.edu 4075140Sgblack@eecs.umich.eduFault 4086023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 4095140Sgblack@eecs.umich.edu{ 4105895Sgblack@eecs.umich.edu bool delayedResponse; 4116023Snate@binkert.org return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 4125140Sgblack@eecs.umich.edu} 4135140Sgblack@eecs.umich.edu 4145894Sgblack@eecs.umich.eduvoid 4156022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 4166023Snate@binkert.org Translation *translation, Mode mode) 4175894Sgblack@eecs.umich.edu{ 4185895Sgblack@eecs.umich.edu bool delayedResponse; 4195894Sgblack@eecs.umich.edu assert(translation); 4206023Snate@binkert.org Fault fault = 4216023Snate@binkert.org TLB::translate(req, tc, translation, mode, delayedResponse, true); 4225895Sgblack@eecs.umich.edu if (!delayedResponse) 4236023Snate@binkert.org translation->finish(fault, req, tc, mode); 4245894Sgblack@eecs.umich.edu} 4255894Sgblack@eecs.umich.edu 4268888Sgeoffrey.blake@arm.comFault 4278888Sgeoffrey.blake@arm.comTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 4288888Sgeoffrey.blake@arm.com{ 4298888Sgeoffrey.blake@arm.com panic("Not implemented\n"); 4308888Sgeoffrey.blake@arm.com return NoFault; 4318888Sgeoffrey.blake@arm.com} 4328888Sgeoffrey.blake@arm.com 4337912Shestness@cs.utexas.eduWalker * 4347912Shestness@cs.utexas.eduTLB::getWalker() 4357912Shestness@cs.utexas.edu{ 4367912Shestness@cs.utexas.edu return walker; 4377912Shestness@cs.utexas.edu} 4387912Shestness@cs.utexas.edu 4395086Sgblack@eecs.umich.eduvoid 4405086Sgblack@eecs.umich.eduTLB::serialize(std::ostream &os) 4415086Sgblack@eecs.umich.edu{ 4429818Snilay@cs.wisc.edu // Only store the entries in use. 4439818Snilay@cs.wisc.edu uint32_t _size = size - freeList.size(); 4449818Snilay@cs.wisc.edu SERIALIZE_SCALAR(_size); 4459818Snilay@cs.wisc.edu SERIALIZE_SCALAR(lruSeq); 4469818Snilay@cs.wisc.edu 4479818Snilay@cs.wisc.edu uint32_t _count = 0; 4489818Snilay@cs.wisc.edu 4499818Snilay@cs.wisc.edu for (uint32_t x = 0; x < size; x++) { 4509818Snilay@cs.wisc.edu if (tlb[x].trieHandle != NULL) { 4519818Snilay@cs.wisc.edu os << "\n[" << csprintf("%s.Entry%d", name(), _count) << "]\n"; 4529818Snilay@cs.wisc.edu tlb[x].serialize(os); 4539818Snilay@cs.wisc.edu _count++; 4549818Snilay@cs.wisc.edu } 4559818Snilay@cs.wisc.edu } 4565086Sgblack@eecs.umich.edu} 4575086Sgblack@eecs.umich.edu 4585086Sgblack@eecs.umich.eduvoid 4595086Sgblack@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 4605086Sgblack@eecs.umich.edu{ 4619818Snilay@cs.wisc.edu // Do not allow to restore with a smaller tlb. 4629818Snilay@cs.wisc.edu uint32_t _size; 4639818Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(_size); 4649818Snilay@cs.wisc.edu if (_size > size) { 4659818Snilay@cs.wisc.edu fatal("TLB size less than the one in checkpoint!"); 4669818Snilay@cs.wisc.edu } 4679818Snilay@cs.wisc.edu 4689818Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(lruSeq); 4699818Snilay@cs.wisc.edu 4709818Snilay@cs.wisc.edu for (uint32_t x = 0; x < _size; x++) { 4719818Snilay@cs.wisc.edu TlbEntry *newEntry = freeList.front(); 4729818Snilay@cs.wisc.edu freeList.pop_front(); 4739818Snilay@cs.wisc.edu 4749818Snilay@cs.wisc.edu newEntry->unserialize(cp, csprintf("%s.Entry%d", name(), x)); 4759818Snilay@cs.wisc.edu newEntry->trieHandle = trie.insert(newEntry->vaddr, 4769818Snilay@cs.wisc.edu TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry); 4779818Snilay@cs.wisc.edu } 4785086Sgblack@eecs.umich.edu} 4795086Sgblack@eecs.umich.edu 4809294Sandreas.hansson@arm.comBaseMasterPort * 4818922Swilliam.wang@arm.comTLB::getMasterPort() 4828864Snilay@cs.wisc.edu{ 4838922Swilliam.wang@arm.com return &walker->getMasterPort("port"); 4848864Snilay@cs.wisc.edu} 4858864Snilay@cs.wisc.edu 4867811Ssteve.reinhardt@amd.com} // namespace X86ISA 4875086Sgblack@eecs.umich.edu 4886022Sgblack@eecs.umich.eduX86ISA::TLB * 4896022Sgblack@eecs.umich.eduX86TLBParams::create() 4904997Sgblack@eecs.umich.edu{ 4916022Sgblack@eecs.umich.edu return new X86ISA::TLB(this); 4924997Sgblack@eecs.umich.edu} 493