tlb.cc revision 9423
14997Sgblack@eecs.umich.edu/*
25417Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
34997Sgblack@eecs.umich.edu * All rights reserved.
44997Sgblack@eecs.umich.edu *
57087Snate@binkert.org * The license below extends only to copyright in the software and shall
67087Snate@binkert.org * not be construed as granting a license to any other intellectual
77087Snate@binkert.org * property including but not limited to intellectual property relating
87087Snate@binkert.org * to a hardware implementation of the functionality of the software
97087Snate@binkert.org * licensed hereunder.  You may use the software subject to the license
107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated
117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software,
127087Snate@binkert.org * modified or unmodified, in source code or in binary form.
134997Sgblack@eecs.umich.edu *
147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without
157087Snate@binkert.org * modification, are permitted provided that the following conditions are
167087Snate@binkert.org * met: redistributions of source code must retain the above copyright
177087Snate@binkert.org * notice, this list of conditions and the following disclaimer;
187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright
197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the
207087Snate@binkert.org * documentation and/or other materials provided with the distribution;
217087Snate@binkert.org * neither the name of the copyright holders nor the names of its
224997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
237087Snate@binkert.org * this software without specific prior written permission.
244997Sgblack@eecs.umich.edu *
254997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
264997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
274997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
284997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
294997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
304997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
314997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
324997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
334997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
344997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
354997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
364997Sgblack@eecs.umich.edu *
374997Sgblack@eecs.umich.edu * Authors: Gabe Black
384997Sgblack@eecs.umich.edu */
394997Sgblack@eecs.umich.edu
404997Sgblack@eecs.umich.edu#include <cstring>
414997Sgblack@eecs.umich.edu
428229Snate@binkert.org#include "arch/x86/insts/microldstop.hh"
438229Snate@binkert.org#include "arch/x86/regs/misc.hh"
448582Sgblack@eecs.umich.edu#include "arch/x86/regs/msr.hh"
456315Sgblack@eecs.umich.edu#include "arch/x86/faults.hh"
465124Sgblack@eecs.umich.edu#include "arch/x86/pagetable.hh"
478752Sgblack@eecs.umich.edu#include "arch/x86/pagetable_walker.hh"
485086Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh"
495149Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh"
505086Sgblack@eecs.umich.edu#include "base/bitfield.hh"
515086Sgblack@eecs.umich.edu#include "base/trace.hh"
528229Snate@binkert.org#include "cpu/base.hh"
535086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh"
548232Snate@binkert.org#include "debug/TLB.hh"
555086Sgblack@eecs.umich.edu#include "mem/packet_access.hh"
568767Sgblack@eecs.umich.edu#include "mem/page_table.hh"
575086Sgblack@eecs.umich.edu#include "mem/request.hh"
588767Sgblack@eecs.umich.edu#include "sim/full_system.hh"
595895Sgblack@eecs.umich.edu#include "sim/process.hh"
605086Sgblack@eecs.umich.edu
615086Sgblack@eecs.umich.edunamespace X86ISA {
625086Sgblack@eecs.umich.edu
638953Sgblack@eecs.umich.eduTLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size),
648953Sgblack@eecs.umich.edu    lruSeq(0)
655124Sgblack@eecs.umich.edu{
668953Sgblack@eecs.umich.edu    if (!size)
678953Sgblack@eecs.umich.edu        fatal("TLBs must have a non-zero size.\n");
685124Sgblack@eecs.umich.edu    tlb = new TlbEntry[size];
695124Sgblack@eecs.umich.edu    std::memset(tlb, 0, sizeof(TlbEntry) * size);
705124Sgblack@eecs.umich.edu
718953Sgblack@eecs.umich.edu    for (int x = 0; x < size; x++) {
728953Sgblack@eecs.umich.edu        tlb[x].trieHandle = NULL;
735124Sgblack@eecs.umich.edu        freeList.push_back(&tlb[x]);
748953Sgblack@eecs.umich.edu    }
755124Sgblack@eecs.umich.edu
765245Sgblack@eecs.umich.edu    walker = p->walker;
775245Sgblack@eecs.umich.edu    walker->setTLB(this);
785236Sgblack@eecs.umich.edu}
795236Sgblack@eecs.umich.edu
808953Sgblack@eecs.umich.eduvoid
818953Sgblack@eecs.umich.eduTLB::evictLRU()
828953Sgblack@eecs.umich.edu{
838953Sgblack@eecs.umich.edu    // Find the entry with the lowest (and hence least recently updated)
848953Sgblack@eecs.umich.edu    // sequence number.
858953Sgblack@eecs.umich.edu
868953Sgblack@eecs.umich.edu    unsigned lru = 0;
878953Sgblack@eecs.umich.edu    for (unsigned i = 1; i < size; i++) {
888953Sgblack@eecs.umich.edu        if (tlb[i].lruSeq < tlb[lru].lruSeq)
898953Sgblack@eecs.umich.edu            lru = i;
908953Sgblack@eecs.umich.edu    }
918953Sgblack@eecs.umich.edu
928953Sgblack@eecs.umich.edu    assert(tlb[lru].trieHandle);
938953Sgblack@eecs.umich.edu    trie.remove(tlb[lru].trieHandle);
948953Sgblack@eecs.umich.edu    tlb[lru].trieHandle = NULL;
958953Sgblack@eecs.umich.edu    freeList.push_back(&tlb[lru]);
968953Sgblack@eecs.umich.edu}
978953Sgblack@eecs.umich.edu
985895Sgblack@eecs.umich.eduTlbEntry *
995124Sgblack@eecs.umich.eduTLB::insert(Addr vpn, TlbEntry &entry)
1005124Sgblack@eecs.umich.edu{
1018962Sgblack@eecs.umich.edu    // If somebody beat us to it, just use that existing entry.
1028962Sgblack@eecs.umich.edu    TlbEntry *newEntry = trie.lookup(vpn);
1038962Sgblack@eecs.umich.edu    if (newEntry) {
1049064Snilay@cs.wisc.edu        assert(newEntry->vaddr == vpn);
1058962Sgblack@eecs.umich.edu        return newEntry;
1068962Sgblack@eecs.umich.edu    }
1075124Sgblack@eecs.umich.edu
1088953Sgblack@eecs.umich.edu    if (freeList.empty())
1098953Sgblack@eecs.umich.edu        evictLRU();
1108962Sgblack@eecs.umich.edu
1118953Sgblack@eecs.umich.edu    newEntry = freeList.front();
1128953Sgblack@eecs.umich.edu    freeList.pop_front();
1138953Sgblack@eecs.umich.edu
1145124Sgblack@eecs.umich.edu    *newEntry = entry;
1158953Sgblack@eecs.umich.edu    newEntry->lruSeq = nextSeq();
1165124Sgblack@eecs.umich.edu    newEntry->vaddr = vpn;
1178953Sgblack@eecs.umich.edu    newEntry->trieHandle =
1188962Sgblack@eecs.umich.edu    trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
1195895Sgblack@eecs.umich.edu    return newEntry;
1205124Sgblack@eecs.umich.edu}
1215124Sgblack@eecs.umich.edu
1225360Sgblack@eecs.umich.eduTlbEntry *
1235360Sgblack@eecs.umich.eduTLB::lookup(Addr va, bool update_lru)
1245360Sgblack@eecs.umich.edu{
1258953Sgblack@eecs.umich.edu    TlbEntry *entry = trie.lookup(va);
1268953Sgblack@eecs.umich.edu    if (entry && update_lru)
1278953Sgblack@eecs.umich.edu        entry->lruSeq = nextSeq();
1288953Sgblack@eecs.umich.edu    return entry;
1295124Sgblack@eecs.umich.edu}
1305124Sgblack@eecs.umich.edu
1315124Sgblack@eecs.umich.eduvoid
1329423SAndreas.Sandberg@arm.comTLB::flushAll()
1335124Sgblack@eecs.umich.edu{
1345242Sgblack@eecs.umich.edu    DPRINTF(TLB, "Invalidating all entries.\n");
1358953Sgblack@eecs.umich.edu    for (unsigned i = 0; i < size; i++) {
1368953Sgblack@eecs.umich.edu        if (tlb[i].trieHandle) {
1378953Sgblack@eecs.umich.edu            trie.remove(tlb[i].trieHandle);
1388953Sgblack@eecs.umich.edu            tlb[i].trieHandle = NULL;
1398953Sgblack@eecs.umich.edu            freeList.push_back(&tlb[i]);
1408953Sgblack@eecs.umich.edu        }
1415242Sgblack@eecs.umich.edu    }
1425124Sgblack@eecs.umich.edu}
1435124Sgblack@eecs.umich.edu
1445124Sgblack@eecs.umich.eduvoid
1455357Sgblack@eecs.umich.eduTLB::setConfigAddress(uint32_t addr)
1465357Sgblack@eecs.umich.edu{
1475357Sgblack@eecs.umich.edu    configAddress = addr;
1485357Sgblack@eecs.umich.edu}
1495357Sgblack@eecs.umich.edu
1505357Sgblack@eecs.umich.eduvoid
1519423SAndreas.Sandberg@arm.comTLB::flushNonGlobal()
1525124Sgblack@eecs.umich.edu{
1535242Sgblack@eecs.umich.edu    DPRINTF(TLB, "Invalidating all non global entries.\n");
1548953Sgblack@eecs.umich.edu    for (unsigned i = 0; i < size; i++) {
1558953Sgblack@eecs.umich.edu        if (tlb[i].trieHandle && !tlb[i].global) {
1568953Sgblack@eecs.umich.edu            trie.remove(tlb[i].trieHandle);
1578953Sgblack@eecs.umich.edu            tlb[i].trieHandle = NULL;
1588953Sgblack@eecs.umich.edu            freeList.push_back(&tlb[i]);
1595242Sgblack@eecs.umich.edu        }
1605242Sgblack@eecs.umich.edu    }
1615124Sgblack@eecs.umich.edu}
1625124Sgblack@eecs.umich.edu
1635124Sgblack@eecs.umich.eduvoid
1645358Sgblack@eecs.umich.eduTLB::demapPage(Addr va, uint64_t asn)
1655086Sgblack@eecs.umich.edu{
1668953Sgblack@eecs.umich.edu    TlbEntry *entry = trie.lookup(va);
1678953Sgblack@eecs.umich.edu    if (entry) {
1688953Sgblack@eecs.umich.edu        trie.remove(entry->trieHandle);
1698953Sgblack@eecs.umich.edu        entry->trieHandle = NULL;
1708953Sgblack@eecs.umich.edu        freeList.push_back(entry);
1715359Sgblack@eecs.umich.edu    }
1725086Sgblack@eecs.umich.edu}
1735086Sgblack@eecs.umich.edu
1745086Sgblack@eecs.umich.eduFault
1756141Sgblack@eecs.umich.eduTLB::translateInt(RequestPtr req, ThreadContext *tc)
1766141Sgblack@eecs.umich.edu{
1776141Sgblack@eecs.umich.edu    DPRINTF(TLB, "Addresses references internal memory.\n");
1786141Sgblack@eecs.umich.edu    Addr vaddr = req->getVaddr();
1796141Sgblack@eecs.umich.edu    Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
1806141Sgblack@eecs.umich.edu    if (prefix == IntAddrPrefixCPUID) {
1816141Sgblack@eecs.umich.edu        panic("CPUID memory space not yet implemented!\n");
1826141Sgblack@eecs.umich.edu    } else if (prefix == IntAddrPrefixMSR) {
1838582Sgblack@eecs.umich.edu        vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
1848105Sgblack@eecs.umich.edu        req->setFlags(Request::MMAPPED_IPR);
1858582Sgblack@eecs.umich.edu
1868582Sgblack@eecs.umich.edu        MiscRegIndex regNum;
1878582Sgblack@eecs.umich.edu        if (!msrAddrToIndex(regNum, vaddr))
1886141Sgblack@eecs.umich.edu            return new GeneralProtection(0);
1898582Sgblack@eecs.umich.edu
1906141Sgblack@eecs.umich.edu        //The index is multiplied by the size of a MiscReg so that
1916141Sgblack@eecs.umich.edu        //any memory dependence calculations will not see these as
1926141Sgblack@eecs.umich.edu        //overlapping.
1938582Sgblack@eecs.umich.edu        req->setPaddr((Addr)regNum * sizeof(MiscReg));
1946141Sgblack@eecs.umich.edu        return NoFault;
1956141Sgblack@eecs.umich.edu    } else if (prefix == IntAddrPrefixIO) {
1966141Sgblack@eecs.umich.edu        // TODO If CPL > IOPL or in virtual mode, check the I/O permission
1976141Sgblack@eecs.umich.edu        // bitmap in the TSS.
1986141Sgblack@eecs.umich.edu
1996141Sgblack@eecs.umich.edu        Addr IOPort = vaddr & ~IntAddrPrefixMask;
2006141Sgblack@eecs.umich.edu        // Make sure the address fits in the expected 16 bit IO address
2016141Sgblack@eecs.umich.edu        // space.
2026141Sgblack@eecs.umich.edu        assert(!(IOPort & ~0xFFFF));
2036141Sgblack@eecs.umich.edu        if (IOPort == 0xCF8 && req->getSize() == 4) {
2048105Sgblack@eecs.umich.edu            req->setFlags(Request::MMAPPED_IPR);
2056141Sgblack@eecs.umich.edu            req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
2066141Sgblack@eecs.umich.edu        } else if ((IOPort & ~mask(2)) == 0xCFC) {
2077774Sgblack@eecs.umich.edu            req->setFlags(Request::UNCACHEABLE);
2086141Sgblack@eecs.umich.edu            Addr configAddress =
2096141Sgblack@eecs.umich.edu                tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
2106141Sgblack@eecs.umich.edu            if (bits(configAddress, 31, 31)) {
2116141Sgblack@eecs.umich.edu                req->setPaddr(PhysAddrPrefixPciConfig |
2126141Sgblack@eecs.umich.edu                        mbits(configAddress, 30, 2) |
2136141Sgblack@eecs.umich.edu                        (IOPort & mask(2)));
2148098Sgblack@eecs.umich.edu            } else {
2158098Sgblack@eecs.umich.edu                req->setPaddr(PhysAddrPrefixIO | IOPort);
2166141Sgblack@eecs.umich.edu            }
2176141Sgblack@eecs.umich.edu        } else {
2187774Sgblack@eecs.umich.edu            req->setFlags(Request::UNCACHEABLE);
2196141Sgblack@eecs.umich.edu            req->setPaddr(PhysAddrPrefixIO | IOPort);
2206141Sgblack@eecs.umich.edu        }
2216141Sgblack@eecs.umich.edu        return NoFault;
2226141Sgblack@eecs.umich.edu    } else {
2236141Sgblack@eecs.umich.edu        panic("Access to unrecognized internal address space %#x.\n",
2246141Sgblack@eecs.umich.edu                prefix);
2256141Sgblack@eecs.umich.edu    }
2266141Sgblack@eecs.umich.edu}
2276141Sgblack@eecs.umich.edu
2286141Sgblack@eecs.umich.eduFault
2296023Snate@binkert.orgTLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
2306023Snate@binkert.org        Mode mode, bool &delayedResponse, bool timing)
2315086Sgblack@eecs.umich.edu{
2326141Sgblack@eecs.umich.edu    uint32_t flags = req->getFlags();
2336141Sgblack@eecs.umich.edu    int seg = flags & SegmentFlagMask;
2346141Sgblack@eecs.umich.edu    bool storeCheck = flags & (StoreCheck << FlagShift);
2356141Sgblack@eecs.umich.edu
2368535Sgblack@eecs.umich.edu    delayedResponse = false;
2378535Sgblack@eecs.umich.edu
2386141Sgblack@eecs.umich.edu    // If this is true, we're dealing with a request to a non-memory address
2396141Sgblack@eecs.umich.edu    // space.
2406141Sgblack@eecs.umich.edu    if (seg == SEGMENT_REG_MS) {
2416141Sgblack@eecs.umich.edu        return translateInt(req, tc);
2426141Sgblack@eecs.umich.edu    }
2436141Sgblack@eecs.umich.edu
2445124Sgblack@eecs.umich.edu    Addr vaddr = req->getVaddr();
2455140Sgblack@eecs.umich.edu    DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
2465140Sgblack@eecs.umich.edu
2476141Sgblack@eecs.umich.edu    HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
2485140Sgblack@eecs.umich.edu
2495140Sgblack@eecs.umich.edu    // If protected mode has been enabled...
2506141Sgblack@eecs.umich.edu    if (m5Reg.prot) {
2515237Sgblack@eecs.umich.edu        DPRINTF(TLB, "In protected mode.\n");
2525140Sgblack@eecs.umich.edu        // If we're not in 64-bit mode, do protection/limit checks
2536141Sgblack@eecs.umich.edu        if (m5Reg.mode != LongMode) {
2545237Sgblack@eecs.umich.edu            DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
2555431Sgblack@eecs.umich.edu            // Check for a NULL segment selector.
2566059Sgblack@eecs.umich.edu            if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
2576141Sgblack@eecs.umich.edu                        seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
2586059Sgblack@eecs.umich.edu                    && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
2595431Sgblack@eecs.umich.edu                return new GeneralProtection(0);
2605433Sgblack@eecs.umich.edu            bool expandDown = false;
2615965Sgblack@eecs.umich.edu            SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
2625433Sgblack@eecs.umich.edu            if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
2636099Sgblack@eecs.umich.edu                if (!attr.writable && (mode == Write || storeCheck))
2645433Sgblack@eecs.umich.edu                    return new GeneralProtection(0);
2656023Snate@binkert.org                if (!attr.readable && mode == Read)
2665433Sgblack@eecs.umich.edu                    return new GeneralProtection(0);
2675433Sgblack@eecs.umich.edu                expandDown = attr.expandDown;
2685965Sgblack@eecs.umich.edu
2695433Sgblack@eecs.umich.edu            }
2705140Sgblack@eecs.umich.edu            Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
2715140Sgblack@eecs.umich.edu            Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
2725965Sgblack@eecs.umich.edu            bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
2739062Sjayneel@cs.wisc.edu            unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr
2749062Sjayneel@cs.wisc.edu                                            : (unsigned)m5Reg.defAddr;
2759028Sgblack@eecs.umich.edu            int size = (1 << logSize) * 8;
2769028Sgblack@eecs.umich.edu            Addr offset = bits(vaddr - base, size - 1, 0);
2775965Sgblack@eecs.umich.edu            Addr endOffset = offset + req->getSize() - 1;
2785433Sgblack@eecs.umich.edu            if (expandDown) {
2795237Sgblack@eecs.umich.edu                DPRINTF(TLB, "Checking an expand down segment.\n");
2805965Sgblack@eecs.umich.edu                warn_once("Expand down segments are untested.\n");
2815965Sgblack@eecs.umich.edu                if (offset <= limit || endOffset <= limit)
2825965Sgblack@eecs.umich.edu                    return new GeneralProtection(0);
2835140Sgblack@eecs.umich.edu            } else {
2845965Sgblack@eecs.umich.edu                if (offset > limit || endOffset > limit)
2855965Sgblack@eecs.umich.edu                    return new GeneralProtection(0);
2865140Sgblack@eecs.umich.edu            }
2875140Sgblack@eecs.umich.edu        }
2889025Sgblack@eecs.umich.edu        if (m5Reg.submode != SixtyFourBitMode ||
2898925Sgblack@eecs.umich.edu                (flags & (AddrSizeFlagBit << FlagShift)))
2908925Sgblack@eecs.umich.edu            vaddr &= mask(32);
2915140Sgblack@eecs.umich.edu        // If paging is enabled, do the translation.
2926141Sgblack@eecs.umich.edu        if (m5Reg.paging) {
2935237Sgblack@eecs.umich.edu            DPRINTF(TLB, "Paging enabled.\n");
2945140Sgblack@eecs.umich.edu            // The vaddr already has the segment base applied.
2955140Sgblack@eecs.umich.edu            TlbEntry *entry = lookup(vaddr);
2965140Sgblack@eecs.umich.edu            if (!entry) {
2978752Sgblack@eecs.umich.edu                if (FullSystem) {
2988752Sgblack@eecs.umich.edu                    Fault fault = walker->start(tc, translation, req, mode);
2998752Sgblack@eecs.umich.edu                    if (timing || fault != NoFault) {
3008752Sgblack@eecs.umich.edu                        // This gets ignored in atomic mode.
3018752Sgblack@eecs.umich.edu                        delayedResponse = true;
3028752Sgblack@eecs.umich.edu                        return fault;
3038752Sgblack@eecs.umich.edu                    }
3048752Sgblack@eecs.umich.edu                    entry = lookup(vaddr);
3058752Sgblack@eecs.umich.edu                    assert(entry);
3068752Sgblack@eecs.umich.edu                } else {
3078752Sgblack@eecs.umich.edu                    DPRINTF(TLB, "Handling a TLB miss for "
3088752Sgblack@eecs.umich.edu                            "address %#x at pc %#x.\n",
3098752Sgblack@eecs.umich.edu                            vaddr, tc->instAddr());
3108752Sgblack@eecs.umich.edu
3118752Sgblack@eecs.umich.edu                    Process *p = tc->getProcessPtr();
3128752Sgblack@eecs.umich.edu                    TlbEntry newEntry;
3138752Sgblack@eecs.umich.edu                    bool success = p->pTable->lookup(vaddr, newEntry);
3148752Sgblack@eecs.umich.edu                    if (!success && mode != Execute) {
3158752Sgblack@eecs.umich.edu                        // Check if we just need to grow the stack.
3168752Sgblack@eecs.umich.edu                        if (p->fixupStackFault(vaddr)) {
3178752Sgblack@eecs.umich.edu                            // If we did, lookup the entry for the new page.
3188752Sgblack@eecs.umich.edu                            success = p->pTable->lookup(vaddr, newEntry);
3198752Sgblack@eecs.umich.edu                        }
3208752Sgblack@eecs.umich.edu                    }
3218752Sgblack@eecs.umich.edu                    if (!success) {
3228752Sgblack@eecs.umich.edu                        return new PageFault(vaddr, true, mode, true, false);
3238752Sgblack@eecs.umich.edu                    } else {
3248752Sgblack@eecs.umich.edu                        Addr alignedVaddr = p->pTable->pageAlign(vaddr);
3258752Sgblack@eecs.umich.edu                        DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
3268752Sgblack@eecs.umich.edu                                newEntry.pageStart());
3278752Sgblack@eecs.umich.edu                        entry = insert(alignedVaddr, newEntry);
3288752Sgblack@eecs.umich.edu                    }
3298752Sgblack@eecs.umich.edu                    DPRINTF(TLB, "Miss was serviced.\n");
3305895Sgblack@eecs.umich.edu                }
3315140Sgblack@eecs.umich.edu            }
3328646Snilay@cs.wisc.edu
3338646Snilay@cs.wisc.edu            DPRINTF(TLB, "Entry found with paddr %#x, "
3348646Snilay@cs.wisc.edu                    "doing protection checks.\n", entry->paddr);
3355895Sgblack@eecs.umich.edu            // Do paging protection checks.
3366141Sgblack@eecs.umich.edu            bool inUser = (m5Reg.cpl == 3 &&
3375917Sgblack@eecs.umich.edu                    !(flags & (CPL0FlagBit << FlagShift)));
3387933Stharris@microsoft.com            CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
3397933Stharris@microsoft.com            bool badWrite = (!entry->writable && (inUser || cr0.wp));
3407933Stharris@microsoft.com            if ((inUser && !entry->user) || (mode == Write && badWrite)) {
3415917Sgblack@eecs.umich.edu                // The page must have been present to get into the TLB in
3425917Sgblack@eecs.umich.edu                // the first place. We'll assume the reserved bits are
3435917Sgblack@eecs.umich.edu                // fine even though we're not checking them.
3446023Snate@binkert.org                return new PageFault(vaddr, true, mode, inUser, false);
3455917Sgblack@eecs.umich.edu            }
3467933Stharris@microsoft.com            if (storeCheck && badWrite) {
3476099Sgblack@eecs.umich.edu                // This would fault if this were a write, so return a page
3486099Sgblack@eecs.umich.edu                // fault that reflects that happening.
3496099Sgblack@eecs.umich.edu                return new PageFault(vaddr, true, Write, inUser, false);
3506099Sgblack@eecs.umich.edu            }
3515917Sgblack@eecs.umich.edu
3528953Sgblack@eecs.umich.edu            Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes));
3535895Sgblack@eecs.umich.edu            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
3545895Sgblack@eecs.umich.edu            req->setPaddr(paddr);
3557775Sgblack@eecs.umich.edu            if (entry->uncacheable)
3567775Sgblack@eecs.umich.edu                req->setFlags(Request::UNCACHEABLE);
3575140Sgblack@eecs.umich.edu        } else {
3585140Sgblack@eecs.umich.edu            //Use the address which already has segmentation applied.
3595237Sgblack@eecs.umich.edu            DPRINTF(TLB, "Paging disabled.\n");
3605237Sgblack@eecs.umich.edu            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
3615140Sgblack@eecs.umich.edu            req->setPaddr(vaddr);
3625140Sgblack@eecs.umich.edu        }
3635124Sgblack@eecs.umich.edu    } else {
3645140Sgblack@eecs.umich.edu        // Real mode
3655237Sgblack@eecs.umich.edu        DPRINTF(TLB, "In real mode.\n");
3665237Sgblack@eecs.umich.edu        DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
3675140Sgblack@eecs.umich.edu        req->setPaddr(vaddr);
3685124Sgblack@eecs.umich.edu    }
3695360Sgblack@eecs.umich.edu    // Check for an access to the local APIC
3708767Sgblack@eecs.umich.edu    if (FullSystem) {
3718767Sgblack@eecs.umich.edu        LocalApicBase localApicBase =
3728767Sgblack@eecs.umich.edu            tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
3738767Sgblack@eecs.umich.edu        Addr baseAddr = localApicBase.base * PageBytes;
3748767Sgblack@eecs.umich.edu        Addr paddr = req->getPaddr();
3758767Sgblack@eecs.umich.edu        if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
3768767Sgblack@eecs.umich.edu            // The Intel developer's manuals say the below restrictions apply,
3778767Sgblack@eecs.umich.edu            // but the linux kernel, because of a compiler optimization, breaks
3788767Sgblack@eecs.umich.edu            // them.
3798767Sgblack@eecs.umich.edu            /*
3808767Sgblack@eecs.umich.edu            // Check alignment
3818767Sgblack@eecs.umich.edu            if (paddr & ((32/8) - 1))
3828767Sgblack@eecs.umich.edu                return new GeneralProtection(0);
3838767Sgblack@eecs.umich.edu            // Check access size
3848767Sgblack@eecs.umich.edu            if (req->getSize() != (32/8))
3858767Sgblack@eecs.umich.edu                return new GeneralProtection(0);
3868767Sgblack@eecs.umich.edu            */
3878767Sgblack@eecs.umich.edu            // Force the access to be uncacheable.
3888767Sgblack@eecs.umich.edu            req->setFlags(Request::UNCACHEABLE);
3898767Sgblack@eecs.umich.edu            req->setPaddr(x86LocalAPICAddress(tc->contextId(),
3908767Sgblack@eecs.umich.edu                        paddr - baseAddr));
3918767Sgblack@eecs.umich.edu        }
3925360Sgblack@eecs.umich.edu    }
3935086Sgblack@eecs.umich.edu    return NoFault;
3948902Sandreas.hansson@arm.com}
3955086Sgblack@eecs.umich.edu
3965140Sgblack@eecs.umich.eduFault
3976023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
3985140Sgblack@eecs.umich.edu{
3995895Sgblack@eecs.umich.edu    bool delayedResponse;
4006023Snate@binkert.org    return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
4015140Sgblack@eecs.umich.edu}
4025140Sgblack@eecs.umich.edu
4035894Sgblack@eecs.umich.eduvoid
4046022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc,
4056023Snate@binkert.org        Translation *translation, Mode mode)
4065894Sgblack@eecs.umich.edu{
4075895Sgblack@eecs.umich.edu    bool delayedResponse;
4085894Sgblack@eecs.umich.edu    assert(translation);
4096023Snate@binkert.org    Fault fault =
4106023Snate@binkert.org        TLB::translate(req, tc, translation, mode, delayedResponse, true);
4115895Sgblack@eecs.umich.edu    if (!delayedResponse)
4126023Snate@binkert.org        translation->finish(fault, req, tc, mode);
4135894Sgblack@eecs.umich.edu}
4145894Sgblack@eecs.umich.edu
4158888Sgeoffrey.blake@arm.comFault
4168888Sgeoffrey.blake@arm.comTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
4178888Sgeoffrey.blake@arm.com{
4188888Sgeoffrey.blake@arm.com    panic("Not implemented\n");
4198888Sgeoffrey.blake@arm.com    return NoFault;
4208888Sgeoffrey.blake@arm.com}
4218888Sgeoffrey.blake@arm.com
4227912Shestness@cs.utexas.eduWalker *
4237912Shestness@cs.utexas.eduTLB::getWalker()
4247912Shestness@cs.utexas.edu{
4257912Shestness@cs.utexas.edu    return walker;
4267912Shestness@cs.utexas.edu}
4277912Shestness@cs.utexas.edu
4285086Sgblack@eecs.umich.eduvoid
4295086Sgblack@eecs.umich.eduTLB::serialize(std::ostream &os)
4305086Sgblack@eecs.umich.edu{
4315086Sgblack@eecs.umich.edu}
4325086Sgblack@eecs.umich.edu
4335086Sgblack@eecs.umich.eduvoid
4345086Sgblack@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string &section)
4355086Sgblack@eecs.umich.edu{
4365086Sgblack@eecs.umich.edu}
4375086Sgblack@eecs.umich.edu
4389294Sandreas.hansson@arm.comBaseMasterPort *
4398922Swilliam.wang@arm.comTLB::getMasterPort()
4408864Snilay@cs.wisc.edu{
4418922Swilliam.wang@arm.com    return &walker->getMasterPort("port");
4428864Snilay@cs.wisc.edu}
4438864Snilay@cs.wisc.edu
4447811Ssteve.reinhardt@amd.com} // namespace X86ISA
4455086Sgblack@eecs.umich.edu
4466022Sgblack@eecs.umich.eduX86ISA::TLB *
4476022Sgblack@eecs.umich.eduX86TLBParams::create()
4484997Sgblack@eecs.umich.edu{
4496022Sgblack@eecs.umich.edu    return new X86ISA::TLB(this);
4504997Sgblack@eecs.umich.edu}
451