tlb.cc revision 9064
12686Sksewell@umich.edu/* 22686Sksewell@umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 35254Sksewell@umich.edu * All rights reserved. 45254Sksewell@umich.edu * 55254Sksewell@umich.edu * The license below extends only to copyright in the software and shall 65254Sksewell@umich.edu * not be construed as granting a license to any other intellectual 75254Sksewell@umich.edu * property including but not limited to intellectual property relating 85254Sksewell@umich.edu * to a hardware implementation of the functionality of the software 95254Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 105254Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 115254Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 125254Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 135254Sksewell@umich.edu * 145254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 155254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 165254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 175254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 185254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 195254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 205254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 215254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 225254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 235254Sksewell@umich.edu * this software without specific prior written permission. 245254Sksewell@umich.edu * 255254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 265254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 275254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 285254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 295254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 305254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312706Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322023SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 338449Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 348449Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 358449Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 368449Sgblack@eecs.umich.edu * 378449Sgblack@eecs.umich.edu * Authors: Gabe Black 388449Sgblack@eecs.umich.edu */ 398449Sgblack@eecs.umich.edu 408449Sgblack@eecs.umich.edu#include <cstring> 418449Sgblack@eecs.umich.edu 428449Sgblack@eecs.umich.edu#include "arch/x86/insts/microldstop.hh" 432023SN/A#include "arch/x86/regs/misc.hh" 442023SN/A#include "arch/x86/regs/msr.hh" 452023SN/A#include "arch/x86/faults.hh" 462616SN/A#include "arch/x86/pagetable.hh" 472077SN/A#include "arch/x86/pagetable_walker.hh" 482077SN/A#include "arch/x86/tlb.hh" 492077SN/A#include "arch/x86/x86_traits.hh" 502616SN/A#include "base/bitfield.hh" 514661Sksewell@umich.edu#include "base/trace.hh" 524661Sksewell@umich.edu#include "cpu/base.hh" 534661Sksewell@umich.edu#include "cpu/thread_context.hh" 542616SN/A#include "debug/TLB.hh" 552616SN/A#include "mem/packet_access.hh" 562562SN/A#include "mem/page_table.hh" 572041SN/A#include "mem/request.hh" 582616SN/A#include "sim/full_system.hh" 596383Sgblack@eecs.umich.edu#include "sim/process.hh" 606383Sgblack@eecs.umich.edu 612616SN/Anamespace X86ISA { 624661Sksewell@umich.edu 636383Sgblack@eecs.umich.eduTLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size), 646383Sgblack@eecs.umich.edu lruSeq(0) 656383Sgblack@eecs.umich.edu{ 666383Sgblack@eecs.umich.edu if (!size) 674661Sksewell@umich.edu fatal("TLBs must have a non-zero size.\n"); 684661Sksewell@umich.edu tlb = new TlbEntry[size]; 696383Sgblack@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 706383Sgblack@eecs.umich.edu 716383Sgblack@eecs.umich.edu for (int x = 0; x < size; x++) { 726383Sgblack@eecs.umich.edu tlb[x].trieHandle = NULL; 736383Sgblack@eecs.umich.edu freeList.push_back(&tlb[x]); 746383Sgblack@eecs.umich.edu } 756383Sgblack@eecs.umich.edu 766383Sgblack@eecs.umich.edu walker = p->walker; 776383Sgblack@eecs.umich.edu walker->setTLB(this); 786383Sgblack@eecs.umich.edu} 796383Sgblack@eecs.umich.edu 806383Sgblack@eecs.umich.eduvoid 816383Sgblack@eecs.umich.eduTLB::evictLRU() 822041SN/A{ 832616SN/A // Find the entry with the lowest (and hence least recently updated) 842077SN/A // sequence number. 852077SN/A 862077SN/A unsigned lru = 0; 872239SN/A for (unsigned i = 1; i < size; i++) { 882041SN/A if (tlb[i].lruSeq < tlb[lru].lruSeq) 894661Sksewell@umich.edu lru = i; 906383Sgblack@eecs.umich.edu } 916383Sgblack@eecs.umich.edu 926383Sgblack@eecs.umich.edu assert(tlb[lru].trieHandle); 936383Sgblack@eecs.umich.edu trie.remove(tlb[lru].trieHandle); 946383Sgblack@eecs.umich.edu tlb[lru].trieHandle = NULL; 952616SN/A freeList.push_back(&tlb[lru]); 964661Sksewell@umich.edu} 972607SN/A 982607SN/ATlbEntry * 992607SN/ATLB::insert(Addr vpn, TlbEntry &entry) 1002607SN/A{ 1012607SN/A // If somebody beat us to it, just use that existing entry. 1022607SN/A TlbEntry *newEntry = trie.lookup(vpn); 1032607SN/A if (newEntry) { 1042607SN/A assert(newEntry->vaddr == vpn); 1052607SN/A return newEntry; 1064661Sksewell@umich.edu } 1076383Sgblack@eecs.umich.edu 1084661Sksewell@umich.edu if (freeList.empty()) 1095222Sksewell@umich.edu evictLRU(); 1106383Sgblack@eecs.umich.edu 1115222Sksewell@umich.edu newEntry = freeList.front(); 1126807Sgblack@eecs.umich.edu freeList.pop_front(); 1136807Sgblack@eecs.umich.edu 1146807Sgblack@eecs.umich.edu *newEntry = entry; 1155222Sksewell@umich.edu newEntry->lruSeq = nextSeq(); 1166807Sgblack@eecs.umich.edu newEntry->vaddr = vpn; 1175222Sksewell@umich.edu newEntry->trieHandle = 1185222Sksewell@umich.edu trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry); 1196338Sgblack@eecs.umich.edu return newEntry; 1204661Sksewell@umich.edu} 1214661Sksewell@umich.edu 1226383Sgblack@eecs.umich.eduTlbEntry * 1236383Sgblack@eecs.umich.eduTLB::lookup(Addr va, bool update_lru) 1246383Sgblack@eecs.umich.edu{ 1256383Sgblack@eecs.umich.edu TlbEntry *entry = trie.lookup(va); 1266383Sgblack@eecs.umich.edu if (entry && update_lru) 1276383Sgblack@eecs.umich.edu entry->lruSeq = nextSeq(); 1286383Sgblack@eecs.umich.edu return entry; 1296383Sgblack@eecs.umich.edu} 1304661Sksewell@umich.edu 1315222Sksewell@umich.eduvoid 1326383Sgblack@eecs.umich.eduTLB::invalidateAll() 1336383Sgblack@eecs.umich.edu{ 1346383Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all entries.\n"); 1356383Sgblack@eecs.umich.edu for (unsigned i = 0; i < size; i++) { 1366383Sgblack@eecs.umich.edu if (tlb[i].trieHandle) { 1376383Sgblack@eecs.umich.edu trie.remove(tlb[i].trieHandle); 1386383Sgblack@eecs.umich.edu tlb[i].trieHandle = NULL; 1396383Sgblack@eecs.umich.edu freeList.push_back(&tlb[i]); 1406383Sgblack@eecs.umich.edu } 1416383Sgblack@eecs.umich.edu } 1426383Sgblack@eecs.umich.edu} 1436383Sgblack@eecs.umich.edu 1446383Sgblack@eecs.umich.eduvoid 1456383Sgblack@eecs.umich.eduTLB::setConfigAddress(uint32_t addr) 1466383Sgblack@eecs.umich.edu{ 1476383Sgblack@eecs.umich.edu configAddress = addr; 1486383Sgblack@eecs.umich.edu} 1494661Sksewell@umich.edu 1502616SN/Avoid 1512495SN/ATLB::invalidateNonGlobal() 1522041SN/A{ 1532616SN/A DPRINTF(TLB, "Invalidating all non global entries.\n"); 1547792Sgblack@eecs.umich.edu for (unsigned i = 0; i < size; i++) { 1557792Sgblack@eecs.umich.edu if (tlb[i].trieHandle && !tlb[i].global) { 1567792Sgblack@eecs.umich.edu trie.remove(tlb[i].trieHandle); 1572023SN/A tlb[i].trieHandle = NULL; 158 freeList.push_back(&tlb[i]); 159 } 160 } 161} 162 163void 164TLB::demapPage(Addr va, uint64_t asn) 165{ 166 TlbEntry *entry = trie.lookup(va); 167 if (entry) { 168 trie.remove(entry->trieHandle); 169 entry->trieHandle = NULL; 170 freeList.push_back(entry); 171 } 172} 173 174Fault 175TLB::translateInt(RequestPtr req, ThreadContext *tc) 176{ 177 DPRINTF(TLB, "Addresses references internal memory.\n"); 178 Addr vaddr = req->getVaddr(); 179 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 180 if (prefix == IntAddrPrefixCPUID) { 181 panic("CPUID memory space not yet implemented!\n"); 182 } else if (prefix == IntAddrPrefixMSR) { 183 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask; 184 req->setFlags(Request::MMAPPED_IPR); 185 186 MiscRegIndex regNum; 187 if (!msrAddrToIndex(regNum, vaddr)) 188 return new GeneralProtection(0); 189 190 //The index is multiplied by the size of a MiscReg so that 191 //any memory dependence calculations will not see these as 192 //overlapping. 193 req->setPaddr((Addr)regNum * sizeof(MiscReg)); 194 return NoFault; 195 } else if (prefix == IntAddrPrefixIO) { 196 // TODO If CPL > IOPL or in virtual mode, check the I/O permission 197 // bitmap in the TSS. 198 199 Addr IOPort = vaddr & ~IntAddrPrefixMask; 200 // Make sure the address fits in the expected 16 bit IO address 201 // space. 202 assert(!(IOPort & ~0xFFFF)); 203 if (IOPort == 0xCF8 && req->getSize() == 4) { 204 req->setFlags(Request::MMAPPED_IPR); 205 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 206 } else if ((IOPort & ~mask(2)) == 0xCFC) { 207 req->setFlags(Request::UNCACHEABLE); 208 Addr configAddress = 209 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 210 if (bits(configAddress, 31, 31)) { 211 req->setPaddr(PhysAddrPrefixPciConfig | 212 mbits(configAddress, 30, 2) | 213 (IOPort & mask(2))); 214 } else { 215 req->setPaddr(PhysAddrPrefixIO | IOPort); 216 } 217 } else { 218 req->setFlags(Request::UNCACHEABLE); 219 req->setPaddr(PhysAddrPrefixIO | IOPort); 220 } 221 return NoFault; 222 } else { 223 panic("Access to unrecognized internal address space %#x.\n", 224 prefix); 225 } 226} 227 228Fault 229TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, 230 Mode mode, bool &delayedResponse, bool timing) 231{ 232 uint32_t flags = req->getFlags(); 233 int seg = flags & SegmentFlagMask; 234 bool storeCheck = flags & (StoreCheck << FlagShift); 235 236 delayedResponse = false; 237 238 // If this is true, we're dealing with a request to a non-memory address 239 // space. 240 if (seg == SEGMENT_REG_MS) { 241 return translateInt(req, tc); 242 } 243 244 Addr vaddr = req->getVaddr(); 245 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 246 247 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 248 249 // If protected mode has been enabled... 250 if (m5Reg.prot) { 251 DPRINTF(TLB, "In protected mode.\n"); 252 // If we're not in 64-bit mode, do protection/limit checks 253 if (m5Reg.mode != LongMode) { 254 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 255 // Check for a NULL segment selector. 256 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 257 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 258 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 259 return new GeneralProtection(0); 260 bool expandDown = false; 261 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 262 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 263 if (!attr.writable && (mode == Write || storeCheck)) 264 return new GeneralProtection(0); 265 if (!attr.readable && mode == Read) 266 return new GeneralProtection(0); 267 expandDown = attr.expandDown; 268 269 } 270 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 271 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 272 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 273 unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr 274 : (unsigned)m5Reg.defAddr; 275 int size = (1 << logSize) * 8; 276 Addr offset = bits(vaddr - base, size - 1, 0); 277 Addr endOffset = offset + req->getSize() - 1; 278 if (expandDown) { 279 DPRINTF(TLB, "Checking an expand down segment.\n"); 280 warn_once("Expand down segments are untested.\n"); 281 if (offset <= limit || endOffset <= limit) 282 return new GeneralProtection(0); 283 } else { 284 if (offset > limit || endOffset > limit) 285 return new GeneralProtection(0); 286 } 287 } 288 if (m5Reg.submode != SixtyFourBitMode || 289 (flags & (AddrSizeFlagBit << FlagShift))) 290 vaddr &= mask(32); 291 // If paging is enabled, do the translation. 292 if (m5Reg.paging) { 293 DPRINTF(TLB, "Paging enabled.\n"); 294 // The vaddr already has the segment base applied. 295 TlbEntry *entry = lookup(vaddr); 296 if (!entry) { 297 if (FullSystem) { 298 Fault fault = walker->start(tc, translation, req, mode); 299 if (timing || fault != NoFault) { 300 // This gets ignored in atomic mode. 301 delayedResponse = true; 302 return fault; 303 } 304 entry = lookup(vaddr); 305 assert(entry); 306 } else { 307 DPRINTF(TLB, "Handling a TLB miss for " 308 "address %#x at pc %#x.\n", 309 vaddr, tc->instAddr()); 310 311 Process *p = tc->getProcessPtr(); 312 TlbEntry newEntry; 313 bool success = p->pTable->lookup(vaddr, newEntry); 314 if (!success && mode != Execute) { 315 // Check if we just need to grow the stack. 316 if (p->fixupStackFault(vaddr)) { 317 // If we did, lookup the entry for the new page. 318 success = p->pTable->lookup(vaddr, newEntry); 319 } 320 } 321 if (!success) { 322 return new PageFault(vaddr, true, mode, true, false); 323 } else { 324 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 325 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 326 newEntry.pageStart()); 327 entry = insert(alignedVaddr, newEntry); 328 } 329 DPRINTF(TLB, "Miss was serviced.\n"); 330 } 331 } 332 333 DPRINTF(TLB, "Entry found with paddr %#x, " 334 "doing protection checks.\n", entry->paddr); 335 // Do paging protection checks. 336 bool inUser = (m5Reg.cpl == 3 && 337 !(flags & (CPL0FlagBit << FlagShift))); 338 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 339 bool badWrite = (!entry->writable && (inUser || cr0.wp)); 340 if ((inUser && !entry->user) || (mode == Write && badWrite)) { 341 // The page must have been present to get into the TLB in 342 // the first place. We'll assume the reserved bits are 343 // fine even though we're not checking them. 344 return new PageFault(vaddr, true, mode, inUser, false); 345 } 346 if (storeCheck && badWrite) { 347 // This would fault if this were a write, so return a page 348 // fault that reflects that happening. 349 return new PageFault(vaddr, true, Write, inUser, false); 350 } 351 352 Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes)); 353 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 354 req->setPaddr(paddr); 355 if (entry->uncacheable) 356 req->setFlags(Request::UNCACHEABLE); 357 } else { 358 //Use the address which already has segmentation applied. 359 DPRINTF(TLB, "Paging disabled.\n"); 360 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 361 req->setPaddr(vaddr); 362 } 363 } else { 364 // Real mode 365 DPRINTF(TLB, "In real mode.\n"); 366 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 367 req->setPaddr(vaddr); 368 } 369 // Check for an access to the local APIC 370 if (FullSystem) { 371 LocalApicBase localApicBase = 372 tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 373 Addr baseAddr = localApicBase.base * PageBytes; 374 Addr paddr = req->getPaddr(); 375 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) { 376 // The Intel developer's manuals say the below restrictions apply, 377 // but the linux kernel, because of a compiler optimization, breaks 378 // them. 379 /* 380 // Check alignment 381 if (paddr & ((32/8) - 1)) 382 return new GeneralProtection(0); 383 // Check access size 384 if (req->getSize() != (32/8)) 385 return new GeneralProtection(0); 386 */ 387 // Force the access to be uncacheable. 388 req->setFlags(Request::UNCACHEABLE); 389 req->setPaddr(x86LocalAPICAddress(tc->contextId(), 390 paddr - baseAddr)); 391 } 392 } 393 return NoFault; 394} 395 396Fault 397TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 398{ 399 bool delayedResponse; 400 return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 401} 402 403void 404TLB::translateTiming(RequestPtr req, ThreadContext *tc, 405 Translation *translation, Mode mode) 406{ 407 bool delayedResponse; 408 assert(translation); 409 Fault fault = 410 TLB::translate(req, tc, translation, mode, delayedResponse, true); 411 if (!delayedResponse) 412 translation->finish(fault, req, tc, mode); 413} 414 415Fault 416TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 417{ 418 panic("Not implemented\n"); 419 return NoFault; 420} 421 422Walker * 423TLB::getWalker() 424{ 425 return walker; 426} 427 428void 429TLB::serialize(std::ostream &os) 430{ 431} 432 433void 434TLB::unserialize(Checkpoint *cp, const std::string §ion) 435{ 436} 437 438MasterPort * 439TLB::getMasterPort() 440{ 441 return &walker->getMasterPort("port"); 442} 443 444} // namespace X86ISA 445 446X86ISA::TLB * 447X86TLBParams::create() 448{ 449 return new X86ISA::TLB(this); 450} 451