tlb.cc revision 8953
14997Sgblack@eecs.umich.edu/* 25417Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 34997Sgblack@eecs.umich.edu * All rights reserved. 44997Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 134997Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 157087Snate@binkert.org * modification, are permitted provided that the following conditions are 167087Snate@binkert.org * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 224997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 244997Sgblack@eecs.umich.edu * 254997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 264997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 274997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 284997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 294997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 304997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 314997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 334997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 354997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 364997Sgblack@eecs.umich.edu * 374997Sgblack@eecs.umich.edu * Authors: Gabe Black 384997Sgblack@eecs.umich.edu */ 394997Sgblack@eecs.umich.edu 404997Sgblack@eecs.umich.edu#include <cstring> 414997Sgblack@eecs.umich.edu 428229Snate@binkert.org#include "arch/x86/insts/microldstop.hh" 438229Snate@binkert.org#include "arch/x86/regs/misc.hh" 448582Sgblack@eecs.umich.edu#include "arch/x86/regs/msr.hh" 456315Sgblack@eecs.umich.edu#include "arch/x86/faults.hh" 465124Sgblack@eecs.umich.edu#include "arch/x86/pagetable.hh" 478752Sgblack@eecs.umich.edu#include "arch/x86/pagetable_walker.hh" 485086Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh" 495149Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 505086Sgblack@eecs.umich.edu#include "base/bitfield.hh" 515086Sgblack@eecs.umich.edu#include "base/trace.hh" 528229Snate@binkert.org#include "cpu/base.hh" 535086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 548232Snate@binkert.org#include "debug/TLB.hh" 555086Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 568767Sgblack@eecs.umich.edu#include "mem/page_table.hh" 575086Sgblack@eecs.umich.edu#include "mem/request.hh" 588767Sgblack@eecs.umich.edu#include "sim/full_system.hh" 595895Sgblack@eecs.umich.edu#include "sim/process.hh" 605086Sgblack@eecs.umich.edu 615086Sgblack@eecs.umich.edunamespace X86ISA { 625086Sgblack@eecs.umich.edu 638953Sgblack@eecs.umich.eduTLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size), 648953Sgblack@eecs.umich.edu lruSeq(0) 655124Sgblack@eecs.umich.edu{ 668953Sgblack@eecs.umich.edu if (!size) 678953Sgblack@eecs.umich.edu fatal("TLBs must have a non-zero size.\n"); 685124Sgblack@eecs.umich.edu tlb = new TlbEntry[size]; 695124Sgblack@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 705124Sgblack@eecs.umich.edu 718953Sgblack@eecs.umich.edu for (int x = 0; x < size; x++) { 728953Sgblack@eecs.umich.edu tlb[x].trieHandle = NULL; 735124Sgblack@eecs.umich.edu freeList.push_back(&tlb[x]); 748953Sgblack@eecs.umich.edu } 755124Sgblack@eecs.umich.edu 765245Sgblack@eecs.umich.edu walker = p->walker; 775245Sgblack@eecs.umich.edu walker->setTLB(this); 785236Sgblack@eecs.umich.edu} 795236Sgblack@eecs.umich.edu 808953Sgblack@eecs.umich.eduvoid 818953Sgblack@eecs.umich.eduTLB::evictLRU() 828953Sgblack@eecs.umich.edu{ 838953Sgblack@eecs.umich.edu // Find the entry with the lowest (and hence least recently updated) 848953Sgblack@eecs.umich.edu // sequence number. 858953Sgblack@eecs.umich.edu 868953Sgblack@eecs.umich.edu unsigned lru = 0; 878953Sgblack@eecs.umich.edu for (unsigned i = 1; i < size; i++) { 888953Sgblack@eecs.umich.edu if (tlb[i].lruSeq < tlb[lru].lruSeq) 898953Sgblack@eecs.umich.edu lru = i; 908953Sgblack@eecs.umich.edu } 918953Sgblack@eecs.umich.edu 928953Sgblack@eecs.umich.edu assert(tlb[lru].trieHandle); 938953Sgblack@eecs.umich.edu trie.remove(tlb[lru].trieHandle); 948953Sgblack@eecs.umich.edu tlb[lru].trieHandle = NULL; 958953Sgblack@eecs.umich.edu freeList.push_back(&tlb[lru]); 968953Sgblack@eecs.umich.edu} 978953Sgblack@eecs.umich.edu 985895Sgblack@eecs.umich.eduTlbEntry * 995124Sgblack@eecs.umich.eduTLB::insert(Addr vpn, TlbEntry &entry) 1005124Sgblack@eecs.umich.edu{ 1015124Sgblack@eecs.umich.edu //TODO Deal with conflicting entries 1025124Sgblack@eecs.umich.edu 1035124Sgblack@eecs.umich.edu TlbEntry *newEntry = NULL; 1048953Sgblack@eecs.umich.edu if (freeList.empty()) 1058953Sgblack@eecs.umich.edu evictLRU(); 1068953Sgblack@eecs.umich.edu newEntry = freeList.front(); 1078953Sgblack@eecs.umich.edu freeList.pop_front(); 1088953Sgblack@eecs.umich.edu 1095124Sgblack@eecs.umich.edu *newEntry = entry; 1108953Sgblack@eecs.umich.edu newEntry->lruSeq = nextSeq(); 1115124Sgblack@eecs.umich.edu newEntry->vaddr = vpn; 1128953Sgblack@eecs.umich.edu newEntry->trieHandle = 1138953Sgblack@eecs.umich.edu trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry); 1145895Sgblack@eecs.umich.edu return newEntry; 1155124Sgblack@eecs.umich.edu} 1165124Sgblack@eecs.umich.edu 1175360Sgblack@eecs.umich.eduTlbEntry * 1185360Sgblack@eecs.umich.eduTLB::lookup(Addr va, bool update_lru) 1195360Sgblack@eecs.umich.edu{ 1208953Sgblack@eecs.umich.edu TlbEntry *entry = trie.lookup(va); 1218953Sgblack@eecs.umich.edu if (entry && update_lru) 1228953Sgblack@eecs.umich.edu entry->lruSeq = nextSeq(); 1238953Sgblack@eecs.umich.edu return entry; 1245124Sgblack@eecs.umich.edu} 1255124Sgblack@eecs.umich.edu 1265124Sgblack@eecs.umich.eduvoid 1275124Sgblack@eecs.umich.eduTLB::invalidateAll() 1285124Sgblack@eecs.umich.edu{ 1295242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all entries.\n"); 1308953Sgblack@eecs.umich.edu for (unsigned i = 0; i < size; i++) { 1318953Sgblack@eecs.umich.edu if (tlb[i].trieHandle) { 1328953Sgblack@eecs.umich.edu trie.remove(tlb[i].trieHandle); 1338953Sgblack@eecs.umich.edu tlb[i].trieHandle = NULL; 1348953Sgblack@eecs.umich.edu freeList.push_back(&tlb[i]); 1358953Sgblack@eecs.umich.edu } 1365242Sgblack@eecs.umich.edu } 1375124Sgblack@eecs.umich.edu} 1385124Sgblack@eecs.umich.edu 1395124Sgblack@eecs.umich.eduvoid 1405357Sgblack@eecs.umich.eduTLB::setConfigAddress(uint32_t addr) 1415357Sgblack@eecs.umich.edu{ 1425357Sgblack@eecs.umich.edu configAddress = addr; 1435357Sgblack@eecs.umich.edu} 1445357Sgblack@eecs.umich.edu 1455357Sgblack@eecs.umich.eduvoid 1465124Sgblack@eecs.umich.eduTLB::invalidateNonGlobal() 1475124Sgblack@eecs.umich.edu{ 1485242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all non global entries.\n"); 1498953Sgblack@eecs.umich.edu for (unsigned i = 0; i < size; i++) { 1508953Sgblack@eecs.umich.edu if (tlb[i].trieHandle && !tlb[i].global) { 1518953Sgblack@eecs.umich.edu trie.remove(tlb[i].trieHandle); 1528953Sgblack@eecs.umich.edu tlb[i].trieHandle = NULL; 1538953Sgblack@eecs.umich.edu freeList.push_back(&tlb[i]); 1545242Sgblack@eecs.umich.edu } 1555242Sgblack@eecs.umich.edu } 1565124Sgblack@eecs.umich.edu} 1575124Sgblack@eecs.umich.edu 1585124Sgblack@eecs.umich.eduvoid 1595358Sgblack@eecs.umich.eduTLB::demapPage(Addr va, uint64_t asn) 1605086Sgblack@eecs.umich.edu{ 1618953Sgblack@eecs.umich.edu TlbEntry *entry = trie.lookup(va); 1628953Sgblack@eecs.umich.edu if (entry) { 1638953Sgblack@eecs.umich.edu trie.remove(entry->trieHandle); 1648953Sgblack@eecs.umich.edu entry->trieHandle = NULL; 1658953Sgblack@eecs.umich.edu freeList.push_back(entry); 1665359Sgblack@eecs.umich.edu } 1675086Sgblack@eecs.umich.edu} 1685086Sgblack@eecs.umich.edu 1695086Sgblack@eecs.umich.eduFault 1706141Sgblack@eecs.umich.eduTLB::translateInt(RequestPtr req, ThreadContext *tc) 1716141Sgblack@eecs.umich.edu{ 1726141Sgblack@eecs.umich.edu DPRINTF(TLB, "Addresses references internal memory.\n"); 1736141Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 1746141Sgblack@eecs.umich.edu Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 1756141Sgblack@eecs.umich.edu if (prefix == IntAddrPrefixCPUID) { 1766141Sgblack@eecs.umich.edu panic("CPUID memory space not yet implemented!\n"); 1776141Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixMSR) { 1788582Sgblack@eecs.umich.edu vaddr = (vaddr >> 3) & ~IntAddrPrefixMask; 1798105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 1808582Sgblack@eecs.umich.edu 1818582Sgblack@eecs.umich.edu MiscRegIndex regNum; 1828582Sgblack@eecs.umich.edu if (!msrAddrToIndex(regNum, vaddr)) 1836141Sgblack@eecs.umich.edu return new GeneralProtection(0); 1848582Sgblack@eecs.umich.edu 1856141Sgblack@eecs.umich.edu //The index is multiplied by the size of a MiscReg so that 1866141Sgblack@eecs.umich.edu //any memory dependence calculations will not see these as 1876141Sgblack@eecs.umich.edu //overlapping. 1888582Sgblack@eecs.umich.edu req->setPaddr((Addr)regNum * sizeof(MiscReg)); 1896141Sgblack@eecs.umich.edu return NoFault; 1906141Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixIO) { 1916141Sgblack@eecs.umich.edu // TODO If CPL > IOPL or in virtual mode, check the I/O permission 1926141Sgblack@eecs.umich.edu // bitmap in the TSS. 1936141Sgblack@eecs.umich.edu 1946141Sgblack@eecs.umich.edu Addr IOPort = vaddr & ~IntAddrPrefixMask; 1956141Sgblack@eecs.umich.edu // Make sure the address fits in the expected 16 bit IO address 1966141Sgblack@eecs.umich.edu // space. 1976141Sgblack@eecs.umich.edu assert(!(IOPort & ~0xFFFF)); 1986141Sgblack@eecs.umich.edu if (IOPort == 0xCF8 && req->getSize() == 4) { 1998105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 2006141Sgblack@eecs.umich.edu req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 2016141Sgblack@eecs.umich.edu } else if ((IOPort & ~mask(2)) == 0xCFC) { 2027774Sgblack@eecs.umich.edu req->setFlags(Request::UNCACHEABLE); 2036141Sgblack@eecs.umich.edu Addr configAddress = 2046141Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 2056141Sgblack@eecs.umich.edu if (bits(configAddress, 31, 31)) { 2066141Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixPciConfig | 2076141Sgblack@eecs.umich.edu mbits(configAddress, 30, 2) | 2086141Sgblack@eecs.umich.edu (IOPort & mask(2))); 2098098Sgblack@eecs.umich.edu } else { 2108098Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 2116141Sgblack@eecs.umich.edu } 2126141Sgblack@eecs.umich.edu } else { 2137774Sgblack@eecs.umich.edu req->setFlags(Request::UNCACHEABLE); 2146141Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 2156141Sgblack@eecs.umich.edu } 2166141Sgblack@eecs.umich.edu return NoFault; 2176141Sgblack@eecs.umich.edu } else { 2186141Sgblack@eecs.umich.edu panic("Access to unrecognized internal address space %#x.\n", 2196141Sgblack@eecs.umich.edu prefix); 2206141Sgblack@eecs.umich.edu } 2216141Sgblack@eecs.umich.edu} 2226141Sgblack@eecs.umich.edu 2236141Sgblack@eecs.umich.eduFault 2246023Snate@binkert.orgTLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, 2256023Snate@binkert.org Mode mode, bool &delayedResponse, bool timing) 2265086Sgblack@eecs.umich.edu{ 2276141Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 2286141Sgblack@eecs.umich.edu int seg = flags & SegmentFlagMask; 2296141Sgblack@eecs.umich.edu bool storeCheck = flags & (StoreCheck << FlagShift); 2306141Sgblack@eecs.umich.edu 2318535Sgblack@eecs.umich.edu delayedResponse = false; 2328535Sgblack@eecs.umich.edu 2336141Sgblack@eecs.umich.edu // If this is true, we're dealing with a request to a non-memory address 2346141Sgblack@eecs.umich.edu // space. 2356141Sgblack@eecs.umich.edu if (seg == SEGMENT_REG_MS) { 2366141Sgblack@eecs.umich.edu return translateInt(req, tc); 2376141Sgblack@eecs.umich.edu } 2386141Sgblack@eecs.umich.edu 2395124Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 2405140Sgblack@eecs.umich.edu DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 2415140Sgblack@eecs.umich.edu 2426141Sgblack@eecs.umich.edu HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 2435140Sgblack@eecs.umich.edu 2445140Sgblack@eecs.umich.edu // If protected mode has been enabled... 2456141Sgblack@eecs.umich.edu if (m5Reg.prot) { 2465237Sgblack@eecs.umich.edu DPRINTF(TLB, "In protected mode.\n"); 2475140Sgblack@eecs.umich.edu // If we're not in 64-bit mode, do protection/limit checks 2486141Sgblack@eecs.umich.edu if (m5Reg.mode != LongMode) { 2495237Sgblack@eecs.umich.edu DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 2505431Sgblack@eecs.umich.edu // Check for a NULL segment selector. 2516059Sgblack@eecs.umich.edu if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 2526141Sgblack@eecs.umich.edu seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 2536059Sgblack@eecs.umich.edu && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 2545431Sgblack@eecs.umich.edu return new GeneralProtection(0); 2555433Sgblack@eecs.umich.edu bool expandDown = false; 2565965Sgblack@eecs.umich.edu SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 2575433Sgblack@eecs.umich.edu if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 2586099Sgblack@eecs.umich.edu if (!attr.writable && (mode == Write || storeCheck)) 2595433Sgblack@eecs.umich.edu return new GeneralProtection(0); 2606023Snate@binkert.org if (!attr.readable && mode == Read) 2615433Sgblack@eecs.umich.edu return new GeneralProtection(0); 2625433Sgblack@eecs.umich.edu expandDown = attr.expandDown; 2635965Sgblack@eecs.umich.edu 2645433Sgblack@eecs.umich.edu } 2655140Sgblack@eecs.umich.edu Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 2665140Sgblack@eecs.umich.edu Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 2675965Sgblack@eecs.umich.edu // This assumes we're not in 64 bit mode. If we were, the default 2685965Sgblack@eecs.umich.edu // address size is 64 bits, overridable to 32. 2695965Sgblack@eecs.umich.edu int size = 32; 2705965Sgblack@eecs.umich.edu bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 2716141Sgblack@eecs.umich.edu SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR); 2725980Snate@binkert.org if ((csAttr.defaultSize && sizeOverride) || 2735980Snate@binkert.org (!csAttr.defaultSize && !sizeOverride)) 2745965Sgblack@eecs.umich.edu size = 16; 2755965Sgblack@eecs.umich.edu Addr offset = bits(vaddr - base, size-1, 0); 2765965Sgblack@eecs.umich.edu Addr endOffset = offset + req->getSize() - 1; 2775433Sgblack@eecs.umich.edu if (expandDown) { 2785237Sgblack@eecs.umich.edu DPRINTF(TLB, "Checking an expand down segment.\n"); 2795965Sgblack@eecs.umich.edu warn_once("Expand down segments are untested.\n"); 2805965Sgblack@eecs.umich.edu if (offset <= limit || endOffset <= limit) 2815965Sgblack@eecs.umich.edu return new GeneralProtection(0); 2825140Sgblack@eecs.umich.edu } else { 2835965Sgblack@eecs.umich.edu if (offset > limit || endOffset > limit) 2845965Sgblack@eecs.umich.edu return new GeneralProtection(0); 2855140Sgblack@eecs.umich.edu } 2865140Sgblack@eecs.umich.edu } 2878925Sgblack@eecs.umich.edu if (m5Reg.mode != LongMode || 2888925Sgblack@eecs.umich.edu (flags & (AddrSizeFlagBit << FlagShift))) 2898925Sgblack@eecs.umich.edu vaddr &= mask(32); 2905140Sgblack@eecs.umich.edu // If paging is enabled, do the translation. 2916141Sgblack@eecs.umich.edu if (m5Reg.paging) { 2925237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging enabled.\n"); 2935140Sgblack@eecs.umich.edu // The vaddr already has the segment base applied. 2945140Sgblack@eecs.umich.edu TlbEntry *entry = lookup(vaddr); 2955140Sgblack@eecs.umich.edu if (!entry) { 2968752Sgblack@eecs.umich.edu if (FullSystem) { 2978752Sgblack@eecs.umich.edu Fault fault = walker->start(tc, translation, req, mode); 2988752Sgblack@eecs.umich.edu if (timing || fault != NoFault) { 2998752Sgblack@eecs.umich.edu // This gets ignored in atomic mode. 3008752Sgblack@eecs.umich.edu delayedResponse = true; 3018752Sgblack@eecs.umich.edu return fault; 3028752Sgblack@eecs.umich.edu } 3038752Sgblack@eecs.umich.edu entry = lookup(vaddr); 3048752Sgblack@eecs.umich.edu assert(entry); 3058752Sgblack@eecs.umich.edu } else { 3068752Sgblack@eecs.umich.edu DPRINTF(TLB, "Handling a TLB miss for " 3078752Sgblack@eecs.umich.edu "address %#x at pc %#x.\n", 3088752Sgblack@eecs.umich.edu vaddr, tc->instAddr()); 3098752Sgblack@eecs.umich.edu 3108752Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 3118752Sgblack@eecs.umich.edu TlbEntry newEntry; 3128752Sgblack@eecs.umich.edu bool success = p->pTable->lookup(vaddr, newEntry); 3138752Sgblack@eecs.umich.edu if (!success && mode != Execute) { 3148752Sgblack@eecs.umich.edu // Check if we just need to grow the stack. 3158752Sgblack@eecs.umich.edu if (p->fixupStackFault(vaddr)) { 3168752Sgblack@eecs.umich.edu // If we did, lookup the entry for the new page. 3178752Sgblack@eecs.umich.edu success = p->pTable->lookup(vaddr, newEntry); 3188752Sgblack@eecs.umich.edu } 3198752Sgblack@eecs.umich.edu } 3208752Sgblack@eecs.umich.edu if (!success) { 3218752Sgblack@eecs.umich.edu return new PageFault(vaddr, true, mode, true, false); 3228752Sgblack@eecs.umich.edu } else { 3238752Sgblack@eecs.umich.edu Addr alignedVaddr = p->pTable->pageAlign(vaddr); 3248752Sgblack@eecs.umich.edu DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 3258752Sgblack@eecs.umich.edu newEntry.pageStart()); 3268752Sgblack@eecs.umich.edu entry = insert(alignedVaddr, newEntry); 3278752Sgblack@eecs.umich.edu } 3288752Sgblack@eecs.umich.edu DPRINTF(TLB, "Miss was serviced.\n"); 3295895Sgblack@eecs.umich.edu } 3305140Sgblack@eecs.umich.edu } 3318646Snilay@cs.wisc.edu 3328646Snilay@cs.wisc.edu DPRINTF(TLB, "Entry found with paddr %#x, " 3338646Snilay@cs.wisc.edu "doing protection checks.\n", entry->paddr); 3345895Sgblack@eecs.umich.edu // Do paging protection checks. 3356141Sgblack@eecs.umich.edu bool inUser = (m5Reg.cpl == 3 && 3365917Sgblack@eecs.umich.edu !(flags & (CPL0FlagBit << FlagShift))); 3377933Stharris@microsoft.com CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 3387933Stharris@microsoft.com bool badWrite = (!entry->writable && (inUser || cr0.wp)); 3397933Stharris@microsoft.com if ((inUser && !entry->user) || (mode == Write && badWrite)) { 3405917Sgblack@eecs.umich.edu // The page must have been present to get into the TLB in 3415917Sgblack@eecs.umich.edu // the first place. We'll assume the reserved bits are 3425917Sgblack@eecs.umich.edu // fine even though we're not checking them. 3436023Snate@binkert.org return new PageFault(vaddr, true, mode, inUser, false); 3445917Sgblack@eecs.umich.edu } 3457933Stharris@microsoft.com if (storeCheck && badWrite) { 3466099Sgblack@eecs.umich.edu // This would fault if this were a write, so return a page 3476099Sgblack@eecs.umich.edu // fault that reflects that happening. 3486099Sgblack@eecs.umich.edu return new PageFault(vaddr, true, Write, inUser, false); 3496099Sgblack@eecs.umich.edu } 3505917Sgblack@eecs.umich.edu 3518953Sgblack@eecs.umich.edu Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes)); 3525895Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 3535895Sgblack@eecs.umich.edu req->setPaddr(paddr); 3547775Sgblack@eecs.umich.edu if (entry->uncacheable) 3557775Sgblack@eecs.umich.edu req->setFlags(Request::UNCACHEABLE); 3565140Sgblack@eecs.umich.edu } else { 3575140Sgblack@eecs.umich.edu //Use the address which already has segmentation applied. 3585237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging disabled.\n"); 3595237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 3605140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 3615140Sgblack@eecs.umich.edu } 3625124Sgblack@eecs.umich.edu } else { 3635140Sgblack@eecs.umich.edu // Real mode 3645237Sgblack@eecs.umich.edu DPRINTF(TLB, "In real mode.\n"); 3655237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 3665140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 3675124Sgblack@eecs.umich.edu } 3685360Sgblack@eecs.umich.edu // Check for an access to the local APIC 3698767Sgblack@eecs.umich.edu if (FullSystem) { 3708767Sgblack@eecs.umich.edu LocalApicBase localApicBase = 3718767Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 3728767Sgblack@eecs.umich.edu Addr baseAddr = localApicBase.base * PageBytes; 3738767Sgblack@eecs.umich.edu Addr paddr = req->getPaddr(); 3748767Sgblack@eecs.umich.edu if (baseAddr <= paddr && baseAddr + PageBytes > paddr) { 3758767Sgblack@eecs.umich.edu // The Intel developer's manuals say the below restrictions apply, 3768767Sgblack@eecs.umich.edu // but the linux kernel, because of a compiler optimization, breaks 3778767Sgblack@eecs.umich.edu // them. 3788767Sgblack@eecs.umich.edu /* 3798767Sgblack@eecs.umich.edu // Check alignment 3808767Sgblack@eecs.umich.edu if (paddr & ((32/8) - 1)) 3818767Sgblack@eecs.umich.edu return new GeneralProtection(0); 3828767Sgblack@eecs.umich.edu // Check access size 3838767Sgblack@eecs.umich.edu if (req->getSize() != (32/8)) 3848767Sgblack@eecs.umich.edu return new GeneralProtection(0); 3858767Sgblack@eecs.umich.edu */ 3868767Sgblack@eecs.umich.edu // Force the access to be uncacheable. 3878767Sgblack@eecs.umich.edu req->setFlags(Request::UNCACHEABLE); 3888767Sgblack@eecs.umich.edu req->setPaddr(x86LocalAPICAddress(tc->contextId(), 3898767Sgblack@eecs.umich.edu paddr - baseAddr)); 3908767Sgblack@eecs.umich.edu } 3915360Sgblack@eecs.umich.edu } 3925086Sgblack@eecs.umich.edu return NoFault; 3938902Sandreas.hansson@arm.com} 3945086Sgblack@eecs.umich.edu 3955140Sgblack@eecs.umich.eduFault 3966023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 3975140Sgblack@eecs.umich.edu{ 3985895Sgblack@eecs.umich.edu bool delayedResponse; 3996023Snate@binkert.org return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 4005140Sgblack@eecs.umich.edu} 4015140Sgblack@eecs.umich.edu 4025894Sgblack@eecs.umich.eduvoid 4036022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 4046023Snate@binkert.org Translation *translation, Mode mode) 4055894Sgblack@eecs.umich.edu{ 4065895Sgblack@eecs.umich.edu bool delayedResponse; 4075894Sgblack@eecs.umich.edu assert(translation); 4086023Snate@binkert.org Fault fault = 4096023Snate@binkert.org TLB::translate(req, tc, translation, mode, delayedResponse, true); 4105895Sgblack@eecs.umich.edu if (!delayedResponse) 4116023Snate@binkert.org translation->finish(fault, req, tc, mode); 4125894Sgblack@eecs.umich.edu} 4135894Sgblack@eecs.umich.edu 4148888Sgeoffrey.blake@arm.comFault 4158888Sgeoffrey.blake@arm.comTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 4168888Sgeoffrey.blake@arm.com{ 4178888Sgeoffrey.blake@arm.com panic("Not implemented\n"); 4188888Sgeoffrey.blake@arm.com return NoFault; 4198888Sgeoffrey.blake@arm.com} 4208888Sgeoffrey.blake@arm.com 4217912Shestness@cs.utexas.eduWalker * 4227912Shestness@cs.utexas.eduTLB::getWalker() 4237912Shestness@cs.utexas.edu{ 4247912Shestness@cs.utexas.edu return walker; 4257912Shestness@cs.utexas.edu} 4267912Shestness@cs.utexas.edu 4275086Sgblack@eecs.umich.eduvoid 4285086Sgblack@eecs.umich.eduTLB::serialize(std::ostream &os) 4295086Sgblack@eecs.umich.edu{ 4305086Sgblack@eecs.umich.edu} 4315086Sgblack@eecs.umich.edu 4325086Sgblack@eecs.umich.eduvoid 4335086Sgblack@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 4345086Sgblack@eecs.umich.edu{ 4355086Sgblack@eecs.umich.edu} 4365086Sgblack@eecs.umich.edu 4378922Swilliam.wang@arm.comMasterPort * 4388922Swilliam.wang@arm.comTLB::getMasterPort() 4398864Snilay@cs.wisc.edu{ 4408922Swilliam.wang@arm.com return &walker->getMasterPort("port"); 4418864Snilay@cs.wisc.edu} 4428864Snilay@cs.wisc.edu 4437811Ssteve.reinhardt@amd.com} // namespace X86ISA 4445086Sgblack@eecs.umich.edu 4456022Sgblack@eecs.umich.eduX86ISA::TLB * 4466022Sgblack@eecs.umich.eduX86TLBParams::create() 4474997Sgblack@eecs.umich.edu{ 4486022Sgblack@eecs.umich.edu return new X86ISA::TLB(this); 4494997Sgblack@eecs.umich.edu} 450