tlb.cc revision 7811
14997Sgblack@eecs.umich.edu/*
25417Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
34997Sgblack@eecs.umich.edu * All rights reserved.
44997Sgblack@eecs.umich.edu *
57087Snate@binkert.org * The license below extends only to copyright in the software and shall
67087Snate@binkert.org * not be construed as granting a license to any other intellectual
77087Snate@binkert.org * property including but not limited to intellectual property relating
87087Snate@binkert.org * to a hardware implementation of the functionality of the software
97087Snate@binkert.org * licensed hereunder.  You may use the software subject to the license
107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated
117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software,
127087Snate@binkert.org * modified or unmodified, in source code or in binary form.
134997Sgblack@eecs.umich.edu *
147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without
157087Snate@binkert.org * modification, are permitted provided that the following conditions are
167087Snate@binkert.org * met: redistributions of source code must retain the above copyright
177087Snate@binkert.org * notice, this list of conditions and the following disclaimer;
187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright
197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the
207087Snate@binkert.org * documentation and/or other materials provided with the distribution;
217087Snate@binkert.org * neither the name of the copyright holders nor the names of its
224997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
237087Snate@binkert.org * this software without specific prior written permission.
244997Sgblack@eecs.umich.edu *
254997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
264997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
274997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
284997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
294997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
304997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
314997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
324997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
334997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
344997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
354997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
364997Sgblack@eecs.umich.edu *
374997Sgblack@eecs.umich.edu * Authors: Gabe Black
384997Sgblack@eecs.umich.edu */
394997Sgblack@eecs.umich.edu
404997Sgblack@eecs.umich.edu#include <cstring>
414997Sgblack@eecs.umich.edu
425086Sgblack@eecs.umich.edu#include "config/full_system.hh"
435086Sgblack@eecs.umich.edu
446315Sgblack@eecs.umich.edu#include "arch/x86/faults.hh"
455912Sgblack@eecs.umich.edu#include "arch/x86/insts/microldstop.hh"
465124Sgblack@eecs.umich.edu#include "arch/x86/pagetable.hh"
477629Sgblack@eecs.umich.edu#include "arch/x86/regs/misc.hh"
485086Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh"
495149Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh"
505086Sgblack@eecs.umich.edu#include "base/bitfield.hh"
515086Sgblack@eecs.umich.edu#include "base/trace.hh"
525237Sgblack@eecs.umich.edu#include "config/full_system.hh"
535086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh"
545086Sgblack@eecs.umich.edu#include "cpu/base.hh"
555086Sgblack@eecs.umich.edu#include "mem/packet_access.hh"
565086Sgblack@eecs.umich.edu#include "mem/request.hh"
575245Sgblack@eecs.umich.edu
585245Sgblack@eecs.umich.edu#if FULL_SYSTEM
595245Sgblack@eecs.umich.edu#include "arch/x86/pagetable_walker.hh"
605895Sgblack@eecs.umich.edu#else
615895Sgblack@eecs.umich.edu#include "mem/page_table.hh"
625895Sgblack@eecs.umich.edu#include "sim/process.hh"
635245Sgblack@eecs.umich.edu#endif
645086Sgblack@eecs.umich.edu
655086Sgblack@eecs.umich.edunamespace X86ISA {
665086Sgblack@eecs.umich.edu
675358Sgblack@eecs.umich.eduTLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
685124Sgblack@eecs.umich.edu{
695124Sgblack@eecs.umich.edu    tlb = new TlbEntry[size];
705124Sgblack@eecs.umich.edu    std::memset(tlb, 0, sizeof(TlbEntry) * size);
715124Sgblack@eecs.umich.edu
725124Sgblack@eecs.umich.edu    for (int x = 0; x < size; x++)
735124Sgblack@eecs.umich.edu        freeList.push_back(&tlb[x]);
745124Sgblack@eecs.umich.edu
755237Sgblack@eecs.umich.edu#if FULL_SYSTEM
765245Sgblack@eecs.umich.edu    walker = p->walker;
775245Sgblack@eecs.umich.edu    walker->setTLB(this);
785245Sgblack@eecs.umich.edu#endif
795236Sgblack@eecs.umich.edu}
805236Sgblack@eecs.umich.edu
815895Sgblack@eecs.umich.eduTlbEntry *
825124Sgblack@eecs.umich.eduTLB::insert(Addr vpn, TlbEntry &entry)
835124Sgblack@eecs.umich.edu{
845124Sgblack@eecs.umich.edu    //TODO Deal with conflicting entries
855124Sgblack@eecs.umich.edu
865124Sgblack@eecs.umich.edu    TlbEntry *newEntry = NULL;
875124Sgblack@eecs.umich.edu    if (!freeList.empty()) {
885124Sgblack@eecs.umich.edu        newEntry = freeList.front();
895124Sgblack@eecs.umich.edu        freeList.pop_front();
905124Sgblack@eecs.umich.edu    } else {
915124Sgblack@eecs.umich.edu        newEntry = entryList.back();
925124Sgblack@eecs.umich.edu        entryList.pop_back();
935124Sgblack@eecs.umich.edu    }
945124Sgblack@eecs.umich.edu    *newEntry = entry;
955124Sgblack@eecs.umich.edu    newEntry->vaddr = vpn;
965124Sgblack@eecs.umich.edu    entryList.push_front(newEntry);
975895Sgblack@eecs.umich.edu    return newEntry;
985124Sgblack@eecs.umich.edu}
995124Sgblack@eecs.umich.edu
1005360Sgblack@eecs.umich.eduTLB::EntryList::iterator
1015360Sgblack@eecs.umich.eduTLB::lookupIt(Addr va, bool update_lru)
1025124Sgblack@eecs.umich.edu{
1035124Sgblack@eecs.umich.edu    //TODO make this smarter at some point
1045124Sgblack@eecs.umich.edu    EntryList::iterator entry;
1055124Sgblack@eecs.umich.edu    for (entry = entryList.begin(); entry != entryList.end(); entry++) {
1065124Sgblack@eecs.umich.edu        if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
1075124Sgblack@eecs.umich.edu            DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
1085124Sgblack@eecs.umich.edu                    "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
1095124Sgblack@eecs.umich.edu            if (update_lru) {
1105360Sgblack@eecs.umich.edu                entryList.push_front(*entry);
1115124Sgblack@eecs.umich.edu                entryList.erase(entry);
1125360Sgblack@eecs.umich.edu                entry = entryList.begin();
1135124Sgblack@eecs.umich.edu            }
1145360Sgblack@eecs.umich.edu            break;
1155124Sgblack@eecs.umich.edu        }
1165124Sgblack@eecs.umich.edu    }
1175360Sgblack@eecs.umich.edu    return entry;
1185360Sgblack@eecs.umich.edu}
1195360Sgblack@eecs.umich.edu
1205360Sgblack@eecs.umich.eduTlbEntry *
1215360Sgblack@eecs.umich.eduTLB::lookup(Addr va, bool update_lru)
1225360Sgblack@eecs.umich.edu{
1235360Sgblack@eecs.umich.edu    EntryList::iterator entry = lookupIt(va, update_lru);
1245360Sgblack@eecs.umich.edu    if (entry == entryList.end())
1255360Sgblack@eecs.umich.edu        return NULL;
1265360Sgblack@eecs.umich.edu    else
1275360Sgblack@eecs.umich.edu        return *entry;
1285124Sgblack@eecs.umich.edu}
1295124Sgblack@eecs.umich.edu
1305124Sgblack@eecs.umich.eduvoid
1315124Sgblack@eecs.umich.eduTLB::invalidateAll()
1325124Sgblack@eecs.umich.edu{
1335242Sgblack@eecs.umich.edu    DPRINTF(TLB, "Invalidating all entries.\n");
1345242Sgblack@eecs.umich.edu    while (!entryList.empty()) {
1355242Sgblack@eecs.umich.edu        TlbEntry *entry = entryList.front();
1365242Sgblack@eecs.umich.edu        entryList.pop_front();
1375242Sgblack@eecs.umich.edu        freeList.push_back(entry);
1385242Sgblack@eecs.umich.edu    }
1395124Sgblack@eecs.umich.edu}
1405124Sgblack@eecs.umich.edu
1415124Sgblack@eecs.umich.eduvoid
1425357Sgblack@eecs.umich.eduTLB::setConfigAddress(uint32_t addr)
1435357Sgblack@eecs.umich.edu{
1445357Sgblack@eecs.umich.edu    configAddress = addr;
1455357Sgblack@eecs.umich.edu}
1465357Sgblack@eecs.umich.edu
1475357Sgblack@eecs.umich.eduvoid
1485124Sgblack@eecs.umich.eduTLB::invalidateNonGlobal()
1495124Sgblack@eecs.umich.edu{
1505242Sgblack@eecs.umich.edu    DPRINTF(TLB, "Invalidating all non global entries.\n");
1515242Sgblack@eecs.umich.edu    EntryList::iterator entryIt;
1525242Sgblack@eecs.umich.edu    for (entryIt = entryList.begin(); entryIt != entryList.end();) {
1535242Sgblack@eecs.umich.edu        if (!(*entryIt)->global) {
1545242Sgblack@eecs.umich.edu            freeList.push_back(*entryIt);
1555242Sgblack@eecs.umich.edu            entryList.erase(entryIt++);
1565242Sgblack@eecs.umich.edu        } else {
1575242Sgblack@eecs.umich.edu            entryIt++;
1585242Sgblack@eecs.umich.edu        }
1595242Sgblack@eecs.umich.edu    }
1605124Sgblack@eecs.umich.edu}
1615124Sgblack@eecs.umich.edu
1625124Sgblack@eecs.umich.eduvoid
1635358Sgblack@eecs.umich.eduTLB::demapPage(Addr va, uint64_t asn)
1645086Sgblack@eecs.umich.edu{
1655359Sgblack@eecs.umich.edu    EntryList::iterator entry = lookupIt(va, false);
1665359Sgblack@eecs.umich.edu    if (entry != entryList.end()) {
1675359Sgblack@eecs.umich.edu        freeList.push_back(*entry);
1685359Sgblack@eecs.umich.edu        entryList.erase(entry);
1695359Sgblack@eecs.umich.edu    }
1705086Sgblack@eecs.umich.edu}
1715086Sgblack@eecs.umich.edu
1725086Sgblack@eecs.umich.eduFault
1736141Sgblack@eecs.umich.eduTLB::translateInt(RequestPtr req, ThreadContext *tc)
1746141Sgblack@eecs.umich.edu{
1756141Sgblack@eecs.umich.edu    DPRINTF(TLB, "Addresses references internal memory.\n");
1766141Sgblack@eecs.umich.edu    Addr vaddr = req->getVaddr();
1776141Sgblack@eecs.umich.edu    Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
1786141Sgblack@eecs.umich.edu    if (prefix == IntAddrPrefixCPUID) {
1796141Sgblack@eecs.umich.edu        panic("CPUID memory space not yet implemented!\n");
1806141Sgblack@eecs.umich.edu    } else if (prefix == IntAddrPrefixMSR) {
1816141Sgblack@eecs.umich.edu        vaddr = vaddr >> 3;
1826428Ssteve.reinhardt@amd.com        req->setFlags(Request::MMAPED_IPR);
1836141Sgblack@eecs.umich.edu        Addr regNum = 0;
1846141Sgblack@eecs.umich.edu        switch (vaddr & ~IntAddrPrefixMask) {
1856141Sgblack@eecs.umich.edu          case 0x10:
1866141Sgblack@eecs.umich.edu            regNum = MISCREG_TSC;
1876141Sgblack@eecs.umich.edu            break;
1886141Sgblack@eecs.umich.edu          case 0x1B:
1896141Sgblack@eecs.umich.edu            regNum = MISCREG_APIC_BASE;
1906141Sgblack@eecs.umich.edu            break;
1916141Sgblack@eecs.umich.edu          case 0xFE:
1926141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRRCAP;
1936141Sgblack@eecs.umich.edu            break;
1946141Sgblack@eecs.umich.edu          case 0x174:
1956141Sgblack@eecs.umich.edu            regNum = MISCREG_SYSENTER_CS;
1966141Sgblack@eecs.umich.edu            break;
1976141Sgblack@eecs.umich.edu          case 0x175:
1986141Sgblack@eecs.umich.edu            regNum = MISCREG_SYSENTER_ESP;
1996141Sgblack@eecs.umich.edu            break;
2006141Sgblack@eecs.umich.edu          case 0x176:
2016141Sgblack@eecs.umich.edu            regNum = MISCREG_SYSENTER_EIP;
2026141Sgblack@eecs.umich.edu            break;
2036141Sgblack@eecs.umich.edu          case 0x179:
2046141Sgblack@eecs.umich.edu            regNum = MISCREG_MCG_CAP;
2056141Sgblack@eecs.umich.edu            break;
2066141Sgblack@eecs.umich.edu          case 0x17A:
2076141Sgblack@eecs.umich.edu            regNum = MISCREG_MCG_STATUS;
2086141Sgblack@eecs.umich.edu            break;
2096141Sgblack@eecs.umich.edu          case 0x17B:
2106141Sgblack@eecs.umich.edu            regNum = MISCREG_MCG_CTL;
2116141Sgblack@eecs.umich.edu            break;
2126141Sgblack@eecs.umich.edu          case 0x1D9:
2136141Sgblack@eecs.umich.edu            regNum = MISCREG_DEBUG_CTL_MSR;
2146141Sgblack@eecs.umich.edu            break;
2156141Sgblack@eecs.umich.edu          case 0x1DB:
2166141Sgblack@eecs.umich.edu            regNum = MISCREG_LAST_BRANCH_FROM_IP;
2176141Sgblack@eecs.umich.edu            break;
2186141Sgblack@eecs.umich.edu          case 0x1DC:
2196141Sgblack@eecs.umich.edu            regNum = MISCREG_LAST_BRANCH_TO_IP;
2206141Sgblack@eecs.umich.edu            break;
2216141Sgblack@eecs.umich.edu          case 0x1DD:
2226141Sgblack@eecs.umich.edu            regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
2236141Sgblack@eecs.umich.edu            break;
2246141Sgblack@eecs.umich.edu          case 0x1DE:
2256141Sgblack@eecs.umich.edu            regNum = MISCREG_LAST_EXCEPTION_TO_IP;
2266141Sgblack@eecs.umich.edu            break;
2276141Sgblack@eecs.umich.edu          case 0x200:
2286141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_BASE_0;
2296141Sgblack@eecs.umich.edu            break;
2306141Sgblack@eecs.umich.edu          case 0x201:
2316141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_MASK_0;
2326141Sgblack@eecs.umich.edu            break;
2336141Sgblack@eecs.umich.edu          case 0x202:
2346141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_BASE_1;
2356141Sgblack@eecs.umich.edu            break;
2366141Sgblack@eecs.umich.edu          case 0x203:
2376141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_MASK_1;
2386141Sgblack@eecs.umich.edu            break;
2396141Sgblack@eecs.umich.edu          case 0x204:
2406141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_BASE_2;
2416141Sgblack@eecs.umich.edu            break;
2426141Sgblack@eecs.umich.edu          case 0x205:
2436141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_MASK_2;
2446141Sgblack@eecs.umich.edu            break;
2456141Sgblack@eecs.umich.edu          case 0x206:
2466141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_BASE_3;
2476141Sgblack@eecs.umich.edu            break;
2486141Sgblack@eecs.umich.edu          case 0x207:
2496141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_MASK_3;
2506141Sgblack@eecs.umich.edu            break;
2516141Sgblack@eecs.umich.edu          case 0x208:
2526141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_BASE_4;
2536141Sgblack@eecs.umich.edu            break;
2546141Sgblack@eecs.umich.edu          case 0x209:
2556141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_MASK_4;
2566141Sgblack@eecs.umich.edu            break;
2576141Sgblack@eecs.umich.edu          case 0x20A:
2586141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_BASE_5;
2596141Sgblack@eecs.umich.edu            break;
2606141Sgblack@eecs.umich.edu          case 0x20B:
2616141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_MASK_5;
2626141Sgblack@eecs.umich.edu            break;
2636141Sgblack@eecs.umich.edu          case 0x20C:
2646141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_BASE_6;
2656141Sgblack@eecs.umich.edu            break;
2666141Sgblack@eecs.umich.edu          case 0x20D:
2676141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_MASK_6;
2686141Sgblack@eecs.umich.edu            break;
2696141Sgblack@eecs.umich.edu          case 0x20E:
2706141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_BASE_7;
2716141Sgblack@eecs.umich.edu            break;
2726141Sgblack@eecs.umich.edu          case 0x20F:
2736141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_PHYS_MASK_7;
2746141Sgblack@eecs.umich.edu            break;
2756141Sgblack@eecs.umich.edu          case 0x250:
2766141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_FIX_64K_00000;
2776141Sgblack@eecs.umich.edu            break;
2786141Sgblack@eecs.umich.edu          case 0x258:
2796141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_FIX_16K_80000;
2806141Sgblack@eecs.umich.edu            break;
2816141Sgblack@eecs.umich.edu          case 0x259:
2826141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_FIX_16K_A0000;
2836141Sgblack@eecs.umich.edu            break;
2846141Sgblack@eecs.umich.edu          case 0x268:
2856141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_FIX_4K_C0000;
2866141Sgblack@eecs.umich.edu            break;
2876141Sgblack@eecs.umich.edu          case 0x269:
2886141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_FIX_4K_C8000;
2896141Sgblack@eecs.umich.edu            break;
2906141Sgblack@eecs.umich.edu          case 0x26A:
2916141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_FIX_4K_D0000;
2926141Sgblack@eecs.umich.edu            break;
2936141Sgblack@eecs.umich.edu          case 0x26B:
2946141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_FIX_4K_D8000;
2956141Sgblack@eecs.umich.edu            break;
2966141Sgblack@eecs.umich.edu          case 0x26C:
2976141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_FIX_4K_E0000;
2986141Sgblack@eecs.umich.edu            break;
2996141Sgblack@eecs.umich.edu          case 0x26D:
3006141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_FIX_4K_E8000;
3016141Sgblack@eecs.umich.edu            break;
3026141Sgblack@eecs.umich.edu          case 0x26E:
3036141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_FIX_4K_F0000;
3046141Sgblack@eecs.umich.edu            break;
3056141Sgblack@eecs.umich.edu          case 0x26F:
3066141Sgblack@eecs.umich.edu            regNum = MISCREG_MTRR_FIX_4K_F8000;
3076141Sgblack@eecs.umich.edu            break;
3086141Sgblack@eecs.umich.edu          case 0x277:
3096141Sgblack@eecs.umich.edu            regNum = MISCREG_PAT;
3106141Sgblack@eecs.umich.edu            break;
3116141Sgblack@eecs.umich.edu          case 0x2FF:
3126141Sgblack@eecs.umich.edu            regNum = MISCREG_DEF_TYPE;
3136141Sgblack@eecs.umich.edu            break;
3146141Sgblack@eecs.umich.edu          case 0x400:
3156141Sgblack@eecs.umich.edu            regNum = MISCREG_MC0_CTL;
3166141Sgblack@eecs.umich.edu            break;
3176141Sgblack@eecs.umich.edu          case 0x404:
3186141Sgblack@eecs.umich.edu            regNum = MISCREG_MC1_CTL;
3196141Sgblack@eecs.umich.edu            break;
3206141Sgblack@eecs.umich.edu          case 0x408:
3216141Sgblack@eecs.umich.edu            regNum = MISCREG_MC2_CTL;
3226141Sgblack@eecs.umich.edu            break;
3236141Sgblack@eecs.umich.edu          case 0x40C:
3246141Sgblack@eecs.umich.edu            regNum = MISCREG_MC3_CTL;
3256141Sgblack@eecs.umich.edu            break;
3266141Sgblack@eecs.umich.edu          case 0x410:
3276141Sgblack@eecs.umich.edu            regNum = MISCREG_MC4_CTL;
3286141Sgblack@eecs.umich.edu            break;
3296141Sgblack@eecs.umich.edu          case 0x414:
3306141Sgblack@eecs.umich.edu            regNum = MISCREG_MC5_CTL;
3316141Sgblack@eecs.umich.edu            break;
3326141Sgblack@eecs.umich.edu          case 0x418:
3336141Sgblack@eecs.umich.edu            regNum = MISCREG_MC6_CTL;
3346141Sgblack@eecs.umich.edu            break;
3356141Sgblack@eecs.umich.edu          case 0x41C:
3366141Sgblack@eecs.umich.edu            regNum = MISCREG_MC7_CTL;
3376141Sgblack@eecs.umich.edu            break;
3386141Sgblack@eecs.umich.edu          case 0x401:
3396141Sgblack@eecs.umich.edu            regNum = MISCREG_MC0_STATUS;
3406141Sgblack@eecs.umich.edu            break;
3416141Sgblack@eecs.umich.edu          case 0x405:
3426141Sgblack@eecs.umich.edu            regNum = MISCREG_MC1_STATUS;
3436141Sgblack@eecs.umich.edu            break;
3446141Sgblack@eecs.umich.edu          case 0x409:
3456141Sgblack@eecs.umich.edu            regNum = MISCREG_MC2_STATUS;
3466141Sgblack@eecs.umich.edu            break;
3476141Sgblack@eecs.umich.edu          case 0x40D:
3486141Sgblack@eecs.umich.edu            regNum = MISCREG_MC3_STATUS;
3496141Sgblack@eecs.umich.edu            break;
3506141Sgblack@eecs.umich.edu          case 0x411:
3516141Sgblack@eecs.umich.edu            regNum = MISCREG_MC4_STATUS;
3526141Sgblack@eecs.umich.edu            break;
3536141Sgblack@eecs.umich.edu          case 0x415:
3546141Sgblack@eecs.umich.edu            regNum = MISCREG_MC5_STATUS;
3556141Sgblack@eecs.umich.edu            break;
3566141Sgblack@eecs.umich.edu          case 0x419:
3576141Sgblack@eecs.umich.edu            regNum = MISCREG_MC6_STATUS;
3586141Sgblack@eecs.umich.edu            break;
3596141Sgblack@eecs.umich.edu          case 0x41D:
3606141Sgblack@eecs.umich.edu            regNum = MISCREG_MC7_STATUS;
3616141Sgblack@eecs.umich.edu            break;
3626141Sgblack@eecs.umich.edu          case 0x402:
3636141Sgblack@eecs.umich.edu            regNum = MISCREG_MC0_ADDR;
3646141Sgblack@eecs.umich.edu            break;
3656141Sgblack@eecs.umich.edu          case 0x406:
3666141Sgblack@eecs.umich.edu            regNum = MISCREG_MC1_ADDR;
3676141Sgblack@eecs.umich.edu            break;
3686141Sgblack@eecs.umich.edu          case 0x40A:
3696141Sgblack@eecs.umich.edu            regNum = MISCREG_MC2_ADDR;
3706141Sgblack@eecs.umich.edu            break;
3716141Sgblack@eecs.umich.edu          case 0x40E:
3726141Sgblack@eecs.umich.edu            regNum = MISCREG_MC3_ADDR;
3736141Sgblack@eecs.umich.edu            break;
3746141Sgblack@eecs.umich.edu          case 0x412:
3756141Sgblack@eecs.umich.edu            regNum = MISCREG_MC4_ADDR;
3766141Sgblack@eecs.umich.edu            break;
3776141Sgblack@eecs.umich.edu          case 0x416:
3786141Sgblack@eecs.umich.edu            regNum = MISCREG_MC5_ADDR;
3796141Sgblack@eecs.umich.edu            break;
3806141Sgblack@eecs.umich.edu          case 0x41A:
3816141Sgblack@eecs.umich.edu            regNum = MISCREG_MC6_ADDR;
3826141Sgblack@eecs.umich.edu            break;
3836141Sgblack@eecs.umich.edu          case 0x41E:
3846141Sgblack@eecs.umich.edu            regNum = MISCREG_MC7_ADDR;
3856141Sgblack@eecs.umich.edu            break;
3866141Sgblack@eecs.umich.edu          case 0x403:
3876141Sgblack@eecs.umich.edu            regNum = MISCREG_MC0_MISC;
3886141Sgblack@eecs.umich.edu            break;
3896141Sgblack@eecs.umich.edu          case 0x407:
3906141Sgblack@eecs.umich.edu            regNum = MISCREG_MC1_MISC;
3916141Sgblack@eecs.umich.edu            break;
3926141Sgblack@eecs.umich.edu          case 0x40B:
3936141Sgblack@eecs.umich.edu            regNum = MISCREG_MC2_MISC;
3946141Sgblack@eecs.umich.edu            break;
3956141Sgblack@eecs.umich.edu          case 0x40F:
3966141Sgblack@eecs.umich.edu            regNum = MISCREG_MC3_MISC;
3976141Sgblack@eecs.umich.edu            break;
3986141Sgblack@eecs.umich.edu          case 0x413:
3996141Sgblack@eecs.umich.edu            regNum = MISCREG_MC4_MISC;
4006141Sgblack@eecs.umich.edu            break;
4016141Sgblack@eecs.umich.edu          case 0x417:
4026141Sgblack@eecs.umich.edu            regNum = MISCREG_MC5_MISC;
4036141Sgblack@eecs.umich.edu            break;
4046141Sgblack@eecs.umich.edu          case 0x41B:
4056141Sgblack@eecs.umich.edu            regNum = MISCREG_MC6_MISC;
4066141Sgblack@eecs.umich.edu            break;
4076141Sgblack@eecs.umich.edu          case 0x41F:
4086141Sgblack@eecs.umich.edu            regNum = MISCREG_MC7_MISC;
4096141Sgblack@eecs.umich.edu            break;
4106141Sgblack@eecs.umich.edu          case 0xC0000080:
4116141Sgblack@eecs.umich.edu            regNum = MISCREG_EFER;
4126141Sgblack@eecs.umich.edu            break;
4136141Sgblack@eecs.umich.edu          case 0xC0000081:
4146141Sgblack@eecs.umich.edu            regNum = MISCREG_STAR;
4156141Sgblack@eecs.umich.edu            break;
4166141Sgblack@eecs.umich.edu          case 0xC0000082:
4176141Sgblack@eecs.umich.edu            regNum = MISCREG_LSTAR;
4186141Sgblack@eecs.umich.edu            break;
4196141Sgblack@eecs.umich.edu          case 0xC0000083:
4206141Sgblack@eecs.umich.edu            regNum = MISCREG_CSTAR;
4216141Sgblack@eecs.umich.edu            break;
4226141Sgblack@eecs.umich.edu          case 0xC0000084:
4236141Sgblack@eecs.umich.edu            regNum = MISCREG_SF_MASK;
4246141Sgblack@eecs.umich.edu            break;
4256141Sgblack@eecs.umich.edu          case 0xC0000100:
4266141Sgblack@eecs.umich.edu            regNum = MISCREG_FS_BASE;
4276141Sgblack@eecs.umich.edu            break;
4286141Sgblack@eecs.umich.edu          case 0xC0000101:
4296141Sgblack@eecs.umich.edu            regNum = MISCREG_GS_BASE;
4306141Sgblack@eecs.umich.edu            break;
4316141Sgblack@eecs.umich.edu          case 0xC0000102:
4326141Sgblack@eecs.umich.edu            regNum = MISCREG_KERNEL_GS_BASE;
4336141Sgblack@eecs.umich.edu            break;
4346141Sgblack@eecs.umich.edu          case 0xC0000103:
4356141Sgblack@eecs.umich.edu            regNum = MISCREG_TSC_AUX;
4366141Sgblack@eecs.umich.edu            break;
4376141Sgblack@eecs.umich.edu          case 0xC0010000:
4386141Sgblack@eecs.umich.edu            regNum = MISCREG_PERF_EVT_SEL0;
4396141Sgblack@eecs.umich.edu            break;
4406141Sgblack@eecs.umich.edu          case 0xC0010001:
4416141Sgblack@eecs.umich.edu            regNum = MISCREG_PERF_EVT_SEL1;
4426141Sgblack@eecs.umich.edu            break;
4436141Sgblack@eecs.umich.edu          case 0xC0010002:
4446141Sgblack@eecs.umich.edu            regNum = MISCREG_PERF_EVT_SEL2;
4456141Sgblack@eecs.umich.edu            break;
4466141Sgblack@eecs.umich.edu          case 0xC0010003:
4476141Sgblack@eecs.umich.edu            regNum = MISCREG_PERF_EVT_SEL3;
4486141Sgblack@eecs.umich.edu            break;
4496141Sgblack@eecs.umich.edu          case 0xC0010004:
4506141Sgblack@eecs.umich.edu            regNum = MISCREG_PERF_EVT_CTR0;
4516141Sgblack@eecs.umich.edu            break;
4526141Sgblack@eecs.umich.edu          case 0xC0010005:
4536141Sgblack@eecs.umich.edu            regNum = MISCREG_PERF_EVT_CTR1;
4546141Sgblack@eecs.umich.edu            break;
4556141Sgblack@eecs.umich.edu          case 0xC0010006:
4566141Sgblack@eecs.umich.edu            regNum = MISCREG_PERF_EVT_CTR2;
4576141Sgblack@eecs.umich.edu            break;
4586141Sgblack@eecs.umich.edu          case 0xC0010007:
4596141Sgblack@eecs.umich.edu            regNum = MISCREG_PERF_EVT_CTR3;
4606141Sgblack@eecs.umich.edu            break;
4616141Sgblack@eecs.umich.edu          case 0xC0010010:
4626141Sgblack@eecs.umich.edu            regNum = MISCREG_SYSCFG;
4636141Sgblack@eecs.umich.edu            break;
4646141Sgblack@eecs.umich.edu          case 0xC0010016:
4656141Sgblack@eecs.umich.edu            regNum = MISCREG_IORR_BASE0;
4666141Sgblack@eecs.umich.edu            break;
4676141Sgblack@eecs.umich.edu          case 0xC0010017:
4686141Sgblack@eecs.umich.edu            regNum = MISCREG_IORR_BASE1;
4696141Sgblack@eecs.umich.edu            break;
4706141Sgblack@eecs.umich.edu          case 0xC0010018:
4716141Sgblack@eecs.umich.edu            regNum = MISCREG_IORR_MASK0;
4726141Sgblack@eecs.umich.edu            break;
4736141Sgblack@eecs.umich.edu          case 0xC0010019:
4746141Sgblack@eecs.umich.edu            regNum = MISCREG_IORR_MASK1;
4756141Sgblack@eecs.umich.edu            break;
4766141Sgblack@eecs.umich.edu          case 0xC001001A:
4776141Sgblack@eecs.umich.edu            regNum = MISCREG_TOP_MEM;
4786141Sgblack@eecs.umich.edu            break;
4796141Sgblack@eecs.umich.edu          case 0xC001001D:
4806141Sgblack@eecs.umich.edu            regNum = MISCREG_TOP_MEM2;
4816141Sgblack@eecs.umich.edu            break;
4826141Sgblack@eecs.umich.edu          case 0xC0010114:
4836141Sgblack@eecs.umich.edu            regNum = MISCREG_VM_CR;
4846141Sgblack@eecs.umich.edu            break;
4856141Sgblack@eecs.umich.edu          case 0xC0010115:
4866141Sgblack@eecs.umich.edu            regNum = MISCREG_IGNNE;
4876141Sgblack@eecs.umich.edu            break;
4886141Sgblack@eecs.umich.edu          case 0xC0010116:
4896141Sgblack@eecs.umich.edu            regNum = MISCREG_SMM_CTL;
4906141Sgblack@eecs.umich.edu            break;
4916141Sgblack@eecs.umich.edu          case 0xC0010117:
4926141Sgblack@eecs.umich.edu            regNum = MISCREG_VM_HSAVE_PA;
4936141Sgblack@eecs.umich.edu            break;
4946141Sgblack@eecs.umich.edu          default:
4956141Sgblack@eecs.umich.edu            return new GeneralProtection(0);
4966141Sgblack@eecs.umich.edu        }
4976141Sgblack@eecs.umich.edu        //The index is multiplied by the size of a MiscReg so that
4986141Sgblack@eecs.umich.edu        //any memory dependence calculations will not see these as
4996141Sgblack@eecs.umich.edu        //overlapping.
5006141Sgblack@eecs.umich.edu        req->setPaddr(regNum * sizeof(MiscReg));
5016141Sgblack@eecs.umich.edu        return NoFault;
5026141Sgblack@eecs.umich.edu    } else if (prefix == IntAddrPrefixIO) {
5036141Sgblack@eecs.umich.edu        // TODO If CPL > IOPL or in virtual mode, check the I/O permission
5046141Sgblack@eecs.umich.edu        // bitmap in the TSS.
5056141Sgblack@eecs.umich.edu
5066141Sgblack@eecs.umich.edu        Addr IOPort = vaddr & ~IntAddrPrefixMask;
5076141Sgblack@eecs.umich.edu        // Make sure the address fits in the expected 16 bit IO address
5086141Sgblack@eecs.umich.edu        // space.
5096141Sgblack@eecs.umich.edu        assert(!(IOPort & ~0xFFFF));
5106141Sgblack@eecs.umich.edu        if (IOPort == 0xCF8 && req->getSize() == 4) {
5116428Ssteve.reinhardt@amd.com            req->setFlags(Request::MMAPED_IPR);
5126141Sgblack@eecs.umich.edu            req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
5136141Sgblack@eecs.umich.edu        } else if ((IOPort & ~mask(2)) == 0xCFC) {
5147774Sgblack@eecs.umich.edu            req->setFlags(Request::UNCACHEABLE);
5156141Sgblack@eecs.umich.edu            Addr configAddress =
5166141Sgblack@eecs.umich.edu                tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
5176141Sgblack@eecs.umich.edu            if (bits(configAddress, 31, 31)) {
5186141Sgblack@eecs.umich.edu                req->setPaddr(PhysAddrPrefixPciConfig |
5196141Sgblack@eecs.umich.edu                        mbits(configAddress, 30, 2) |
5206141Sgblack@eecs.umich.edu                        (IOPort & mask(2)));
5216141Sgblack@eecs.umich.edu            }
5226141Sgblack@eecs.umich.edu        } else {
5237774Sgblack@eecs.umich.edu            req->setFlags(Request::UNCACHEABLE);
5246141Sgblack@eecs.umich.edu            req->setPaddr(PhysAddrPrefixIO | IOPort);
5256141Sgblack@eecs.umich.edu        }
5266141Sgblack@eecs.umich.edu        return NoFault;
5276141Sgblack@eecs.umich.edu    } else {
5286141Sgblack@eecs.umich.edu        panic("Access to unrecognized internal address space %#x.\n",
5296141Sgblack@eecs.umich.edu                prefix);
5306141Sgblack@eecs.umich.edu    }
5316141Sgblack@eecs.umich.edu}
5326141Sgblack@eecs.umich.edu
5336141Sgblack@eecs.umich.eduFault
5346023Snate@binkert.orgTLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
5356023Snate@binkert.org        Mode mode, bool &delayedResponse, bool timing)
5365086Sgblack@eecs.umich.edu{
5376141Sgblack@eecs.umich.edu    uint32_t flags = req->getFlags();
5386141Sgblack@eecs.umich.edu    int seg = flags & SegmentFlagMask;
5396141Sgblack@eecs.umich.edu    bool storeCheck = flags & (StoreCheck << FlagShift);
5406141Sgblack@eecs.umich.edu
5416141Sgblack@eecs.umich.edu    // If this is true, we're dealing with a request to a non-memory address
5426141Sgblack@eecs.umich.edu    // space.
5436141Sgblack@eecs.umich.edu    if (seg == SEGMENT_REG_MS) {
5446141Sgblack@eecs.umich.edu        return translateInt(req, tc);
5456141Sgblack@eecs.umich.edu    }
5466141Sgblack@eecs.umich.edu
5475895Sgblack@eecs.umich.edu    delayedResponse = false;
5485124Sgblack@eecs.umich.edu    Addr vaddr = req->getVaddr();
5495140Sgblack@eecs.umich.edu    DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
5505140Sgblack@eecs.umich.edu
5516141Sgblack@eecs.umich.edu    HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
5525140Sgblack@eecs.umich.edu
5535140Sgblack@eecs.umich.edu    // If protected mode has been enabled...
5546141Sgblack@eecs.umich.edu    if (m5Reg.prot) {
5555237Sgblack@eecs.umich.edu        DPRINTF(TLB, "In protected mode.\n");
5565140Sgblack@eecs.umich.edu        // If we're not in 64-bit mode, do protection/limit checks
5576141Sgblack@eecs.umich.edu        if (m5Reg.mode != LongMode) {
5585237Sgblack@eecs.umich.edu            DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
5595431Sgblack@eecs.umich.edu            // Check for a NULL segment selector.
5606059Sgblack@eecs.umich.edu            if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
5616141Sgblack@eecs.umich.edu                        seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
5626059Sgblack@eecs.umich.edu                    && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
5635431Sgblack@eecs.umich.edu                return new GeneralProtection(0);
5645433Sgblack@eecs.umich.edu            bool expandDown = false;
5655965Sgblack@eecs.umich.edu            SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
5665433Sgblack@eecs.umich.edu            if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
5676099Sgblack@eecs.umich.edu                if (!attr.writable && (mode == Write || storeCheck))
5685433Sgblack@eecs.umich.edu                    return new GeneralProtection(0);
5696023Snate@binkert.org                if (!attr.readable && mode == Read)
5705433Sgblack@eecs.umich.edu                    return new GeneralProtection(0);
5715433Sgblack@eecs.umich.edu                expandDown = attr.expandDown;
5725965Sgblack@eecs.umich.edu
5735433Sgblack@eecs.umich.edu            }
5745140Sgblack@eecs.umich.edu            Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
5755140Sgblack@eecs.umich.edu            Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
5765965Sgblack@eecs.umich.edu            // This assumes we're not in 64 bit mode. If we were, the default
5775965Sgblack@eecs.umich.edu            // address size is 64 bits, overridable to 32.
5785965Sgblack@eecs.umich.edu            int size = 32;
5795965Sgblack@eecs.umich.edu            bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
5806141Sgblack@eecs.umich.edu            SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
5815980Snate@binkert.org            if ((csAttr.defaultSize && sizeOverride) ||
5825980Snate@binkert.org                    (!csAttr.defaultSize && !sizeOverride))
5835965Sgblack@eecs.umich.edu                size = 16;
5845965Sgblack@eecs.umich.edu            Addr offset = bits(vaddr - base, size-1, 0);
5855965Sgblack@eecs.umich.edu            Addr endOffset = offset + req->getSize() - 1;
5865433Sgblack@eecs.umich.edu            if (expandDown) {
5875237Sgblack@eecs.umich.edu                DPRINTF(TLB, "Checking an expand down segment.\n");
5885965Sgblack@eecs.umich.edu                warn_once("Expand down segments are untested.\n");
5895965Sgblack@eecs.umich.edu                if (offset <= limit || endOffset <= limit)
5905965Sgblack@eecs.umich.edu                    return new GeneralProtection(0);
5915140Sgblack@eecs.umich.edu            } else {
5925965Sgblack@eecs.umich.edu                if (offset > limit || endOffset > limit)
5935965Sgblack@eecs.umich.edu                    return new GeneralProtection(0);
5945140Sgblack@eecs.umich.edu            }
5955140Sgblack@eecs.umich.edu        }
5965140Sgblack@eecs.umich.edu        // If paging is enabled, do the translation.
5976141Sgblack@eecs.umich.edu        if (m5Reg.paging) {
5985237Sgblack@eecs.umich.edu            DPRINTF(TLB, "Paging enabled.\n");
5995140Sgblack@eecs.umich.edu            // The vaddr already has the segment base applied.
6005140Sgblack@eecs.umich.edu            TlbEntry *entry = lookup(vaddr);
6015140Sgblack@eecs.umich.edu            if (!entry) {
6025895Sgblack@eecs.umich.edu#if FULL_SYSTEM
6036023Snate@binkert.org                Fault fault = walker->start(tc, translation, req, mode);
6045895Sgblack@eecs.umich.edu                if (timing || fault != NoFault) {
6055895Sgblack@eecs.umich.edu                    // This gets ignored in atomic mode.
6065895Sgblack@eecs.umich.edu                    delayedResponse = true;
6075895Sgblack@eecs.umich.edu                    return fault;
6085895Sgblack@eecs.umich.edu                }
6095895Sgblack@eecs.umich.edu                entry = lookup(vaddr);
6105895Sgblack@eecs.umich.edu                assert(entry);
6115895Sgblack@eecs.umich.edu#else
6125895Sgblack@eecs.umich.edu                DPRINTF(TLB, "Handling a TLB miss for "
6135895Sgblack@eecs.umich.edu                        "address %#x at pc %#x.\n",
6147720Sgblack@eecs.umich.edu                        vaddr, tc->instAddr());
6155895Sgblack@eecs.umich.edu
6165895Sgblack@eecs.umich.edu                Process *p = tc->getProcessPtr();
6175895Sgblack@eecs.umich.edu                TlbEntry newEntry;
6185895Sgblack@eecs.umich.edu                bool success = p->pTable->lookup(vaddr, newEntry);
6196737Sgblack@eecs.umich.edu                if (!success && mode != Execute) {
6205895Sgblack@eecs.umich.edu                    p->checkAndAllocNextPage(vaddr);
6215895Sgblack@eecs.umich.edu                    success = p->pTable->lookup(vaddr, newEntry);
6225895Sgblack@eecs.umich.edu                }
6236737Sgblack@eecs.umich.edu                if (!success) {
6247625Sgblack@eecs.umich.edu                    return new PageFault(vaddr, true, mode, true, false);
6255895Sgblack@eecs.umich.edu                } else {
6265895Sgblack@eecs.umich.edu                    Addr alignedVaddr = p->pTable->pageAlign(vaddr);
6275895Sgblack@eecs.umich.edu                    DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
6285895Sgblack@eecs.umich.edu                            newEntry.pageStart());
6295895Sgblack@eecs.umich.edu                    entry = insert(alignedVaddr, newEntry);
6305895Sgblack@eecs.umich.edu                }
6315895Sgblack@eecs.umich.edu                DPRINTF(TLB, "Miss was serviced.\n");
6325895Sgblack@eecs.umich.edu#endif
6335140Sgblack@eecs.umich.edu            }
6345895Sgblack@eecs.umich.edu            // Do paging protection checks.
6356141Sgblack@eecs.umich.edu            bool inUser = (m5Reg.cpl == 3 &&
6365917Sgblack@eecs.umich.edu                    !(flags & (CPL0FlagBit << FlagShift)));
6375980Snate@binkert.org            if ((inUser && !entry->user) ||
6386023Snate@binkert.org                (mode == Write && !entry->writable)) {
6395917Sgblack@eecs.umich.edu                // The page must have been present to get into the TLB in
6405917Sgblack@eecs.umich.edu                // the first place. We'll assume the reserved bits are
6415917Sgblack@eecs.umich.edu                // fine even though we're not checking them.
6426023Snate@binkert.org                return new PageFault(vaddr, true, mode, inUser, false);
6435917Sgblack@eecs.umich.edu            }
6446099Sgblack@eecs.umich.edu            if (storeCheck && !entry->writable) {
6456099Sgblack@eecs.umich.edu                // This would fault if this were a write, so return a page
6466099Sgblack@eecs.umich.edu                // fault that reflects that happening.
6476099Sgblack@eecs.umich.edu                return new PageFault(vaddr, true, Write, inUser, false);
6486099Sgblack@eecs.umich.edu            }
6495917Sgblack@eecs.umich.edu
6505917Sgblack@eecs.umich.edu
6515895Sgblack@eecs.umich.edu            DPRINTF(TLB, "Entry found with paddr %#x, "
6525895Sgblack@eecs.umich.edu                    "doing protection checks.\n", entry->paddr);
6535895Sgblack@eecs.umich.edu            Addr paddr = entry->paddr | (vaddr & (entry->size-1));
6545895Sgblack@eecs.umich.edu            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
6555895Sgblack@eecs.umich.edu            req->setPaddr(paddr);
6567775Sgblack@eecs.umich.edu            if (entry->uncacheable)
6577775Sgblack@eecs.umich.edu                req->setFlags(Request::UNCACHEABLE);
6585140Sgblack@eecs.umich.edu        } else {
6595140Sgblack@eecs.umich.edu            //Use the address which already has segmentation applied.
6605237Sgblack@eecs.umich.edu            DPRINTF(TLB, "Paging disabled.\n");
6615237Sgblack@eecs.umich.edu            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
6625140Sgblack@eecs.umich.edu            req->setPaddr(vaddr);
6635140Sgblack@eecs.umich.edu        }
6645124Sgblack@eecs.umich.edu    } else {
6655140Sgblack@eecs.umich.edu        // Real mode
6665237Sgblack@eecs.umich.edu        DPRINTF(TLB, "In real mode.\n");
6675237Sgblack@eecs.umich.edu        DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
6685140Sgblack@eecs.umich.edu        req->setPaddr(vaddr);
6695124Sgblack@eecs.umich.edu    }
6705360Sgblack@eecs.umich.edu    // Check for an access to the local APIC
6715374Sgblack@eecs.umich.edu#if FULL_SYSTEM
6725360Sgblack@eecs.umich.edu    LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
6735648Sgblack@eecs.umich.edu    Addr baseAddr = localApicBase.base * PageBytes;
6745360Sgblack@eecs.umich.edu    Addr paddr = req->getPaddr();
6755648Sgblack@eecs.umich.edu    if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
6765417Sgblack@eecs.umich.edu        // The Intel developer's manuals say the below restrictions apply,
6775417Sgblack@eecs.umich.edu        // but the linux kernel, because of a compiler optimization, breaks
6785417Sgblack@eecs.umich.edu        // them.
6795417Sgblack@eecs.umich.edu        /*
6805360Sgblack@eecs.umich.edu        // Check alignment
6815360Sgblack@eecs.umich.edu        if (paddr & ((32/8) - 1))
6825360Sgblack@eecs.umich.edu            return new GeneralProtection(0);
6835360Sgblack@eecs.umich.edu        // Check access size
6845360Sgblack@eecs.umich.edu        if (req->getSize() != (32/8))
6855360Sgblack@eecs.umich.edu            return new GeneralProtection(0);
6865417Sgblack@eecs.umich.edu        */
6875648Sgblack@eecs.umich.edu        // Force the access to be uncacheable.
6885736Snate@binkert.org        req->setFlags(Request::UNCACHEABLE);
6895714Shsul@eecs.umich.edu        req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
6905360Sgblack@eecs.umich.edu    }
6915374Sgblack@eecs.umich.edu#endif
6925086Sgblack@eecs.umich.edu    return NoFault;
6935086Sgblack@eecs.umich.edu};
6945086Sgblack@eecs.umich.edu
6955140Sgblack@eecs.umich.eduFault
6966023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
6975140Sgblack@eecs.umich.edu{
6985895Sgblack@eecs.umich.edu    bool delayedResponse;
6996023Snate@binkert.org    return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
7005140Sgblack@eecs.umich.edu}
7015140Sgblack@eecs.umich.edu
7025894Sgblack@eecs.umich.eduvoid
7036022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc,
7046023Snate@binkert.org        Translation *translation, Mode mode)
7055894Sgblack@eecs.umich.edu{
7065895Sgblack@eecs.umich.edu    bool delayedResponse;
7075894Sgblack@eecs.umich.edu    assert(translation);
7086023Snate@binkert.org    Fault fault =
7096023Snate@binkert.org        TLB::translate(req, tc, translation, mode, delayedResponse, true);
7105895Sgblack@eecs.umich.edu    if (!delayedResponse)
7116023Snate@binkert.org        translation->finish(fault, req, tc, mode);
7125894Sgblack@eecs.umich.edu}
7135894Sgblack@eecs.umich.edu
7145086Sgblack@eecs.umich.edu#if FULL_SYSTEM
7155086Sgblack@eecs.umich.edu
7165086Sgblack@eecs.umich.eduTick
7176022Sgblack@eecs.umich.eduTLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
7185086Sgblack@eecs.umich.edu{
7195100Ssaidi@eecs.umich.edu    return tc->getCpuPtr()->ticks(1);
7205086Sgblack@eecs.umich.edu}
7215086Sgblack@eecs.umich.edu
7225086Sgblack@eecs.umich.eduTick
7236022Sgblack@eecs.umich.eduTLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
7245086Sgblack@eecs.umich.edu{
7255100Ssaidi@eecs.umich.edu    return tc->getCpuPtr()->ticks(1);
7265086Sgblack@eecs.umich.edu}
7275086Sgblack@eecs.umich.edu
7285086Sgblack@eecs.umich.edu#endif
7295086Sgblack@eecs.umich.edu
7305086Sgblack@eecs.umich.eduvoid
7315086Sgblack@eecs.umich.eduTLB::serialize(std::ostream &os)
7325086Sgblack@eecs.umich.edu{
7335086Sgblack@eecs.umich.edu}
7345086Sgblack@eecs.umich.edu
7355086Sgblack@eecs.umich.eduvoid
7365086Sgblack@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string &section)
7375086Sgblack@eecs.umich.edu{
7385086Sgblack@eecs.umich.edu}
7395086Sgblack@eecs.umich.edu
7407811Ssteve.reinhardt@amd.com} // namespace X86ISA
7415086Sgblack@eecs.umich.edu
7426022Sgblack@eecs.umich.eduX86ISA::TLB *
7436022Sgblack@eecs.umich.eduX86TLBParams::create()
7444997Sgblack@eecs.umich.edu{
7456022Sgblack@eecs.umich.edu    return new X86ISA::TLB(this);
7464997Sgblack@eecs.umich.edu}
747