tlb.cc revision 6059
14997Sgblack@eecs.umich.edu/*
25417Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
34997Sgblack@eecs.umich.edu * All rights reserved.
44997Sgblack@eecs.umich.edu *
54997Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms,
64997Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the
74997Sgblack@eecs.umich.edu * following conditions are met:
84997Sgblack@eecs.umich.edu *
94997Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any
104997Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary
114997Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use.  Illustrative
124997Sgblack@eecs.umich.edu * examples of non-commercial use are academic research, personal study,
134997Sgblack@eecs.umich.edu * teaching, education and corporate research & development.
144997Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for
154997Sgblack@eecs.umich.edu * commercial advantage and providing services using the software for
164997Sgblack@eecs.umich.edu * commercial advantage.
174997Sgblack@eecs.umich.edu *
184997Sgblack@eecs.umich.edu * If you wish to use this software or functionality therein that may be
194997Sgblack@eecs.umich.edu * covered by patents for commercial use, please contact:
204997Sgblack@eecs.umich.edu *     Director of Intellectual Property Licensing
214997Sgblack@eecs.umich.edu *     Office of Strategy and Technology
224997Sgblack@eecs.umich.edu *     Hewlett-Packard Company
234997Sgblack@eecs.umich.edu *     1501 Page Mill Road
244997Sgblack@eecs.umich.edu *     Palo Alto, California  94304
254997Sgblack@eecs.umich.edu *
264997Sgblack@eecs.umich.edu * Redistributions of source code must retain the above copyright notice,
274997Sgblack@eecs.umich.edu * this list of conditions and the following disclaimer.  Redistributions
284997Sgblack@eecs.umich.edu * in binary form must reproduce the above copyright notice, this list of
294997Sgblack@eecs.umich.edu * conditions and the following disclaimer in the documentation and/or
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314997Sgblack@eecs.umich.edu * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
324997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
334997Sgblack@eecs.umich.edu * this software without specific prior written permission.  No right of
344997Sgblack@eecs.umich.edu * sublicense is granted herewith.  Derivatives of the software and
354997Sgblack@eecs.umich.edu * output created using the software may be prepared, but only for
364997Sgblack@eecs.umich.edu * Non-Commercial Uses.  Derivatives of the software may be shared with
374997Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of
384997Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions;
394997Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright
404997Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where
414997Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below.
424997Sgblack@eecs.umich.edu *
434997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
444997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
454997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
464997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
474997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
484997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
494997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
504997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
514997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
534997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
544997Sgblack@eecs.umich.edu *
554997Sgblack@eecs.umich.edu * Authors: Gabe Black
564997Sgblack@eecs.umich.edu */
574997Sgblack@eecs.umich.edu
584997Sgblack@eecs.umich.edu#include <cstring>
594997Sgblack@eecs.umich.edu
605086Sgblack@eecs.umich.edu#include "config/full_system.hh"
615086Sgblack@eecs.umich.edu
625912Sgblack@eecs.umich.edu#include "arch/x86/insts/microldstop.hh"
635124Sgblack@eecs.umich.edu#include "arch/x86/pagetable.hh"
645086Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh"
655149Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh"
665086Sgblack@eecs.umich.edu#include "base/bitfield.hh"
675086Sgblack@eecs.umich.edu#include "base/trace.hh"
685237Sgblack@eecs.umich.edu#include "config/full_system.hh"
695086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh"
705086Sgblack@eecs.umich.edu#include "cpu/base.hh"
715086Sgblack@eecs.umich.edu#include "mem/packet_access.hh"
725086Sgblack@eecs.umich.edu#include "mem/request.hh"
735245Sgblack@eecs.umich.edu
745245Sgblack@eecs.umich.edu#if FULL_SYSTEM
755245Sgblack@eecs.umich.edu#include "arch/x86/pagetable_walker.hh"
765895Sgblack@eecs.umich.edu#else
775895Sgblack@eecs.umich.edu#include "mem/page_table.hh"
785895Sgblack@eecs.umich.edu#include "sim/process.hh"
795245Sgblack@eecs.umich.edu#endif
805086Sgblack@eecs.umich.edu
815086Sgblack@eecs.umich.edunamespace X86ISA {
825086Sgblack@eecs.umich.edu
835358Sgblack@eecs.umich.eduTLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
845124Sgblack@eecs.umich.edu{
855124Sgblack@eecs.umich.edu    tlb = new TlbEntry[size];
865124Sgblack@eecs.umich.edu    std::memset(tlb, 0, sizeof(TlbEntry) * size);
875124Sgblack@eecs.umich.edu
885124Sgblack@eecs.umich.edu    for (int x = 0; x < size; x++)
895124Sgblack@eecs.umich.edu        freeList.push_back(&tlb[x]);
905124Sgblack@eecs.umich.edu
915237Sgblack@eecs.umich.edu#if FULL_SYSTEM
925245Sgblack@eecs.umich.edu    walker = p->walker;
935245Sgblack@eecs.umich.edu    walker->setTLB(this);
945245Sgblack@eecs.umich.edu#endif
955236Sgblack@eecs.umich.edu}
965236Sgblack@eecs.umich.edu
975895Sgblack@eecs.umich.eduTlbEntry *
985124Sgblack@eecs.umich.eduTLB::insert(Addr vpn, TlbEntry &entry)
995124Sgblack@eecs.umich.edu{
1005124Sgblack@eecs.umich.edu    //TODO Deal with conflicting entries
1015124Sgblack@eecs.umich.edu
1025124Sgblack@eecs.umich.edu    TlbEntry *newEntry = NULL;
1035124Sgblack@eecs.umich.edu    if (!freeList.empty()) {
1045124Sgblack@eecs.umich.edu        newEntry = freeList.front();
1055124Sgblack@eecs.umich.edu        freeList.pop_front();
1065124Sgblack@eecs.umich.edu    } else {
1075124Sgblack@eecs.umich.edu        newEntry = entryList.back();
1085124Sgblack@eecs.umich.edu        entryList.pop_back();
1095124Sgblack@eecs.umich.edu    }
1105124Sgblack@eecs.umich.edu    *newEntry = entry;
1115124Sgblack@eecs.umich.edu    newEntry->vaddr = vpn;
1125124Sgblack@eecs.umich.edu    entryList.push_front(newEntry);
1135895Sgblack@eecs.umich.edu    return newEntry;
1145124Sgblack@eecs.umich.edu}
1155124Sgblack@eecs.umich.edu
1165360Sgblack@eecs.umich.eduTLB::EntryList::iterator
1175360Sgblack@eecs.umich.eduTLB::lookupIt(Addr va, bool update_lru)
1185124Sgblack@eecs.umich.edu{
1195124Sgblack@eecs.umich.edu    //TODO make this smarter at some point
1205124Sgblack@eecs.umich.edu    EntryList::iterator entry;
1215124Sgblack@eecs.umich.edu    for (entry = entryList.begin(); entry != entryList.end(); entry++) {
1225124Sgblack@eecs.umich.edu        if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
1235124Sgblack@eecs.umich.edu            DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
1245124Sgblack@eecs.umich.edu                    "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
1255124Sgblack@eecs.umich.edu            if (update_lru) {
1265360Sgblack@eecs.umich.edu                entryList.push_front(*entry);
1275124Sgblack@eecs.umich.edu                entryList.erase(entry);
1285360Sgblack@eecs.umich.edu                entry = entryList.begin();
1295124Sgblack@eecs.umich.edu            }
1305360Sgblack@eecs.umich.edu            break;
1315124Sgblack@eecs.umich.edu        }
1325124Sgblack@eecs.umich.edu    }
1335360Sgblack@eecs.umich.edu    return entry;
1345360Sgblack@eecs.umich.edu}
1355360Sgblack@eecs.umich.edu
1365360Sgblack@eecs.umich.eduTlbEntry *
1375360Sgblack@eecs.umich.eduTLB::lookup(Addr va, bool update_lru)
1385360Sgblack@eecs.umich.edu{
1395360Sgblack@eecs.umich.edu    EntryList::iterator entry = lookupIt(va, update_lru);
1405360Sgblack@eecs.umich.edu    if (entry == entryList.end())
1415360Sgblack@eecs.umich.edu        return NULL;
1425360Sgblack@eecs.umich.edu    else
1435360Sgblack@eecs.umich.edu        return *entry;
1445124Sgblack@eecs.umich.edu}
1455124Sgblack@eecs.umich.edu
1465124Sgblack@eecs.umich.eduvoid
1475124Sgblack@eecs.umich.eduTLB::invalidateAll()
1485124Sgblack@eecs.umich.edu{
1495242Sgblack@eecs.umich.edu    DPRINTF(TLB, "Invalidating all entries.\n");
1505242Sgblack@eecs.umich.edu    while (!entryList.empty()) {
1515242Sgblack@eecs.umich.edu        TlbEntry *entry = entryList.front();
1525242Sgblack@eecs.umich.edu        entryList.pop_front();
1535242Sgblack@eecs.umich.edu        freeList.push_back(entry);
1545242Sgblack@eecs.umich.edu    }
1555124Sgblack@eecs.umich.edu}
1565124Sgblack@eecs.umich.edu
1575124Sgblack@eecs.umich.eduvoid
1585357Sgblack@eecs.umich.eduTLB::setConfigAddress(uint32_t addr)
1595357Sgblack@eecs.umich.edu{
1605357Sgblack@eecs.umich.edu    configAddress = addr;
1615357Sgblack@eecs.umich.edu}
1625357Sgblack@eecs.umich.edu
1635357Sgblack@eecs.umich.eduvoid
1645124Sgblack@eecs.umich.eduTLB::invalidateNonGlobal()
1655124Sgblack@eecs.umich.edu{
1665242Sgblack@eecs.umich.edu    DPRINTF(TLB, "Invalidating all non global entries.\n");
1675242Sgblack@eecs.umich.edu    EntryList::iterator entryIt;
1685242Sgblack@eecs.umich.edu    for (entryIt = entryList.begin(); entryIt != entryList.end();) {
1695242Sgblack@eecs.umich.edu        if (!(*entryIt)->global) {
1705242Sgblack@eecs.umich.edu            freeList.push_back(*entryIt);
1715242Sgblack@eecs.umich.edu            entryList.erase(entryIt++);
1725242Sgblack@eecs.umich.edu        } else {
1735242Sgblack@eecs.umich.edu            entryIt++;
1745242Sgblack@eecs.umich.edu        }
1755242Sgblack@eecs.umich.edu    }
1765124Sgblack@eecs.umich.edu}
1775124Sgblack@eecs.umich.edu
1785124Sgblack@eecs.umich.eduvoid
1795358Sgblack@eecs.umich.eduTLB::demapPage(Addr va, uint64_t asn)
1805086Sgblack@eecs.umich.edu{
1815359Sgblack@eecs.umich.edu    EntryList::iterator entry = lookupIt(va, false);
1825359Sgblack@eecs.umich.edu    if (entry != entryList.end()) {
1835359Sgblack@eecs.umich.edu        freeList.push_back(*entry);
1845359Sgblack@eecs.umich.edu        entryList.erase(entry);
1855359Sgblack@eecs.umich.edu    }
1865086Sgblack@eecs.umich.edu}
1875086Sgblack@eecs.umich.edu
1885086Sgblack@eecs.umich.eduFault
1896023Snate@binkert.orgTLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
1906023Snate@binkert.org        Mode mode, bool &delayedResponse, bool timing)
1915086Sgblack@eecs.umich.edu{
1925895Sgblack@eecs.umich.edu    delayedResponse = false;
1935124Sgblack@eecs.umich.edu    Addr vaddr = req->getVaddr();
1945140Sgblack@eecs.umich.edu    DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
1955124Sgblack@eecs.umich.edu    uint32_t flags = req->getFlags();
1965124Sgblack@eecs.umich.edu    bool storeCheck = flags & StoreCheck;
1975140Sgblack@eecs.umich.edu
1985912Sgblack@eecs.umich.edu    int seg = flags & SegmentFlagMask;
1995124Sgblack@eecs.umich.edu
2005124Sgblack@eecs.umich.edu    //XXX Junk code to surpress the warning
2015149Sgblack@eecs.umich.edu    if (storeCheck);
2025149Sgblack@eecs.umich.edu
2035149Sgblack@eecs.umich.edu    // If this is true, we're dealing with a request to read an internal
2045149Sgblack@eecs.umich.edu    // value.
2055294Sgblack@eecs.umich.edu    if (seg == SEGMENT_REG_MS) {
2065243Sgblack@eecs.umich.edu        DPRINTF(TLB, "Addresses references internal memory.\n");
2075418Sgblack@eecs.umich.edu        Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
2085149Sgblack@eecs.umich.edu        if (prefix == IntAddrPrefixCPUID) {
2095149Sgblack@eecs.umich.edu            panic("CPUID memory space not yet implemented!\n");
2105149Sgblack@eecs.umich.edu        } else if (prefix == IntAddrPrefixMSR) {
2115418Sgblack@eecs.umich.edu            vaddr = vaddr >> 3;
2125149Sgblack@eecs.umich.edu            req->setMmapedIpr(true);
2135149Sgblack@eecs.umich.edu            Addr regNum = 0;
2145149Sgblack@eecs.umich.edu            switch (vaddr & ~IntAddrPrefixMask) {
2155149Sgblack@eecs.umich.edu              case 0x10:
2165149Sgblack@eecs.umich.edu                regNum = MISCREG_TSC;
2175149Sgblack@eecs.umich.edu                break;
2185360Sgblack@eecs.umich.edu              case 0x1B:
2195360Sgblack@eecs.umich.edu                regNum = MISCREG_APIC_BASE;
2205360Sgblack@eecs.umich.edu                break;
2215149Sgblack@eecs.umich.edu              case 0xFE:
2225149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRRCAP;
2235149Sgblack@eecs.umich.edu                break;
2245149Sgblack@eecs.umich.edu              case 0x174:
2255149Sgblack@eecs.umich.edu                regNum = MISCREG_SYSENTER_CS;
2265149Sgblack@eecs.umich.edu                break;
2275149Sgblack@eecs.umich.edu              case 0x175:
2285149Sgblack@eecs.umich.edu                regNum = MISCREG_SYSENTER_ESP;
2295149Sgblack@eecs.umich.edu                break;
2305149Sgblack@eecs.umich.edu              case 0x176:
2315149Sgblack@eecs.umich.edu                regNum = MISCREG_SYSENTER_EIP;
2325149Sgblack@eecs.umich.edu                break;
2335149Sgblack@eecs.umich.edu              case 0x179:
2345149Sgblack@eecs.umich.edu                regNum = MISCREG_MCG_CAP;
2355149Sgblack@eecs.umich.edu                break;
2365149Sgblack@eecs.umich.edu              case 0x17A:
2375149Sgblack@eecs.umich.edu                regNum = MISCREG_MCG_STATUS;
2385149Sgblack@eecs.umich.edu                break;
2395149Sgblack@eecs.umich.edu              case 0x17B:
2405149Sgblack@eecs.umich.edu                regNum = MISCREG_MCG_CTL;
2415149Sgblack@eecs.umich.edu                break;
2425149Sgblack@eecs.umich.edu              case 0x1D9:
2435149Sgblack@eecs.umich.edu                regNum = MISCREG_DEBUG_CTL_MSR;
2445149Sgblack@eecs.umich.edu                break;
2455149Sgblack@eecs.umich.edu              case 0x1DB:
2465149Sgblack@eecs.umich.edu                regNum = MISCREG_LAST_BRANCH_FROM_IP;
2475149Sgblack@eecs.umich.edu                break;
2485149Sgblack@eecs.umich.edu              case 0x1DC:
2495149Sgblack@eecs.umich.edu                regNum = MISCREG_LAST_BRANCH_TO_IP;
2505149Sgblack@eecs.umich.edu                break;
2515149Sgblack@eecs.umich.edu              case 0x1DD:
2525149Sgblack@eecs.umich.edu                regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
2535149Sgblack@eecs.umich.edu                break;
2545149Sgblack@eecs.umich.edu              case 0x1DE:
2555149Sgblack@eecs.umich.edu                regNum = MISCREG_LAST_EXCEPTION_TO_IP;
2565149Sgblack@eecs.umich.edu                break;
2575149Sgblack@eecs.umich.edu              case 0x200:
2585149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_BASE_0;
2595149Sgblack@eecs.umich.edu                break;
2605149Sgblack@eecs.umich.edu              case 0x201:
2615149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_MASK_0;
2625149Sgblack@eecs.umich.edu                break;
2635149Sgblack@eecs.umich.edu              case 0x202:
2645149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_BASE_1;
2655149Sgblack@eecs.umich.edu                break;
2665149Sgblack@eecs.umich.edu              case 0x203:
2675149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_MASK_1;
2685149Sgblack@eecs.umich.edu                break;
2695149Sgblack@eecs.umich.edu              case 0x204:
2705149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_BASE_2;
2715149Sgblack@eecs.umich.edu                break;
2725149Sgblack@eecs.umich.edu              case 0x205:
2735149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_MASK_2;
2745149Sgblack@eecs.umich.edu                break;
2755149Sgblack@eecs.umich.edu              case 0x206:
2765149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_BASE_3;
2775149Sgblack@eecs.umich.edu                break;
2785149Sgblack@eecs.umich.edu              case 0x207:
2795149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_MASK_3;
2805149Sgblack@eecs.umich.edu                break;
2815149Sgblack@eecs.umich.edu              case 0x208:
2825149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_BASE_4;
2835149Sgblack@eecs.umich.edu                break;
2845149Sgblack@eecs.umich.edu              case 0x209:
2855149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_MASK_4;
2865149Sgblack@eecs.umich.edu                break;
2875149Sgblack@eecs.umich.edu              case 0x20A:
2885149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_BASE_5;
2895149Sgblack@eecs.umich.edu                break;
2905149Sgblack@eecs.umich.edu              case 0x20B:
2915149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_MASK_5;
2925149Sgblack@eecs.umich.edu                break;
2935149Sgblack@eecs.umich.edu              case 0x20C:
2945149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_BASE_6;
2955149Sgblack@eecs.umich.edu                break;
2965149Sgblack@eecs.umich.edu              case 0x20D:
2975149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_MASK_6;
2985149Sgblack@eecs.umich.edu                break;
2995149Sgblack@eecs.umich.edu              case 0x20E:
3005149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_BASE_7;
3015149Sgblack@eecs.umich.edu                break;
3025149Sgblack@eecs.umich.edu              case 0x20F:
3035149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_PHYS_MASK_7;
3045149Sgblack@eecs.umich.edu                break;
3055149Sgblack@eecs.umich.edu              case 0x250:
3065149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_FIX_64K_00000;
3075149Sgblack@eecs.umich.edu                break;
3085149Sgblack@eecs.umich.edu              case 0x258:
3095149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_FIX_16K_80000;
3105149Sgblack@eecs.umich.edu                break;
3115149Sgblack@eecs.umich.edu              case 0x259:
3125149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_FIX_16K_A0000;
3135149Sgblack@eecs.umich.edu                break;
3145149Sgblack@eecs.umich.edu              case 0x268:
3155149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_FIX_4K_C0000;
3165149Sgblack@eecs.umich.edu                break;
3175149Sgblack@eecs.umich.edu              case 0x269:
3185149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_FIX_4K_C8000;
3195149Sgblack@eecs.umich.edu                break;
3205149Sgblack@eecs.umich.edu              case 0x26A:
3215149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_FIX_4K_D0000;
3225149Sgblack@eecs.umich.edu                break;
3235149Sgblack@eecs.umich.edu              case 0x26B:
3245149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_FIX_4K_D8000;
3255149Sgblack@eecs.umich.edu                break;
3265149Sgblack@eecs.umich.edu              case 0x26C:
3275149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_FIX_4K_E0000;
3285149Sgblack@eecs.umich.edu                break;
3295149Sgblack@eecs.umich.edu              case 0x26D:
3305149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_FIX_4K_E8000;
3315149Sgblack@eecs.umich.edu                break;
3325149Sgblack@eecs.umich.edu              case 0x26E:
3335149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_FIX_4K_F0000;
3345149Sgblack@eecs.umich.edu                break;
3355149Sgblack@eecs.umich.edu              case 0x26F:
3365149Sgblack@eecs.umich.edu                regNum = MISCREG_MTRR_FIX_4K_F8000;
3375149Sgblack@eecs.umich.edu                break;
3385149Sgblack@eecs.umich.edu              case 0x277:
3395149Sgblack@eecs.umich.edu                regNum = MISCREG_PAT;
3405149Sgblack@eecs.umich.edu                break;
3415149Sgblack@eecs.umich.edu              case 0x2FF:
3425149Sgblack@eecs.umich.edu                regNum = MISCREG_DEF_TYPE;
3435149Sgblack@eecs.umich.edu                break;
3445149Sgblack@eecs.umich.edu              case 0x400:
3455149Sgblack@eecs.umich.edu                regNum = MISCREG_MC0_CTL;
3465149Sgblack@eecs.umich.edu                break;
3475149Sgblack@eecs.umich.edu              case 0x404:
3485149Sgblack@eecs.umich.edu                regNum = MISCREG_MC1_CTL;
3495149Sgblack@eecs.umich.edu                break;
3505149Sgblack@eecs.umich.edu              case 0x408:
3515149Sgblack@eecs.umich.edu                regNum = MISCREG_MC2_CTL;
3525149Sgblack@eecs.umich.edu                break;
3535149Sgblack@eecs.umich.edu              case 0x40C:
3545149Sgblack@eecs.umich.edu                regNum = MISCREG_MC3_CTL;
3555149Sgblack@eecs.umich.edu                break;
3565149Sgblack@eecs.umich.edu              case 0x410:
3575149Sgblack@eecs.umich.edu                regNum = MISCREG_MC4_CTL;
3585149Sgblack@eecs.umich.edu                break;
3595419Sgblack@eecs.umich.edu              case 0x414:
3605419Sgblack@eecs.umich.edu                regNum = MISCREG_MC5_CTL;
3615419Sgblack@eecs.umich.edu                break;
3625419Sgblack@eecs.umich.edu              case 0x418:
3635419Sgblack@eecs.umich.edu                regNum = MISCREG_MC6_CTL;
3645419Sgblack@eecs.umich.edu                break;
3655419Sgblack@eecs.umich.edu              case 0x41C:
3665419Sgblack@eecs.umich.edu                regNum = MISCREG_MC7_CTL;
3675419Sgblack@eecs.umich.edu                break;
3685149Sgblack@eecs.umich.edu              case 0x401:
3695149Sgblack@eecs.umich.edu                regNum = MISCREG_MC0_STATUS;
3705149Sgblack@eecs.umich.edu                break;
3715149Sgblack@eecs.umich.edu              case 0x405:
3725149Sgblack@eecs.umich.edu                regNum = MISCREG_MC1_STATUS;
3735149Sgblack@eecs.umich.edu                break;
3745149Sgblack@eecs.umich.edu              case 0x409:
3755149Sgblack@eecs.umich.edu                regNum = MISCREG_MC2_STATUS;
3765149Sgblack@eecs.umich.edu                break;
3775149Sgblack@eecs.umich.edu              case 0x40D:
3785149Sgblack@eecs.umich.edu                regNum = MISCREG_MC3_STATUS;
3795149Sgblack@eecs.umich.edu                break;
3805149Sgblack@eecs.umich.edu              case 0x411:
3815149Sgblack@eecs.umich.edu                regNum = MISCREG_MC4_STATUS;
3825149Sgblack@eecs.umich.edu                break;
3835419Sgblack@eecs.umich.edu              case 0x415:
3845419Sgblack@eecs.umich.edu                regNum = MISCREG_MC5_STATUS;
3855419Sgblack@eecs.umich.edu                break;
3865419Sgblack@eecs.umich.edu              case 0x419:
3875419Sgblack@eecs.umich.edu                regNum = MISCREG_MC6_STATUS;
3885419Sgblack@eecs.umich.edu                break;
3895419Sgblack@eecs.umich.edu              case 0x41D:
3905419Sgblack@eecs.umich.edu                regNum = MISCREG_MC7_STATUS;
3915419Sgblack@eecs.umich.edu                break;
3925149Sgblack@eecs.umich.edu              case 0x402:
3935149Sgblack@eecs.umich.edu                regNum = MISCREG_MC0_ADDR;
3945149Sgblack@eecs.umich.edu                break;
3955149Sgblack@eecs.umich.edu              case 0x406:
3965149Sgblack@eecs.umich.edu                regNum = MISCREG_MC1_ADDR;
3975149Sgblack@eecs.umich.edu                break;
3985149Sgblack@eecs.umich.edu              case 0x40A:
3995149Sgblack@eecs.umich.edu                regNum = MISCREG_MC2_ADDR;
4005149Sgblack@eecs.umich.edu                break;
4015149Sgblack@eecs.umich.edu              case 0x40E:
4025149Sgblack@eecs.umich.edu                regNum = MISCREG_MC3_ADDR;
4035149Sgblack@eecs.umich.edu                break;
4045149Sgblack@eecs.umich.edu              case 0x412:
4055149Sgblack@eecs.umich.edu                regNum = MISCREG_MC4_ADDR;
4065149Sgblack@eecs.umich.edu                break;
4075419Sgblack@eecs.umich.edu              case 0x416:
4085419Sgblack@eecs.umich.edu                regNum = MISCREG_MC5_ADDR;
4095419Sgblack@eecs.umich.edu                break;
4105419Sgblack@eecs.umich.edu              case 0x41A:
4115419Sgblack@eecs.umich.edu                regNum = MISCREG_MC6_ADDR;
4125419Sgblack@eecs.umich.edu                break;
4135419Sgblack@eecs.umich.edu              case 0x41E:
4145419Sgblack@eecs.umich.edu                regNum = MISCREG_MC7_ADDR;
4155419Sgblack@eecs.umich.edu                break;
4165149Sgblack@eecs.umich.edu              case 0x403:
4175149Sgblack@eecs.umich.edu                regNum = MISCREG_MC0_MISC;
4185149Sgblack@eecs.umich.edu                break;
4195149Sgblack@eecs.umich.edu              case 0x407:
4205149Sgblack@eecs.umich.edu                regNum = MISCREG_MC1_MISC;
4215149Sgblack@eecs.umich.edu                break;
4225149Sgblack@eecs.umich.edu              case 0x40B:
4235149Sgblack@eecs.umich.edu                regNum = MISCREG_MC2_MISC;
4245149Sgblack@eecs.umich.edu                break;
4255149Sgblack@eecs.umich.edu              case 0x40F:
4265149Sgblack@eecs.umich.edu                regNum = MISCREG_MC3_MISC;
4275149Sgblack@eecs.umich.edu                break;
4285149Sgblack@eecs.umich.edu              case 0x413:
4295149Sgblack@eecs.umich.edu                regNum = MISCREG_MC4_MISC;
4305149Sgblack@eecs.umich.edu                break;
4315419Sgblack@eecs.umich.edu              case 0x417:
4325419Sgblack@eecs.umich.edu                regNum = MISCREG_MC5_MISC;
4335419Sgblack@eecs.umich.edu                break;
4345419Sgblack@eecs.umich.edu              case 0x41B:
4355419Sgblack@eecs.umich.edu                regNum = MISCREG_MC6_MISC;
4365419Sgblack@eecs.umich.edu                break;
4375419Sgblack@eecs.umich.edu              case 0x41F:
4385419Sgblack@eecs.umich.edu                regNum = MISCREG_MC7_MISC;
4395419Sgblack@eecs.umich.edu                break;
4405149Sgblack@eecs.umich.edu              case 0xC0000080:
4415149Sgblack@eecs.umich.edu                regNum = MISCREG_EFER;
4425149Sgblack@eecs.umich.edu                break;
4435149Sgblack@eecs.umich.edu              case 0xC0000081:
4445149Sgblack@eecs.umich.edu                regNum = MISCREG_STAR;
4455149Sgblack@eecs.umich.edu                break;
4465149Sgblack@eecs.umich.edu              case 0xC0000082:
4475149Sgblack@eecs.umich.edu                regNum = MISCREG_LSTAR;
4485149Sgblack@eecs.umich.edu                break;
4495149Sgblack@eecs.umich.edu              case 0xC0000083:
4505149Sgblack@eecs.umich.edu                regNum = MISCREG_CSTAR;
4515149Sgblack@eecs.umich.edu                break;
4525149Sgblack@eecs.umich.edu              case 0xC0000084:
4535149Sgblack@eecs.umich.edu                regNum = MISCREG_SF_MASK;
4545149Sgblack@eecs.umich.edu                break;
4555149Sgblack@eecs.umich.edu              case 0xC0000100:
4565149Sgblack@eecs.umich.edu                regNum = MISCREG_FS_BASE;
4575149Sgblack@eecs.umich.edu                break;
4585149Sgblack@eecs.umich.edu              case 0xC0000101:
4595149Sgblack@eecs.umich.edu                regNum = MISCREG_GS_BASE;
4605149Sgblack@eecs.umich.edu                break;
4615149Sgblack@eecs.umich.edu              case 0xC0000102:
4625149Sgblack@eecs.umich.edu                regNum = MISCREG_KERNEL_GS_BASE;
4635149Sgblack@eecs.umich.edu                break;
4645149Sgblack@eecs.umich.edu              case 0xC0000103:
4655149Sgblack@eecs.umich.edu                regNum = MISCREG_TSC_AUX;
4665149Sgblack@eecs.umich.edu                break;
4675149Sgblack@eecs.umich.edu              case 0xC0010000:
4685149Sgblack@eecs.umich.edu                regNum = MISCREG_PERF_EVT_SEL0;
4695149Sgblack@eecs.umich.edu                break;
4705149Sgblack@eecs.umich.edu              case 0xC0010001:
4715149Sgblack@eecs.umich.edu                regNum = MISCREG_PERF_EVT_SEL1;
4725149Sgblack@eecs.umich.edu                break;
4735149Sgblack@eecs.umich.edu              case 0xC0010002:
4745149Sgblack@eecs.umich.edu                regNum = MISCREG_PERF_EVT_SEL2;
4755149Sgblack@eecs.umich.edu                break;
4765149Sgblack@eecs.umich.edu              case 0xC0010003:
4775149Sgblack@eecs.umich.edu                regNum = MISCREG_PERF_EVT_SEL3;
4785149Sgblack@eecs.umich.edu                break;
4795149Sgblack@eecs.umich.edu              case 0xC0010004:
4805149Sgblack@eecs.umich.edu                regNum = MISCREG_PERF_EVT_CTR0;
4815149Sgblack@eecs.umich.edu                break;
4825149Sgblack@eecs.umich.edu              case 0xC0010005:
4835149Sgblack@eecs.umich.edu                regNum = MISCREG_PERF_EVT_CTR1;
4845149Sgblack@eecs.umich.edu                break;
4855149Sgblack@eecs.umich.edu              case 0xC0010006:
4865149Sgblack@eecs.umich.edu                regNum = MISCREG_PERF_EVT_CTR2;
4875149Sgblack@eecs.umich.edu                break;
4885149Sgblack@eecs.umich.edu              case 0xC0010007:
4895149Sgblack@eecs.umich.edu                regNum = MISCREG_PERF_EVT_CTR3;
4905149Sgblack@eecs.umich.edu                break;
4915149Sgblack@eecs.umich.edu              case 0xC0010010:
4925149Sgblack@eecs.umich.edu                regNum = MISCREG_SYSCFG;
4935149Sgblack@eecs.umich.edu                break;
4945149Sgblack@eecs.umich.edu              case 0xC0010016:
4955149Sgblack@eecs.umich.edu                regNum = MISCREG_IORR_BASE0;
4965149Sgblack@eecs.umich.edu                break;
4975149Sgblack@eecs.umich.edu              case 0xC0010017:
4985149Sgblack@eecs.umich.edu                regNum = MISCREG_IORR_BASE1;
4995149Sgblack@eecs.umich.edu                break;
5005149Sgblack@eecs.umich.edu              case 0xC0010018:
5015149Sgblack@eecs.umich.edu                regNum = MISCREG_IORR_MASK0;
5025149Sgblack@eecs.umich.edu                break;
5035149Sgblack@eecs.umich.edu              case 0xC0010019:
5045149Sgblack@eecs.umich.edu                regNum = MISCREG_IORR_MASK1;
5055149Sgblack@eecs.umich.edu                break;
5065149Sgblack@eecs.umich.edu              case 0xC001001A:
5075149Sgblack@eecs.umich.edu                regNum = MISCREG_TOP_MEM;
5085149Sgblack@eecs.umich.edu                break;
5095149Sgblack@eecs.umich.edu              case 0xC001001D:
5105149Sgblack@eecs.umich.edu                regNum = MISCREG_TOP_MEM2;
5115149Sgblack@eecs.umich.edu                break;
5125149Sgblack@eecs.umich.edu              case 0xC0010114:
5135149Sgblack@eecs.umich.edu                regNum = MISCREG_VM_CR;
5145149Sgblack@eecs.umich.edu                break;
5155149Sgblack@eecs.umich.edu              case 0xC0010115:
5165149Sgblack@eecs.umich.edu                regNum = MISCREG_IGNNE;
5175149Sgblack@eecs.umich.edu                break;
5185149Sgblack@eecs.umich.edu              case 0xC0010116:
5195149Sgblack@eecs.umich.edu                regNum = MISCREG_SMM_CTL;
5205149Sgblack@eecs.umich.edu                break;
5215149Sgblack@eecs.umich.edu              case 0xC0010117:
5225149Sgblack@eecs.umich.edu                regNum = MISCREG_VM_HSAVE_PA;
5235149Sgblack@eecs.umich.edu                break;
5245149Sgblack@eecs.umich.edu              default:
5255149Sgblack@eecs.umich.edu                return new GeneralProtection(0);
5265149Sgblack@eecs.umich.edu            }
5275149Sgblack@eecs.umich.edu            //The index is multiplied by the size of a MiscReg so that
5285149Sgblack@eecs.umich.edu            //any memory dependence calculations will not see these as
5295149Sgblack@eecs.umich.edu            //overlapping.
5305149Sgblack@eecs.umich.edu            req->setPaddr(regNum * sizeof(MiscReg));
5315149Sgblack@eecs.umich.edu            return NoFault;
5325323Sgblack@eecs.umich.edu        } else if (prefix == IntAddrPrefixIO) {
5335323Sgblack@eecs.umich.edu            // TODO If CPL > IOPL or in virtual mode, check the I/O permission
5345323Sgblack@eecs.umich.edu            // bitmap in the TSS.
5355323Sgblack@eecs.umich.edu
5365323Sgblack@eecs.umich.edu            Addr IOPort = vaddr & ~IntAddrPrefixMask;
5375323Sgblack@eecs.umich.edu            // Make sure the address fits in the expected 16 bit IO address
5385323Sgblack@eecs.umich.edu            // space.
5395323Sgblack@eecs.umich.edu            assert(!(IOPort & ~0xFFFF));
5405357Sgblack@eecs.umich.edu            if (IOPort == 0xCF8 && req->getSize() == 4) {
5415357Sgblack@eecs.umich.edu                req->setMmapedIpr(true);
5425357Sgblack@eecs.umich.edu                req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
5435357Sgblack@eecs.umich.edu            } else if ((IOPort & ~mask(2)) == 0xCFC) {
5445357Sgblack@eecs.umich.edu                Addr configAddress =
5455357Sgblack@eecs.umich.edu                    tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
5465357Sgblack@eecs.umich.edu                if (bits(configAddress, 31, 31)) {
5475357Sgblack@eecs.umich.edu                    req->setPaddr(PhysAddrPrefixPciConfig |
5485837Sgblack@eecs.umich.edu                            mbits(configAddress, 30, 2) |
5495837Sgblack@eecs.umich.edu                            (IOPort & mask(2)));
5505357Sgblack@eecs.umich.edu                }
5515357Sgblack@eecs.umich.edu            } else {
5525357Sgblack@eecs.umich.edu                req->setPaddr(PhysAddrPrefixIO | IOPort);
5535357Sgblack@eecs.umich.edu            }
5545323Sgblack@eecs.umich.edu            return NoFault;
5555149Sgblack@eecs.umich.edu        } else {
5565149Sgblack@eecs.umich.edu            panic("Access to unrecognized internal address space %#x.\n",
5575149Sgblack@eecs.umich.edu                    prefix);
5585149Sgblack@eecs.umich.edu        }
5595149Sgblack@eecs.umich.edu    }
5605124Sgblack@eecs.umich.edu
5615140Sgblack@eecs.umich.edu    // Get cr0. This will tell us how to do translation. We'll assume it was
5625140Sgblack@eecs.umich.edu    // verified to be correct and consistent when set.
5635140Sgblack@eecs.umich.edu    CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
5645140Sgblack@eecs.umich.edu
5655140Sgblack@eecs.umich.edu    // If protected mode has been enabled...
5665140Sgblack@eecs.umich.edu    if (cr0.pe) {
5675237Sgblack@eecs.umich.edu        DPRINTF(TLB, "In protected mode.\n");
5685140Sgblack@eecs.umich.edu        Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
5695140Sgblack@eecs.umich.edu        SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
5705140Sgblack@eecs.umich.edu        // If we're not in 64-bit mode, do protection/limit checks
5715140Sgblack@eecs.umich.edu        if (!efer.lma || !csAttr.longMode) {
5725237Sgblack@eecs.umich.edu            DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
5735431Sgblack@eecs.umich.edu            // Check for a NULL segment selector.
5746059Sgblack@eecs.umich.edu            if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
5756059Sgblack@eecs.umich.edu                        seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS ||
5766059Sgblack@eecs.umich.edu                        seg == SEGMENT_REG_MS)
5776059Sgblack@eecs.umich.edu                    && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
5785431Sgblack@eecs.umich.edu                return new GeneralProtection(0);
5795433Sgblack@eecs.umich.edu            bool expandDown = false;
5805965Sgblack@eecs.umich.edu            SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
5815433Sgblack@eecs.umich.edu            if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
5826023Snate@binkert.org                if (!attr.writable && mode == Write)
5835433Sgblack@eecs.umich.edu                    return new GeneralProtection(0);
5846023Snate@binkert.org                if (!attr.readable && mode == Read)
5855433Sgblack@eecs.umich.edu                    return new GeneralProtection(0);
5865433Sgblack@eecs.umich.edu                expandDown = attr.expandDown;
5875965Sgblack@eecs.umich.edu
5885433Sgblack@eecs.umich.edu            }
5895140Sgblack@eecs.umich.edu            Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
5905140Sgblack@eecs.umich.edu            Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
5915965Sgblack@eecs.umich.edu            // This assumes we're not in 64 bit mode. If we were, the default
5925965Sgblack@eecs.umich.edu            // address size is 64 bits, overridable to 32.
5935965Sgblack@eecs.umich.edu            int size = 32;
5945965Sgblack@eecs.umich.edu            bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
5955980Snate@binkert.org            if ((csAttr.defaultSize && sizeOverride) ||
5965980Snate@binkert.org                    (!csAttr.defaultSize && !sizeOverride))
5975965Sgblack@eecs.umich.edu                size = 16;
5985965Sgblack@eecs.umich.edu            Addr offset = bits(vaddr - base, size-1, 0);
5995965Sgblack@eecs.umich.edu            Addr endOffset = offset + req->getSize() - 1;
6005433Sgblack@eecs.umich.edu            if (expandDown) {
6015237Sgblack@eecs.umich.edu                DPRINTF(TLB, "Checking an expand down segment.\n");
6025965Sgblack@eecs.umich.edu                warn_once("Expand down segments are untested.\n");
6035965Sgblack@eecs.umich.edu                if (offset <= limit || endOffset <= limit)
6045965Sgblack@eecs.umich.edu                    return new GeneralProtection(0);
6055140Sgblack@eecs.umich.edu            } else {
6065965Sgblack@eecs.umich.edu                if (offset > limit || endOffset > limit)
6075965Sgblack@eecs.umich.edu                    return new GeneralProtection(0);
6085140Sgblack@eecs.umich.edu            }
6095140Sgblack@eecs.umich.edu        }
6105140Sgblack@eecs.umich.edu        // If paging is enabled, do the translation.
6115140Sgblack@eecs.umich.edu        if (cr0.pg) {
6125237Sgblack@eecs.umich.edu            DPRINTF(TLB, "Paging enabled.\n");
6135140Sgblack@eecs.umich.edu            // The vaddr already has the segment base applied.
6145140Sgblack@eecs.umich.edu            TlbEntry *entry = lookup(vaddr);
6155140Sgblack@eecs.umich.edu            if (!entry) {
6165895Sgblack@eecs.umich.edu#if FULL_SYSTEM
6176023Snate@binkert.org                Fault fault = walker->start(tc, translation, req, mode);
6185895Sgblack@eecs.umich.edu                if (timing || fault != NoFault) {
6195895Sgblack@eecs.umich.edu                    // This gets ignored in atomic mode.
6205895Sgblack@eecs.umich.edu                    delayedResponse = true;
6215895Sgblack@eecs.umich.edu                    return fault;
6225895Sgblack@eecs.umich.edu                }
6235895Sgblack@eecs.umich.edu                entry = lookup(vaddr);
6245895Sgblack@eecs.umich.edu                assert(entry);
6255895Sgblack@eecs.umich.edu#else
6265895Sgblack@eecs.umich.edu                DPRINTF(TLB, "Handling a TLB miss for "
6275895Sgblack@eecs.umich.edu                        "address %#x at pc %#x.\n",
6285895Sgblack@eecs.umich.edu                        vaddr, tc->readPC());
6295895Sgblack@eecs.umich.edu
6305895Sgblack@eecs.umich.edu                Process *p = tc->getProcessPtr();
6315895Sgblack@eecs.umich.edu                TlbEntry newEntry;
6325895Sgblack@eecs.umich.edu                bool success = p->pTable->lookup(vaddr, newEntry);
6336023Snate@binkert.org                if(!success && mode != Execute) {
6345895Sgblack@eecs.umich.edu                    p->checkAndAllocNextPage(vaddr);
6355895Sgblack@eecs.umich.edu                    success = p->pTable->lookup(vaddr, newEntry);
6365895Sgblack@eecs.umich.edu                }
6375895Sgblack@eecs.umich.edu                if(!success) {
6385895Sgblack@eecs.umich.edu                    panic("Tried to execute unmapped address %#x.\n", vaddr);
6395895Sgblack@eecs.umich.edu                } else {
6405895Sgblack@eecs.umich.edu                    Addr alignedVaddr = p->pTable->pageAlign(vaddr);
6415895Sgblack@eecs.umich.edu                    DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
6425895Sgblack@eecs.umich.edu                            newEntry.pageStart());
6435895Sgblack@eecs.umich.edu                    entry = insert(alignedVaddr, newEntry);
6445895Sgblack@eecs.umich.edu                }
6455895Sgblack@eecs.umich.edu                DPRINTF(TLB, "Miss was serviced.\n");
6465895Sgblack@eecs.umich.edu#endif
6475140Sgblack@eecs.umich.edu            }
6485895Sgblack@eecs.umich.edu            // Do paging protection checks.
6495917Sgblack@eecs.umich.edu            bool inUser = (csAttr.dpl == 3 &&
6505917Sgblack@eecs.umich.edu                    !(flags & (CPL0FlagBit << FlagShift)));
6515980Snate@binkert.org            if ((inUser && !entry->user) ||
6526023Snate@binkert.org                (mode == Write && !entry->writable)) {
6535917Sgblack@eecs.umich.edu                // The page must have been present to get into the TLB in
6545917Sgblack@eecs.umich.edu                // the first place. We'll assume the reserved bits are
6555917Sgblack@eecs.umich.edu                // fine even though we're not checking them.
6566023Snate@binkert.org                return new PageFault(vaddr, true, mode, inUser, false);
6575917Sgblack@eecs.umich.edu            }
6585917Sgblack@eecs.umich.edu
6595917Sgblack@eecs.umich.edu
6605895Sgblack@eecs.umich.edu            DPRINTF(TLB, "Entry found with paddr %#x, "
6615895Sgblack@eecs.umich.edu                    "doing protection checks.\n", entry->paddr);
6625895Sgblack@eecs.umich.edu            Addr paddr = entry->paddr | (vaddr & (entry->size-1));
6635895Sgblack@eecs.umich.edu            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
6645895Sgblack@eecs.umich.edu            req->setPaddr(paddr);
6655140Sgblack@eecs.umich.edu        } else {
6665140Sgblack@eecs.umich.edu            //Use the address which already has segmentation applied.
6675237Sgblack@eecs.umich.edu            DPRINTF(TLB, "Paging disabled.\n");
6685237Sgblack@eecs.umich.edu            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
6695140Sgblack@eecs.umich.edu            req->setPaddr(vaddr);
6705140Sgblack@eecs.umich.edu        }
6715124Sgblack@eecs.umich.edu    } else {
6725140Sgblack@eecs.umich.edu        // Real mode
6735237Sgblack@eecs.umich.edu        DPRINTF(TLB, "In real mode.\n");
6745237Sgblack@eecs.umich.edu        DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
6755140Sgblack@eecs.umich.edu        req->setPaddr(vaddr);
6765124Sgblack@eecs.umich.edu    }
6775360Sgblack@eecs.umich.edu    // Check for an access to the local APIC
6785374Sgblack@eecs.umich.edu#if FULL_SYSTEM
6795360Sgblack@eecs.umich.edu    LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
6805648Sgblack@eecs.umich.edu    Addr baseAddr = localApicBase.base * PageBytes;
6815360Sgblack@eecs.umich.edu    Addr paddr = req->getPaddr();
6825648Sgblack@eecs.umich.edu    if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
6835417Sgblack@eecs.umich.edu        // The Intel developer's manuals say the below restrictions apply,
6845417Sgblack@eecs.umich.edu        // but the linux kernel, because of a compiler optimization, breaks
6855417Sgblack@eecs.umich.edu        // them.
6865417Sgblack@eecs.umich.edu        /*
6875360Sgblack@eecs.umich.edu        // Check alignment
6885360Sgblack@eecs.umich.edu        if (paddr & ((32/8) - 1))
6895360Sgblack@eecs.umich.edu            return new GeneralProtection(0);
6905360Sgblack@eecs.umich.edu        // Check access size
6915360Sgblack@eecs.umich.edu        if (req->getSize() != (32/8))
6925360Sgblack@eecs.umich.edu            return new GeneralProtection(0);
6935417Sgblack@eecs.umich.edu        */
6945648Sgblack@eecs.umich.edu        // Force the access to be uncacheable.
6955736Snate@binkert.org        req->setFlags(Request::UNCACHEABLE);
6965714Shsul@eecs.umich.edu        req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
6975360Sgblack@eecs.umich.edu    }
6985374Sgblack@eecs.umich.edu#endif
6995086Sgblack@eecs.umich.edu    return NoFault;
7005086Sgblack@eecs.umich.edu};
7015086Sgblack@eecs.umich.edu
7025140Sgblack@eecs.umich.eduFault
7036023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
7045140Sgblack@eecs.umich.edu{
7055895Sgblack@eecs.umich.edu    bool delayedResponse;
7066023Snate@binkert.org    return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
7075140Sgblack@eecs.umich.edu}
7085140Sgblack@eecs.umich.edu
7095894Sgblack@eecs.umich.eduvoid
7106022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc,
7116023Snate@binkert.org        Translation *translation, Mode mode)
7125894Sgblack@eecs.umich.edu{
7135895Sgblack@eecs.umich.edu    bool delayedResponse;
7145894Sgblack@eecs.umich.edu    assert(translation);
7156023Snate@binkert.org    Fault fault =
7166023Snate@binkert.org        TLB::translate(req, tc, translation, mode, delayedResponse, true);
7175895Sgblack@eecs.umich.edu    if (!delayedResponse)
7186023Snate@binkert.org        translation->finish(fault, req, tc, mode);
7195894Sgblack@eecs.umich.edu}
7205894Sgblack@eecs.umich.edu
7215086Sgblack@eecs.umich.edu#if FULL_SYSTEM
7225086Sgblack@eecs.umich.edu
7235086Sgblack@eecs.umich.eduTick
7246022Sgblack@eecs.umich.eduTLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
7255086Sgblack@eecs.umich.edu{
7265100Ssaidi@eecs.umich.edu    return tc->getCpuPtr()->ticks(1);
7275086Sgblack@eecs.umich.edu}
7285086Sgblack@eecs.umich.edu
7295086Sgblack@eecs.umich.eduTick
7306022Sgblack@eecs.umich.eduTLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
7315086Sgblack@eecs.umich.edu{
7325100Ssaidi@eecs.umich.edu    return tc->getCpuPtr()->ticks(1);
7335086Sgblack@eecs.umich.edu}
7345086Sgblack@eecs.umich.edu
7355086Sgblack@eecs.umich.edu#endif
7365086Sgblack@eecs.umich.edu
7375086Sgblack@eecs.umich.eduvoid
7385086Sgblack@eecs.umich.eduTLB::serialize(std::ostream &os)
7395086Sgblack@eecs.umich.edu{
7405086Sgblack@eecs.umich.edu}
7415086Sgblack@eecs.umich.edu
7425086Sgblack@eecs.umich.eduvoid
7435086Sgblack@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string &section)
7445086Sgblack@eecs.umich.edu{
7455086Sgblack@eecs.umich.edu}
7465086Sgblack@eecs.umich.edu
7475086Sgblack@eecs.umich.edu/* end namespace X86ISA */ }
7485086Sgblack@eecs.umich.edu
7496022Sgblack@eecs.umich.eduX86ISA::TLB *
7506022Sgblack@eecs.umich.eduX86TLBParams::create()
7514997Sgblack@eecs.umich.edu{
7526022Sgblack@eecs.umich.edu    return new X86ISA::TLB(this);
7534997Sgblack@eecs.umich.edu}
754