tlb.cc revision 5895
14997Sgblack@eecs.umich.edu/* 25417Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 34997Sgblack@eecs.umich.edu * All rights reserved. 44997Sgblack@eecs.umich.edu * 54997Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 64997Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 74997Sgblack@eecs.umich.edu * following conditions are met: 84997Sgblack@eecs.umich.edu * 94997Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 104997Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 114997Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. Illustrative 124997Sgblack@eecs.umich.edu * examples of non-commercial use are academic research, personal study, 134997Sgblack@eecs.umich.edu * teaching, education and corporate research & development. 144997Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for 154997Sgblack@eecs.umich.edu * commercial advantage and providing services using the software for 164997Sgblack@eecs.umich.edu * commercial advantage. 174997Sgblack@eecs.umich.edu * 184997Sgblack@eecs.umich.edu * If you wish to use this software or functionality therein that may be 194997Sgblack@eecs.umich.edu * covered by patents for commercial use, please contact: 204997Sgblack@eecs.umich.edu * Director of Intellectual Property Licensing 214997Sgblack@eecs.umich.edu * Office of Strategy and Technology 224997Sgblack@eecs.umich.edu * Hewlett-Packard Company 234997Sgblack@eecs.umich.edu * 1501 Page Mill Road 244997Sgblack@eecs.umich.edu * Palo Alto, California 94304 254997Sgblack@eecs.umich.edu * 264997Sgblack@eecs.umich.edu * Redistributions of source code must retain the above copyright notice, 274997Sgblack@eecs.umich.edu * this list of conditions and the following disclaimer. Redistributions 284997Sgblack@eecs.umich.edu * in binary form must reproduce the above copyright notice, this list of 294997Sgblack@eecs.umich.edu * conditions and the following disclaimer in the documentation and/or 304997Sgblack@eecs.umich.edu * other materials provided with the distribution. Neither the name of 314997Sgblack@eecs.umich.edu * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 324997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 334997Sgblack@eecs.umich.edu * this software without specific prior written permission. No right of 344997Sgblack@eecs.umich.edu * sublicense is granted herewith. Derivatives of the software and 354997Sgblack@eecs.umich.edu * output created using the software may be prepared, but only for 364997Sgblack@eecs.umich.edu * Non-Commercial Uses. Derivatives of the software may be shared with 374997Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 384997Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 394997Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 404997Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where 414997Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 424997Sgblack@eecs.umich.edu * 434997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 444997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 454997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 464997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 474997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 484997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 494997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 504997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 514997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 524997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 534997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 544997Sgblack@eecs.umich.edu * 554997Sgblack@eecs.umich.edu * Authors: Gabe Black 564997Sgblack@eecs.umich.edu */ 574997Sgblack@eecs.umich.edu 584997Sgblack@eecs.umich.edu#include <cstring> 594997Sgblack@eecs.umich.edu 605086Sgblack@eecs.umich.edu#include "config/full_system.hh" 615086Sgblack@eecs.umich.edu 625124Sgblack@eecs.umich.edu#include "arch/x86/pagetable.hh" 635086Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh" 645149Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 655086Sgblack@eecs.umich.edu#include "base/bitfield.hh" 665086Sgblack@eecs.umich.edu#include "base/trace.hh" 675237Sgblack@eecs.umich.edu#include "config/full_system.hh" 685086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 695086Sgblack@eecs.umich.edu#include "cpu/base.hh" 705086Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 715086Sgblack@eecs.umich.edu#include "mem/request.hh" 725245Sgblack@eecs.umich.edu 735245Sgblack@eecs.umich.edu#if FULL_SYSTEM 745245Sgblack@eecs.umich.edu#include "arch/x86/pagetable_walker.hh" 755895Sgblack@eecs.umich.edu#else 765895Sgblack@eecs.umich.edu#include "mem/page_table.hh" 775895Sgblack@eecs.umich.edu#include "sim/process.hh" 785245Sgblack@eecs.umich.edu#endif 795086Sgblack@eecs.umich.edu 805086Sgblack@eecs.umich.edunamespace X86ISA { 815086Sgblack@eecs.umich.edu 825358Sgblack@eecs.umich.eduTLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size) 835124Sgblack@eecs.umich.edu{ 845124Sgblack@eecs.umich.edu tlb = new TlbEntry[size]; 855124Sgblack@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 865124Sgblack@eecs.umich.edu 875124Sgblack@eecs.umich.edu for (int x = 0; x < size; x++) 885124Sgblack@eecs.umich.edu freeList.push_back(&tlb[x]); 895124Sgblack@eecs.umich.edu 905237Sgblack@eecs.umich.edu#if FULL_SYSTEM 915245Sgblack@eecs.umich.edu walker = p->walker; 925245Sgblack@eecs.umich.edu walker->setTLB(this); 935245Sgblack@eecs.umich.edu#endif 945236Sgblack@eecs.umich.edu} 955236Sgblack@eecs.umich.edu 965895Sgblack@eecs.umich.eduTlbEntry * 975124Sgblack@eecs.umich.eduTLB::insert(Addr vpn, TlbEntry &entry) 985124Sgblack@eecs.umich.edu{ 995124Sgblack@eecs.umich.edu //TODO Deal with conflicting entries 1005124Sgblack@eecs.umich.edu 1015124Sgblack@eecs.umich.edu TlbEntry *newEntry = NULL; 1025124Sgblack@eecs.umich.edu if (!freeList.empty()) { 1035124Sgblack@eecs.umich.edu newEntry = freeList.front(); 1045124Sgblack@eecs.umich.edu freeList.pop_front(); 1055124Sgblack@eecs.umich.edu } else { 1065124Sgblack@eecs.umich.edu newEntry = entryList.back(); 1075124Sgblack@eecs.umich.edu entryList.pop_back(); 1085124Sgblack@eecs.umich.edu } 1095124Sgblack@eecs.umich.edu *newEntry = entry; 1105124Sgblack@eecs.umich.edu newEntry->vaddr = vpn; 1115124Sgblack@eecs.umich.edu entryList.push_front(newEntry); 1125895Sgblack@eecs.umich.edu return newEntry; 1135124Sgblack@eecs.umich.edu} 1145124Sgblack@eecs.umich.edu 1155360Sgblack@eecs.umich.eduTLB::EntryList::iterator 1165360Sgblack@eecs.umich.eduTLB::lookupIt(Addr va, bool update_lru) 1175124Sgblack@eecs.umich.edu{ 1185124Sgblack@eecs.umich.edu //TODO make this smarter at some point 1195124Sgblack@eecs.umich.edu EntryList::iterator entry; 1205124Sgblack@eecs.umich.edu for (entry = entryList.begin(); entry != entryList.end(); entry++) { 1215124Sgblack@eecs.umich.edu if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) { 1225124Sgblack@eecs.umich.edu DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x " 1235124Sgblack@eecs.umich.edu "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size); 1245124Sgblack@eecs.umich.edu if (update_lru) { 1255360Sgblack@eecs.umich.edu entryList.push_front(*entry); 1265124Sgblack@eecs.umich.edu entryList.erase(entry); 1275360Sgblack@eecs.umich.edu entry = entryList.begin(); 1285124Sgblack@eecs.umich.edu } 1295360Sgblack@eecs.umich.edu break; 1305124Sgblack@eecs.umich.edu } 1315124Sgblack@eecs.umich.edu } 1325360Sgblack@eecs.umich.edu return entry; 1335360Sgblack@eecs.umich.edu} 1345360Sgblack@eecs.umich.edu 1355360Sgblack@eecs.umich.eduTlbEntry * 1365360Sgblack@eecs.umich.eduTLB::lookup(Addr va, bool update_lru) 1375360Sgblack@eecs.umich.edu{ 1385360Sgblack@eecs.umich.edu EntryList::iterator entry = lookupIt(va, update_lru); 1395360Sgblack@eecs.umich.edu if (entry == entryList.end()) 1405360Sgblack@eecs.umich.edu return NULL; 1415360Sgblack@eecs.umich.edu else 1425360Sgblack@eecs.umich.edu return *entry; 1435124Sgblack@eecs.umich.edu} 1445124Sgblack@eecs.umich.edu 1455124Sgblack@eecs.umich.eduvoid 1465124Sgblack@eecs.umich.eduTLB::invalidateAll() 1475124Sgblack@eecs.umich.edu{ 1485242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all entries.\n"); 1495242Sgblack@eecs.umich.edu while (!entryList.empty()) { 1505242Sgblack@eecs.umich.edu TlbEntry *entry = entryList.front(); 1515242Sgblack@eecs.umich.edu entryList.pop_front(); 1525242Sgblack@eecs.umich.edu freeList.push_back(entry); 1535242Sgblack@eecs.umich.edu } 1545124Sgblack@eecs.umich.edu} 1555124Sgblack@eecs.umich.edu 1565124Sgblack@eecs.umich.eduvoid 1575357Sgblack@eecs.umich.eduTLB::setConfigAddress(uint32_t addr) 1585357Sgblack@eecs.umich.edu{ 1595357Sgblack@eecs.umich.edu configAddress = addr; 1605357Sgblack@eecs.umich.edu} 1615357Sgblack@eecs.umich.edu 1625357Sgblack@eecs.umich.eduvoid 1635124Sgblack@eecs.umich.eduTLB::invalidateNonGlobal() 1645124Sgblack@eecs.umich.edu{ 1655242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all non global entries.\n"); 1665242Sgblack@eecs.umich.edu EntryList::iterator entryIt; 1675242Sgblack@eecs.umich.edu for (entryIt = entryList.begin(); entryIt != entryList.end();) { 1685242Sgblack@eecs.umich.edu if (!(*entryIt)->global) { 1695242Sgblack@eecs.umich.edu freeList.push_back(*entryIt); 1705242Sgblack@eecs.umich.edu entryList.erase(entryIt++); 1715242Sgblack@eecs.umich.edu } else { 1725242Sgblack@eecs.umich.edu entryIt++; 1735242Sgblack@eecs.umich.edu } 1745242Sgblack@eecs.umich.edu } 1755124Sgblack@eecs.umich.edu} 1765124Sgblack@eecs.umich.edu 1775124Sgblack@eecs.umich.eduvoid 1785358Sgblack@eecs.umich.eduTLB::demapPage(Addr va, uint64_t asn) 1795086Sgblack@eecs.umich.edu{ 1805359Sgblack@eecs.umich.edu EntryList::iterator entry = lookupIt(va, false); 1815359Sgblack@eecs.umich.edu if (entry != entryList.end()) { 1825359Sgblack@eecs.umich.edu freeList.push_back(*entry); 1835359Sgblack@eecs.umich.edu entryList.erase(entry); 1845359Sgblack@eecs.umich.edu } 1855086Sgblack@eecs.umich.edu} 1865086Sgblack@eecs.umich.edu 1875086Sgblack@eecs.umich.eduFault 1885895Sgblack@eecs.umich.eduTLB::translate(RequestPtr req, ThreadContext *tc, 1895895Sgblack@eecs.umich.edu Translation *translation, bool write, bool execute, 1905895Sgblack@eecs.umich.edu bool &delayedResponse, bool timing) 1915086Sgblack@eecs.umich.edu{ 1925895Sgblack@eecs.umich.edu delayedResponse = false; 1935124Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 1945140Sgblack@eecs.umich.edu DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 1955124Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 1965124Sgblack@eecs.umich.edu bool storeCheck = flags & StoreCheck; 1975140Sgblack@eecs.umich.edu 1985294Sgblack@eecs.umich.edu int seg = flags & mask(4); 1995124Sgblack@eecs.umich.edu 2005124Sgblack@eecs.umich.edu //XXX Junk code to surpress the warning 2015149Sgblack@eecs.umich.edu if (storeCheck); 2025149Sgblack@eecs.umich.edu 2035149Sgblack@eecs.umich.edu // If this is true, we're dealing with a request to read an internal 2045149Sgblack@eecs.umich.edu // value. 2055294Sgblack@eecs.umich.edu if (seg == SEGMENT_REG_MS) { 2065243Sgblack@eecs.umich.edu DPRINTF(TLB, "Addresses references internal memory.\n"); 2075418Sgblack@eecs.umich.edu Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 2085149Sgblack@eecs.umich.edu if (prefix == IntAddrPrefixCPUID) { 2095149Sgblack@eecs.umich.edu panic("CPUID memory space not yet implemented!\n"); 2105149Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixMSR) { 2115418Sgblack@eecs.umich.edu vaddr = vaddr >> 3; 2125149Sgblack@eecs.umich.edu req->setMmapedIpr(true); 2135149Sgblack@eecs.umich.edu Addr regNum = 0; 2145149Sgblack@eecs.umich.edu switch (vaddr & ~IntAddrPrefixMask) { 2155149Sgblack@eecs.umich.edu case 0x10: 2165149Sgblack@eecs.umich.edu regNum = MISCREG_TSC; 2175149Sgblack@eecs.umich.edu break; 2185360Sgblack@eecs.umich.edu case 0x1B: 2195360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_BASE; 2205360Sgblack@eecs.umich.edu break; 2215149Sgblack@eecs.umich.edu case 0xFE: 2225149Sgblack@eecs.umich.edu regNum = MISCREG_MTRRCAP; 2235149Sgblack@eecs.umich.edu break; 2245149Sgblack@eecs.umich.edu case 0x174: 2255149Sgblack@eecs.umich.edu regNum = MISCREG_SYSENTER_CS; 2265149Sgblack@eecs.umich.edu break; 2275149Sgblack@eecs.umich.edu case 0x175: 2285149Sgblack@eecs.umich.edu regNum = MISCREG_SYSENTER_ESP; 2295149Sgblack@eecs.umich.edu break; 2305149Sgblack@eecs.umich.edu case 0x176: 2315149Sgblack@eecs.umich.edu regNum = MISCREG_SYSENTER_EIP; 2325149Sgblack@eecs.umich.edu break; 2335149Sgblack@eecs.umich.edu case 0x179: 2345149Sgblack@eecs.umich.edu regNum = MISCREG_MCG_CAP; 2355149Sgblack@eecs.umich.edu break; 2365149Sgblack@eecs.umich.edu case 0x17A: 2375149Sgblack@eecs.umich.edu regNum = MISCREG_MCG_STATUS; 2385149Sgblack@eecs.umich.edu break; 2395149Sgblack@eecs.umich.edu case 0x17B: 2405149Sgblack@eecs.umich.edu regNum = MISCREG_MCG_CTL; 2415149Sgblack@eecs.umich.edu break; 2425149Sgblack@eecs.umich.edu case 0x1D9: 2435149Sgblack@eecs.umich.edu regNum = MISCREG_DEBUG_CTL_MSR; 2445149Sgblack@eecs.umich.edu break; 2455149Sgblack@eecs.umich.edu case 0x1DB: 2465149Sgblack@eecs.umich.edu regNum = MISCREG_LAST_BRANCH_FROM_IP; 2475149Sgblack@eecs.umich.edu break; 2485149Sgblack@eecs.umich.edu case 0x1DC: 2495149Sgblack@eecs.umich.edu regNum = MISCREG_LAST_BRANCH_TO_IP; 2505149Sgblack@eecs.umich.edu break; 2515149Sgblack@eecs.umich.edu case 0x1DD: 2525149Sgblack@eecs.umich.edu regNum = MISCREG_LAST_EXCEPTION_FROM_IP; 2535149Sgblack@eecs.umich.edu break; 2545149Sgblack@eecs.umich.edu case 0x1DE: 2555149Sgblack@eecs.umich.edu regNum = MISCREG_LAST_EXCEPTION_TO_IP; 2565149Sgblack@eecs.umich.edu break; 2575149Sgblack@eecs.umich.edu case 0x200: 2585149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_0; 2595149Sgblack@eecs.umich.edu break; 2605149Sgblack@eecs.umich.edu case 0x201: 2615149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_0; 2625149Sgblack@eecs.umich.edu break; 2635149Sgblack@eecs.umich.edu case 0x202: 2645149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_1; 2655149Sgblack@eecs.umich.edu break; 2665149Sgblack@eecs.umich.edu case 0x203: 2675149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_1; 2685149Sgblack@eecs.umich.edu break; 2695149Sgblack@eecs.umich.edu case 0x204: 2705149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_2; 2715149Sgblack@eecs.umich.edu break; 2725149Sgblack@eecs.umich.edu case 0x205: 2735149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_2; 2745149Sgblack@eecs.umich.edu break; 2755149Sgblack@eecs.umich.edu case 0x206: 2765149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_3; 2775149Sgblack@eecs.umich.edu break; 2785149Sgblack@eecs.umich.edu case 0x207: 2795149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_3; 2805149Sgblack@eecs.umich.edu break; 2815149Sgblack@eecs.umich.edu case 0x208: 2825149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_4; 2835149Sgblack@eecs.umich.edu break; 2845149Sgblack@eecs.umich.edu case 0x209: 2855149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_4; 2865149Sgblack@eecs.umich.edu break; 2875149Sgblack@eecs.umich.edu case 0x20A: 2885149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_5; 2895149Sgblack@eecs.umich.edu break; 2905149Sgblack@eecs.umich.edu case 0x20B: 2915149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_5; 2925149Sgblack@eecs.umich.edu break; 2935149Sgblack@eecs.umich.edu case 0x20C: 2945149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_6; 2955149Sgblack@eecs.umich.edu break; 2965149Sgblack@eecs.umich.edu case 0x20D: 2975149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_6; 2985149Sgblack@eecs.umich.edu break; 2995149Sgblack@eecs.umich.edu case 0x20E: 3005149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_7; 3015149Sgblack@eecs.umich.edu break; 3025149Sgblack@eecs.umich.edu case 0x20F: 3035149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_7; 3045149Sgblack@eecs.umich.edu break; 3055149Sgblack@eecs.umich.edu case 0x250: 3065149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_64K_00000; 3075149Sgblack@eecs.umich.edu break; 3085149Sgblack@eecs.umich.edu case 0x258: 3095149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_16K_80000; 3105149Sgblack@eecs.umich.edu break; 3115149Sgblack@eecs.umich.edu case 0x259: 3125149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_16K_A0000; 3135149Sgblack@eecs.umich.edu break; 3145149Sgblack@eecs.umich.edu case 0x268: 3155149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_C0000; 3165149Sgblack@eecs.umich.edu break; 3175149Sgblack@eecs.umich.edu case 0x269: 3185149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_C8000; 3195149Sgblack@eecs.umich.edu break; 3205149Sgblack@eecs.umich.edu case 0x26A: 3215149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_D0000; 3225149Sgblack@eecs.umich.edu break; 3235149Sgblack@eecs.umich.edu case 0x26B: 3245149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_D8000; 3255149Sgblack@eecs.umich.edu break; 3265149Sgblack@eecs.umich.edu case 0x26C: 3275149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_E0000; 3285149Sgblack@eecs.umich.edu break; 3295149Sgblack@eecs.umich.edu case 0x26D: 3305149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_E8000; 3315149Sgblack@eecs.umich.edu break; 3325149Sgblack@eecs.umich.edu case 0x26E: 3335149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_F0000; 3345149Sgblack@eecs.umich.edu break; 3355149Sgblack@eecs.umich.edu case 0x26F: 3365149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_F8000; 3375149Sgblack@eecs.umich.edu break; 3385149Sgblack@eecs.umich.edu case 0x277: 3395149Sgblack@eecs.umich.edu regNum = MISCREG_PAT; 3405149Sgblack@eecs.umich.edu break; 3415149Sgblack@eecs.umich.edu case 0x2FF: 3425149Sgblack@eecs.umich.edu regNum = MISCREG_DEF_TYPE; 3435149Sgblack@eecs.umich.edu break; 3445149Sgblack@eecs.umich.edu case 0x400: 3455149Sgblack@eecs.umich.edu regNum = MISCREG_MC0_CTL; 3465149Sgblack@eecs.umich.edu break; 3475149Sgblack@eecs.umich.edu case 0x404: 3485149Sgblack@eecs.umich.edu regNum = MISCREG_MC1_CTL; 3495149Sgblack@eecs.umich.edu break; 3505149Sgblack@eecs.umich.edu case 0x408: 3515149Sgblack@eecs.umich.edu regNum = MISCREG_MC2_CTL; 3525149Sgblack@eecs.umich.edu break; 3535149Sgblack@eecs.umich.edu case 0x40C: 3545149Sgblack@eecs.umich.edu regNum = MISCREG_MC3_CTL; 3555149Sgblack@eecs.umich.edu break; 3565149Sgblack@eecs.umich.edu case 0x410: 3575149Sgblack@eecs.umich.edu regNum = MISCREG_MC4_CTL; 3585149Sgblack@eecs.umich.edu break; 3595419Sgblack@eecs.umich.edu case 0x414: 3605419Sgblack@eecs.umich.edu regNum = MISCREG_MC5_CTL; 3615419Sgblack@eecs.umich.edu break; 3625419Sgblack@eecs.umich.edu case 0x418: 3635419Sgblack@eecs.umich.edu regNum = MISCREG_MC6_CTL; 3645419Sgblack@eecs.umich.edu break; 3655419Sgblack@eecs.umich.edu case 0x41C: 3665419Sgblack@eecs.umich.edu regNum = MISCREG_MC7_CTL; 3675419Sgblack@eecs.umich.edu break; 3685149Sgblack@eecs.umich.edu case 0x401: 3695149Sgblack@eecs.umich.edu regNum = MISCREG_MC0_STATUS; 3705149Sgblack@eecs.umich.edu break; 3715149Sgblack@eecs.umich.edu case 0x405: 3725149Sgblack@eecs.umich.edu regNum = MISCREG_MC1_STATUS; 3735149Sgblack@eecs.umich.edu break; 3745149Sgblack@eecs.umich.edu case 0x409: 3755149Sgblack@eecs.umich.edu regNum = MISCREG_MC2_STATUS; 3765149Sgblack@eecs.umich.edu break; 3775149Sgblack@eecs.umich.edu case 0x40D: 3785149Sgblack@eecs.umich.edu regNum = MISCREG_MC3_STATUS; 3795149Sgblack@eecs.umich.edu break; 3805149Sgblack@eecs.umich.edu case 0x411: 3815149Sgblack@eecs.umich.edu regNum = MISCREG_MC4_STATUS; 3825149Sgblack@eecs.umich.edu break; 3835419Sgblack@eecs.umich.edu case 0x415: 3845419Sgblack@eecs.umich.edu regNum = MISCREG_MC5_STATUS; 3855419Sgblack@eecs.umich.edu break; 3865419Sgblack@eecs.umich.edu case 0x419: 3875419Sgblack@eecs.umich.edu regNum = MISCREG_MC6_STATUS; 3885419Sgblack@eecs.umich.edu break; 3895419Sgblack@eecs.umich.edu case 0x41D: 3905419Sgblack@eecs.umich.edu regNum = MISCREG_MC7_STATUS; 3915419Sgblack@eecs.umich.edu break; 3925149Sgblack@eecs.umich.edu case 0x402: 3935149Sgblack@eecs.umich.edu regNum = MISCREG_MC0_ADDR; 3945149Sgblack@eecs.umich.edu break; 3955149Sgblack@eecs.umich.edu case 0x406: 3965149Sgblack@eecs.umich.edu regNum = MISCREG_MC1_ADDR; 3975149Sgblack@eecs.umich.edu break; 3985149Sgblack@eecs.umich.edu case 0x40A: 3995149Sgblack@eecs.umich.edu regNum = MISCREG_MC2_ADDR; 4005149Sgblack@eecs.umich.edu break; 4015149Sgblack@eecs.umich.edu case 0x40E: 4025149Sgblack@eecs.umich.edu regNum = MISCREG_MC3_ADDR; 4035149Sgblack@eecs.umich.edu break; 4045149Sgblack@eecs.umich.edu case 0x412: 4055149Sgblack@eecs.umich.edu regNum = MISCREG_MC4_ADDR; 4065149Sgblack@eecs.umich.edu break; 4075419Sgblack@eecs.umich.edu case 0x416: 4085419Sgblack@eecs.umich.edu regNum = MISCREG_MC5_ADDR; 4095419Sgblack@eecs.umich.edu break; 4105419Sgblack@eecs.umich.edu case 0x41A: 4115419Sgblack@eecs.umich.edu regNum = MISCREG_MC6_ADDR; 4125419Sgblack@eecs.umich.edu break; 4135419Sgblack@eecs.umich.edu case 0x41E: 4145419Sgblack@eecs.umich.edu regNum = MISCREG_MC7_ADDR; 4155419Sgblack@eecs.umich.edu break; 4165149Sgblack@eecs.umich.edu case 0x403: 4175149Sgblack@eecs.umich.edu regNum = MISCREG_MC0_MISC; 4185149Sgblack@eecs.umich.edu break; 4195149Sgblack@eecs.umich.edu case 0x407: 4205149Sgblack@eecs.umich.edu regNum = MISCREG_MC1_MISC; 4215149Sgblack@eecs.umich.edu break; 4225149Sgblack@eecs.umich.edu case 0x40B: 4235149Sgblack@eecs.umich.edu regNum = MISCREG_MC2_MISC; 4245149Sgblack@eecs.umich.edu break; 4255149Sgblack@eecs.umich.edu case 0x40F: 4265149Sgblack@eecs.umich.edu regNum = MISCREG_MC3_MISC; 4275149Sgblack@eecs.umich.edu break; 4285149Sgblack@eecs.umich.edu case 0x413: 4295149Sgblack@eecs.umich.edu regNum = MISCREG_MC4_MISC; 4305149Sgblack@eecs.umich.edu break; 4315419Sgblack@eecs.umich.edu case 0x417: 4325419Sgblack@eecs.umich.edu regNum = MISCREG_MC5_MISC; 4335419Sgblack@eecs.umich.edu break; 4345419Sgblack@eecs.umich.edu case 0x41B: 4355419Sgblack@eecs.umich.edu regNum = MISCREG_MC6_MISC; 4365419Sgblack@eecs.umich.edu break; 4375419Sgblack@eecs.umich.edu case 0x41F: 4385419Sgblack@eecs.umich.edu regNum = MISCREG_MC7_MISC; 4395419Sgblack@eecs.umich.edu break; 4405149Sgblack@eecs.umich.edu case 0xC0000080: 4415149Sgblack@eecs.umich.edu regNum = MISCREG_EFER; 4425149Sgblack@eecs.umich.edu break; 4435149Sgblack@eecs.umich.edu case 0xC0000081: 4445149Sgblack@eecs.umich.edu regNum = MISCREG_STAR; 4455149Sgblack@eecs.umich.edu break; 4465149Sgblack@eecs.umich.edu case 0xC0000082: 4475149Sgblack@eecs.umich.edu regNum = MISCREG_LSTAR; 4485149Sgblack@eecs.umich.edu break; 4495149Sgblack@eecs.umich.edu case 0xC0000083: 4505149Sgblack@eecs.umich.edu regNum = MISCREG_CSTAR; 4515149Sgblack@eecs.umich.edu break; 4525149Sgblack@eecs.umich.edu case 0xC0000084: 4535149Sgblack@eecs.umich.edu regNum = MISCREG_SF_MASK; 4545149Sgblack@eecs.umich.edu break; 4555149Sgblack@eecs.umich.edu case 0xC0000100: 4565149Sgblack@eecs.umich.edu regNum = MISCREG_FS_BASE; 4575149Sgblack@eecs.umich.edu break; 4585149Sgblack@eecs.umich.edu case 0xC0000101: 4595149Sgblack@eecs.umich.edu regNum = MISCREG_GS_BASE; 4605149Sgblack@eecs.umich.edu break; 4615149Sgblack@eecs.umich.edu case 0xC0000102: 4625149Sgblack@eecs.umich.edu regNum = MISCREG_KERNEL_GS_BASE; 4635149Sgblack@eecs.umich.edu break; 4645149Sgblack@eecs.umich.edu case 0xC0000103: 4655149Sgblack@eecs.umich.edu regNum = MISCREG_TSC_AUX; 4665149Sgblack@eecs.umich.edu break; 4675149Sgblack@eecs.umich.edu case 0xC0010000: 4685149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL0; 4695149Sgblack@eecs.umich.edu break; 4705149Sgblack@eecs.umich.edu case 0xC0010001: 4715149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL1; 4725149Sgblack@eecs.umich.edu break; 4735149Sgblack@eecs.umich.edu case 0xC0010002: 4745149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL2; 4755149Sgblack@eecs.umich.edu break; 4765149Sgblack@eecs.umich.edu case 0xC0010003: 4775149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL3; 4785149Sgblack@eecs.umich.edu break; 4795149Sgblack@eecs.umich.edu case 0xC0010004: 4805149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR0; 4815149Sgblack@eecs.umich.edu break; 4825149Sgblack@eecs.umich.edu case 0xC0010005: 4835149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR1; 4845149Sgblack@eecs.umich.edu break; 4855149Sgblack@eecs.umich.edu case 0xC0010006: 4865149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR2; 4875149Sgblack@eecs.umich.edu break; 4885149Sgblack@eecs.umich.edu case 0xC0010007: 4895149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR3; 4905149Sgblack@eecs.umich.edu break; 4915149Sgblack@eecs.umich.edu case 0xC0010010: 4925149Sgblack@eecs.umich.edu regNum = MISCREG_SYSCFG; 4935149Sgblack@eecs.umich.edu break; 4945149Sgblack@eecs.umich.edu case 0xC0010016: 4955149Sgblack@eecs.umich.edu regNum = MISCREG_IORR_BASE0; 4965149Sgblack@eecs.umich.edu break; 4975149Sgblack@eecs.umich.edu case 0xC0010017: 4985149Sgblack@eecs.umich.edu regNum = MISCREG_IORR_BASE1; 4995149Sgblack@eecs.umich.edu break; 5005149Sgblack@eecs.umich.edu case 0xC0010018: 5015149Sgblack@eecs.umich.edu regNum = MISCREG_IORR_MASK0; 5025149Sgblack@eecs.umich.edu break; 5035149Sgblack@eecs.umich.edu case 0xC0010019: 5045149Sgblack@eecs.umich.edu regNum = MISCREG_IORR_MASK1; 5055149Sgblack@eecs.umich.edu break; 5065149Sgblack@eecs.umich.edu case 0xC001001A: 5075149Sgblack@eecs.umich.edu regNum = MISCREG_TOP_MEM; 5085149Sgblack@eecs.umich.edu break; 5095149Sgblack@eecs.umich.edu case 0xC001001D: 5105149Sgblack@eecs.umich.edu regNum = MISCREG_TOP_MEM2; 5115149Sgblack@eecs.umich.edu break; 5125149Sgblack@eecs.umich.edu case 0xC0010114: 5135149Sgblack@eecs.umich.edu regNum = MISCREG_VM_CR; 5145149Sgblack@eecs.umich.edu break; 5155149Sgblack@eecs.umich.edu case 0xC0010115: 5165149Sgblack@eecs.umich.edu regNum = MISCREG_IGNNE; 5175149Sgblack@eecs.umich.edu break; 5185149Sgblack@eecs.umich.edu case 0xC0010116: 5195149Sgblack@eecs.umich.edu regNum = MISCREG_SMM_CTL; 5205149Sgblack@eecs.umich.edu break; 5215149Sgblack@eecs.umich.edu case 0xC0010117: 5225149Sgblack@eecs.umich.edu regNum = MISCREG_VM_HSAVE_PA; 5235149Sgblack@eecs.umich.edu break; 5245149Sgblack@eecs.umich.edu default: 5255149Sgblack@eecs.umich.edu return new GeneralProtection(0); 5265149Sgblack@eecs.umich.edu } 5275149Sgblack@eecs.umich.edu //The index is multiplied by the size of a MiscReg so that 5285149Sgblack@eecs.umich.edu //any memory dependence calculations will not see these as 5295149Sgblack@eecs.umich.edu //overlapping. 5305149Sgblack@eecs.umich.edu req->setPaddr(regNum * sizeof(MiscReg)); 5315149Sgblack@eecs.umich.edu return NoFault; 5325323Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixIO) { 5335323Sgblack@eecs.umich.edu // TODO If CPL > IOPL or in virtual mode, check the I/O permission 5345323Sgblack@eecs.umich.edu // bitmap in the TSS. 5355323Sgblack@eecs.umich.edu 5365323Sgblack@eecs.umich.edu Addr IOPort = vaddr & ~IntAddrPrefixMask; 5375323Sgblack@eecs.umich.edu // Make sure the address fits in the expected 16 bit IO address 5385323Sgblack@eecs.umich.edu // space. 5395323Sgblack@eecs.umich.edu assert(!(IOPort & ~0xFFFF)); 5405357Sgblack@eecs.umich.edu if (IOPort == 0xCF8 && req->getSize() == 4) { 5415357Sgblack@eecs.umich.edu req->setMmapedIpr(true); 5425357Sgblack@eecs.umich.edu req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 5435357Sgblack@eecs.umich.edu } else if ((IOPort & ~mask(2)) == 0xCFC) { 5445357Sgblack@eecs.umich.edu Addr configAddress = 5455357Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 5465357Sgblack@eecs.umich.edu if (bits(configAddress, 31, 31)) { 5475357Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixPciConfig | 5485837Sgblack@eecs.umich.edu mbits(configAddress, 30, 2) | 5495837Sgblack@eecs.umich.edu (IOPort & mask(2))); 5505357Sgblack@eecs.umich.edu } 5515357Sgblack@eecs.umich.edu } else { 5525357Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 5535357Sgblack@eecs.umich.edu } 5545323Sgblack@eecs.umich.edu return NoFault; 5555149Sgblack@eecs.umich.edu } else { 5565149Sgblack@eecs.umich.edu panic("Access to unrecognized internal address space %#x.\n", 5575149Sgblack@eecs.umich.edu prefix); 5585149Sgblack@eecs.umich.edu } 5595149Sgblack@eecs.umich.edu } 5605124Sgblack@eecs.umich.edu 5615140Sgblack@eecs.umich.edu // Get cr0. This will tell us how to do translation. We'll assume it was 5625140Sgblack@eecs.umich.edu // verified to be correct and consistent when set. 5635140Sgblack@eecs.umich.edu CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 5645140Sgblack@eecs.umich.edu 5655140Sgblack@eecs.umich.edu // If protected mode has been enabled... 5665140Sgblack@eecs.umich.edu if (cr0.pe) { 5675237Sgblack@eecs.umich.edu DPRINTF(TLB, "In protected mode.\n"); 5685140Sgblack@eecs.umich.edu Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 5695140Sgblack@eecs.umich.edu SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR); 5705140Sgblack@eecs.umich.edu // If we're not in 64-bit mode, do protection/limit checks 5715140Sgblack@eecs.umich.edu if (!efer.lma || !csAttr.longMode) { 5725237Sgblack@eecs.umich.edu DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 5735431Sgblack@eecs.umich.edu // Check for a NULL segment selector. 5745431Sgblack@eecs.umich.edu if (!tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 5755431Sgblack@eecs.umich.edu return new GeneralProtection(0); 5765433Sgblack@eecs.umich.edu bool expandDown = false; 5775433Sgblack@eecs.umich.edu if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 5785433Sgblack@eecs.umich.edu SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 5795433Sgblack@eecs.umich.edu if (!attr.writable && write) 5805433Sgblack@eecs.umich.edu return new GeneralProtection(0); 5815433Sgblack@eecs.umich.edu if (!attr.readable && !write && !execute) 5825433Sgblack@eecs.umich.edu return new GeneralProtection(0); 5835433Sgblack@eecs.umich.edu expandDown = attr.expandDown; 5845433Sgblack@eecs.umich.edu } 5855140Sgblack@eecs.umich.edu Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 5865140Sgblack@eecs.umich.edu Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 5875433Sgblack@eecs.umich.edu if (expandDown) { 5885237Sgblack@eecs.umich.edu DPRINTF(TLB, "Checking an expand down segment.\n"); 5895140Sgblack@eecs.umich.edu // We don't have to worry about the access going around the 5905140Sgblack@eecs.umich.edu // end of memory because accesses will be broken up into 5915140Sgblack@eecs.umich.edu // pieces at boundaries aligned on sizes smaller than an 5925140Sgblack@eecs.umich.edu // entire address space. We do have to worry about the limit 5935140Sgblack@eecs.umich.edu // being less than the base. 5945140Sgblack@eecs.umich.edu if (limit < base) { 5955140Sgblack@eecs.umich.edu if (limit < vaddr + req->getSize() && vaddr < base) 5965140Sgblack@eecs.umich.edu return new GeneralProtection(0); 5975140Sgblack@eecs.umich.edu } else { 5985140Sgblack@eecs.umich.edu if (limit < vaddr + req->getSize()) 5995140Sgblack@eecs.umich.edu return new GeneralProtection(0); 6005140Sgblack@eecs.umich.edu } 6015140Sgblack@eecs.umich.edu } else { 6025140Sgblack@eecs.umich.edu if (limit < base) { 6035140Sgblack@eecs.umich.edu if (vaddr <= limit || vaddr + req->getSize() >= base) 6045140Sgblack@eecs.umich.edu return new GeneralProtection(0); 6055140Sgblack@eecs.umich.edu } else { 6065140Sgblack@eecs.umich.edu if (vaddr <= limit && vaddr + req->getSize() >= base) 6075140Sgblack@eecs.umich.edu return new GeneralProtection(0); 6085140Sgblack@eecs.umich.edu } 6095140Sgblack@eecs.umich.edu } 6105140Sgblack@eecs.umich.edu } 6115140Sgblack@eecs.umich.edu // If paging is enabled, do the translation. 6125140Sgblack@eecs.umich.edu if (cr0.pg) { 6135237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging enabled.\n"); 6145140Sgblack@eecs.umich.edu // The vaddr already has the segment base applied. 6155140Sgblack@eecs.umich.edu TlbEntry *entry = lookup(vaddr); 6165140Sgblack@eecs.umich.edu if (!entry) { 6175895Sgblack@eecs.umich.edu#if FULL_SYSTEM 6185895Sgblack@eecs.umich.edu Fault fault = walker->start(tc, translation, req, 6195895Sgblack@eecs.umich.edu write, execute); 6205895Sgblack@eecs.umich.edu if (timing || fault != NoFault) { 6215895Sgblack@eecs.umich.edu // This gets ignored in atomic mode. 6225895Sgblack@eecs.umich.edu delayedResponse = true; 6235895Sgblack@eecs.umich.edu return fault; 6245895Sgblack@eecs.umich.edu } 6255895Sgblack@eecs.umich.edu entry = lookup(vaddr); 6265895Sgblack@eecs.umich.edu assert(entry); 6275895Sgblack@eecs.umich.edu#else 6285895Sgblack@eecs.umich.edu DPRINTF(TLB, "Handling a TLB miss for " 6295895Sgblack@eecs.umich.edu "address %#x at pc %#x.\n", 6305895Sgblack@eecs.umich.edu vaddr, tc->readPC()); 6315895Sgblack@eecs.umich.edu 6325895Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 6335895Sgblack@eecs.umich.edu TlbEntry newEntry; 6345895Sgblack@eecs.umich.edu bool success = p->pTable->lookup(vaddr, newEntry); 6355895Sgblack@eecs.umich.edu if(!success && !execute) { 6365895Sgblack@eecs.umich.edu p->checkAndAllocNextPage(vaddr); 6375895Sgblack@eecs.umich.edu success = p->pTable->lookup(vaddr, newEntry); 6385895Sgblack@eecs.umich.edu } 6395895Sgblack@eecs.umich.edu if(!success) { 6405895Sgblack@eecs.umich.edu panic("Tried to execute unmapped address %#x.\n", vaddr); 6415895Sgblack@eecs.umich.edu } else { 6425895Sgblack@eecs.umich.edu Addr alignedVaddr = p->pTable->pageAlign(vaddr); 6435895Sgblack@eecs.umich.edu DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 6445895Sgblack@eecs.umich.edu newEntry.pageStart()); 6455895Sgblack@eecs.umich.edu entry = insert(alignedVaddr, newEntry); 6465895Sgblack@eecs.umich.edu } 6475895Sgblack@eecs.umich.edu DPRINTF(TLB, "Miss was serviced.\n"); 6485895Sgblack@eecs.umich.edu#endif 6495140Sgblack@eecs.umich.edu } 6505895Sgblack@eecs.umich.edu // Do paging protection checks. 6515895Sgblack@eecs.umich.edu DPRINTF(TLB, "Entry found with paddr %#x, " 6525895Sgblack@eecs.umich.edu "doing protection checks.\n", entry->paddr); 6535895Sgblack@eecs.umich.edu Addr paddr = entry->paddr | (vaddr & (entry->size-1)); 6545895Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 6555895Sgblack@eecs.umich.edu req->setPaddr(paddr); 6565140Sgblack@eecs.umich.edu } else { 6575140Sgblack@eecs.umich.edu //Use the address which already has segmentation applied. 6585237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging disabled.\n"); 6595237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 6605140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 6615140Sgblack@eecs.umich.edu } 6625124Sgblack@eecs.umich.edu } else { 6635140Sgblack@eecs.umich.edu // Real mode 6645237Sgblack@eecs.umich.edu DPRINTF(TLB, "In real mode.\n"); 6655237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 6665140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 6675124Sgblack@eecs.umich.edu } 6685360Sgblack@eecs.umich.edu // Check for an access to the local APIC 6695374Sgblack@eecs.umich.edu#if FULL_SYSTEM 6705360Sgblack@eecs.umich.edu LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 6715648Sgblack@eecs.umich.edu Addr baseAddr = localApicBase.base * PageBytes; 6725360Sgblack@eecs.umich.edu Addr paddr = req->getPaddr(); 6735648Sgblack@eecs.umich.edu if (baseAddr <= paddr && baseAddr + PageBytes > paddr) { 6745417Sgblack@eecs.umich.edu // The Intel developer's manuals say the below restrictions apply, 6755417Sgblack@eecs.umich.edu // but the linux kernel, because of a compiler optimization, breaks 6765417Sgblack@eecs.umich.edu // them. 6775417Sgblack@eecs.umich.edu /* 6785360Sgblack@eecs.umich.edu // Check alignment 6795360Sgblack@eecs.umich.edu if (paddr & ((32/8) - 1)) 6805360Sgblack@eecs.umich.edu return new GeneralProtection(0); 6815360Sgblack@eecs.umich.edu // Check access size 6825360Sgblack@eecs.umich.edu if (req->getSize() != (32/8)) 6835360Sgblack@eecs.umich.edu return new GeneralProtection(0); 6845417Sgblack@eecs.umich.edu */ 6855648Sgblack@eecs.umich.edu // Force the access to be uncacheable. 6865736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 6875714Shsul@eecs.umich.edu req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr)); 6885360Sgblack@eecs.umich.edu } 6895374Sgblack@eecs.umich.edu#endif 6905086Sgblack@eecs.umich.edu return NoFault; 6915086Sgblack@eecs.umich.edu}; 6925086Sgblack@eecs.umich.edu 6935140Sgblack@eecs.umich.eduFault 6945894Sgblack@eecs.umich.eduDTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write) 6955140Sgblack@eecs.umich.edu{ 6965895Sgblack@eecs.umich.edu bool delayedResponse; 6975895Sgblack@eecs.umich.edu return TLB::translate(req, tc, NULL, write, 6985895Sgblack@eecs.umich.edu false, delayedResponse, false); 6995140Sgblack@eecs.umich.edu} 7005140Sgblack@eecs.umich.edu 7015894Sgblack@eecs.umich.eduvoid 7025894Sgblack@eecs.umich.eduDTB::translateTiming(RequestPtr req, ThreadContext *tc, 7035894Sgblack@eecs.umich.edu Translation *translation, bool write) 7045894Sgblack@eecs.umich.edu{ 7055895Sgblack@eecs.umich.edu bool delayedResponse; 7065894Sgblack@eecs.umich.edu assert(translation); 7075895Sgblack@eecs.umich.edu Fault fault = TLB::translate(req, tc, translation, 7085895Sgblack@eecs.umich.edu write, false, delayedResponse, true); 7095895Sgblack@eecs.umich.edu if (!delayedResponse) 7105895Sgblack@eecs.umich.edu translation->finish(fault, req, tc, write); 7115894Sgblack@eecs.umich.edu} 7125894Sgblack@eecs.umich.edu 7135140Sgblack@eecs.umich.eduFault 7145894Sgblack@eecs.umich.eduITB::translateAtomic(RequestPtr req, ThreadContext *tc) 7155140Sgblack@eecs.umich.edu{ 7165895Sgblack@eecs.umich.edu bool delayedResponse; 7175895Sgblack@eecs.umich.edu return TLB::translate(req, tc, NULL, false, 7185895Sgblack@eecs.umich.edu true, delayedResponse, false); 7195140Sgblack@eecs.umich.edu} 7205140Sgblack@eecs.umich.edu 7215894Sgblack@eecs.umich.eduvoid 7225894Sgblack@eecs.umich.eduITB::translateTiming(RequestPtr req, ThreadContext *tc, 7235894Sgblack@eecs.umich.edu Translation *translation) 7245894Sgblack@eecs.umich.edu{ 7255895Sgblack@eecs.umich.edu bool delayedResponse; 7265894Sgblack@eecs.umich.edu assert(translation); 7275895Sgblack@eecs.umich.edu Fault fault = TLB::translate(req, tc, translation, 7285895Sgblack@eecs.umich.edu false, true, delayedResponse, true); 7295895Sgblack@eecs.umich.edu if (!delayedResponse) 7305895Sgblack@eecs.umich.edu translation->finish(fault, req, tc, false); 7315894Sgblack@eecs.umich.edu} 7325894Sgblack@eecs.umich.edu 7335086Sgblack@eecs.umich.edu#if FULL_SYSTEM 7345086Sgblack@eecs.umich.edu 7355086Sgblack@eecs.umich.eduTick 7365086Sgblack@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 7375086Sgblack@eecs.umich.edu{ 7385100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 7395086Sgblack@eecs.umich.edu} 7405086Sgblack@eecs.umich.edu 7415086Sgblack@eecs.umich.eduTick 7425086Sgblack@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 7435086Sgblack@eecs.umich.edu{ 7445100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 7455086Sgblack@eecs.umich.edu} 7465086Sgblack@eecs.umich.edu 7475086Sgblack@eecs.umich.edu#endif 7485086Sgblack@eecs.umich.edu 7495086Sgblack@eecs.umich.eduvoid 7505086Sgblack@eecs.umich.eduTLB::serialize(std::ostream &os) 7515086Sgblack@eecs.umich.edu{ 7525086Sgblack@eecs.umich.edu} 7535086Sgblack@eecs.umich.edu 7545086Sgblack@eecs.umich.eduvoid 7555086Sgblack@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 7565086Sgblack@eecs.umich.edu{ 7575086Sgblack@eecs.umich.edu} 7585086Sgblack@eecs.umich.edu 7595086Sgblack@eecs.umich.eduvoid 7605086Sgblack@eecs.umich.eduDTB::serialize(std::ostream &os) 7615086Sgblack@eecs.umich.edu{ 7625086Sgblack@eecs.umich.edu TLB::serialize(os); 7635086Sgblack@eecs.umich.edu} 7645086Sgblack@eecs.umich.edu 7655086Sgblack@eecs.umich.eduvoid 7665086Sgblack@eecs.umich.eduDTB::unserialize(Checkpoint *cp, const std::string §ion) 7675086Sgblack@eecs.umich.edu{ 7685086Sgblack@eecs.umich.edu TLB::unserialize(cp, section); 7695086Sgblack@eecs.umich.edu} 7705086Sgblack@eecs.umich.edu 7715086Sgblack@eecs.umich.edu/* end namespace X86ISA */ } 7725086Sgblack@eecs.umich.edu 7734997Sgblack@eecs.umich.eduX86ISA::ITB * 7744997Sgblack@eecs.umich.eduX86ITBParams::create() 7754997Sgblack@eecs.umich.edu{ 7765038Sgblack@eecs.umich.edu return new X86ISA::ITB(this); 7774997Sgblack@eecs.umich.edu} 7784997Sgblack@eecs.umich.edu 7794997Sgblack@eecs.umich.eduX86ISA::DTB * 7804997Sgblack@eecs.umich.eduX86DTBParams::create() 7814997Sgblack@eecs.umich.edu{ 7825038Sgblack@eecs.umich.edu return new X86ISA::DTB(this); 7834997Sgblack@eecs.umich.edu} 784