tlb.cc revision 5894
14997Sgblack@eecs.umich.edu/* 25417Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 34997Sgblack@eecs.umich.edu * All rights reserved. 44997Sgblack@eecs.umich.edu * 54997Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 64997Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 74997Sgblack@eecs.umich.edu * following conditions are met: 84997Sgblack@eecs.umich.edu * 94997Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 104997Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 114997Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. Illustrative 124997Sgblack@eecs.umich.edu * examples of non-commercial use are academic research, personal study, 134997Sgblack@eecs.umich.edu * teaching, education and corporate research & development. 144997Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for 154997Sgblack@eecs.umich.edu * commercial advantage and providing services using the software for 164997Sgblack@eecs.umich.edu * commercial advantage. 174997Sgblack@eecs.umich.edu * 184997Sgblack@eecs.umich.edu * If you wish to use this software or functionality therein that may be 194997Sgblack@eecs.umich.edu * covered by patents for commercial use, please contact: 204997Sgblack@eecs.umich.edu * Director of Intellectual Property Licensing 214997Sgblack@eecs.umich.edu * Office of Strategy and Technology 224997Sgblack@eecs.umich.edu * Hewlett-Packard Company 234997Sgblack@eecs.umich.edu * 1501 Page Mill Road 244997Sgblack@eecs.umich.edu * Palo Alto, California 94304 254997Sgblack@eecs.umich.edu * 264997Sgblack@eecs.umich.edu * Redistributions of source code must retain the above copyright notice, 274997Sgblack@eecs.umich.edu * this list of conditions and the following disclaimer. Redistributions 284997Sgblack@eecs.umich.edu * in binary form must reproduce the above copyright notice, this list of 294997Sgblack@eecs.umich.edu * conditions and the following disclaimer in the documentation and/or 304997Sgblack@eecs.umich.edu * other materials provided with the distribution. Neither the name of 314997Sgblack@eecs.umich.edu * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 324997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 334997Sgblack@eecs.umich.edu * this software without specific prior written permission. No right of 344997Sgblack@eecs.umich.edu * sublicense is granted herewith. Derivatives of the software and 354997Sgblack@eecs.umich.edu * output created using the software may be prepared, but only for 364997Sgblack@eecs.umich.edu * Non-Commercial Uses. Derivatives of the software may be shared with 374997Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 384997Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 394997Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 404997Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where 414997Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 424997Sgblack@eecs.umich.edu * 434997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 444997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 454997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 464997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 474997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 484997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 494997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 504997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 514997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 524997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 534997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 544997Sgblack@eecs.umich.edu * 554997Sgblack@eecs.umich.edu * Authors: Gabe Black 564997Sgblack@eecs.umich.edu */ 574997Sgblack@eecs.umich.edu 584997Sgblack@eecs.umich.edu#include <cstring> 594997Sgblack@eecs.umich.edu 605086Sgblack@eecs.umich.edu#include "config/full_system.hh" 615086Sgblack@eecs.umich.edu 625124Sgblack@eecs.umich.edu#include "arch/x86/pagetable.hh" 635086Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh" 645149Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 655086Sgblack@eecs.umich.edu#include "base/bitfield.hh" 665086Sgblack@eecs.umich.edu#include "base/trace.hh" 675237Sgblack@eecs.umich.edu#include "config/full_system.hh" 685086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 695086Sgblack@eecs.umich.edu#include "cpu/base.hh" 705086Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 715086Sgblack@eecs.umich.edu#include "mem/request.hh" 725245Sgblack@eecs.umich.edu 735245Sgblack@eecs.umich.edu#if FULL_SYSTEM 745245Sgblack@eecs.umich.edu#include "arch/x86/pagetable_walker.hh" 755245Sgblack@eecs.umich.edu#endif 765086Sgblack@eecs.umich.edu 775086Sgblack@eecs.umich.edunamespace X86ISA { 785086Sgblack@eecs.umich.edu 795358Sgblack@eecs.umich.eduTLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size) 805124Sgblack@eecs.umich.edu{ 815124Sgblack@eecs.umich.edu tlb = new TlbEntry[size]; 825124Sgblack@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 835124Sgblack@eecs.umich.edu 845124Sgblack@eecs.umich.edu for (int x = 0; x < size; x++) 855124Sgblack@eecs.umich.edu freeList.push_back(&tlb[x]); 865124Sgblack@eecs.umich.edu 875237Sgblack@eecs.umich.edu#if FULL_SYSTEM 885245Sgblack@eecs.umich.edu walker = p->walker; 895245Sgblack@eecs.umich.edu walker->setTLB(this); 905245Sgblack@eecs.umich.edu#endif 915236Sgblack@eecs.umich.edu} 925236Sgblack@eecs.umich.edu 935236Sgblack@eecs.umich.eduvoid 945124Sgblack@eecs.umich.eduTLB::insert(Addr vpn, TlbEntry &entry) 955124Sgblack@eecs.umich.edu{ 965124Sgblack@eecs.umich.edu //TODO Deal with conflicting entries 975124Sgblack@eecs.umich.edu 985124Sgblack@eecs.umich.edu TlbEntry *newEntry = NULL; 995124Sgblack@eecs.umich.edu if (!freeList.empty()) { 1005124Sgblack@eecs.umich.edu newEntry = freeList.front(); 1015124Sgblack@eecs.umich.edu freeList.pop_front(); 1025124Sgblack@eecs.umich.edu } else { 1035124Sgblack@eecs.umich.edu newEntry = entryList.back(); 1045124Sgblack@eecs.umich.edu entryList.pop_back(); 1055124Sgblack@eecs.umich.edu } 1065124Sgblack@eecs.umich.edu *newEntry = entry; 1075124Sgblack@eecs.umich.edu newEntry->vaddr = vpn; 1085124Sgblack@eecs.umich.edu entryList.push_front(newEntry); 1095124Sgblack@eecs.umich.edu} 1105124Sgblack@eecs.umich.edu 1115360Sgblack@eecs.umich.eduTLB::EntryList::iterator 1125360Sgblack@eecs.umich.eduTLB::lookupIt(Addr va, bool update_lru) 1135124Sgblack@eecs.umich.edu{ 1145124Sgblack@eecs.umich.edu //TODO make this smarter at some point 1155124Sgblack@eecs.umich.edu EntryList::iterator entry; 1165124Sgblack@eecs.umich.edu for (entry = entryList.begin(); entry != entryList.end(); entry++) { 1175124Sgblack@eecs.umich.edu if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) { 1185124Sgblack@eecs.umich.edu DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x " 1195124Sgblack@eecs.umich.edu "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size); 1205124Sgblack@eecs.umich.edu if (update_lru) { 1215360Sgblack@eecs.umich.edu entryList.push_front(*entry); 1225124Sgblack@eecs.umich.edu entryList.erase(entry); 1235360Sgblack@eecs.umich.edu entry = entryList.begin(); 1245124Sgblack@eecs.umich.edu } 1255360Sgblack@eecs.umich.edu break; 1265124Sgblack@eecs.umich.edu } 1275124Sgblack@eecs.umich.edu } 1285360Sgblack@eecs.umich.edu return entry; 1295360Sgblack@eecs.umich.edu} 1305360Sgblack@eecs.umich.edu 1315360Sgblack@eecs.umich.eduTlbEntry * 1325360Sgblack@eecs.umich.eduTLB::lookup(Addr va, bool update_lru) 1335360Sgblack@eecs.umich.edu{ 1345360Sgblack@eecs.umich.edu EntryList::iterator entry = lookupIt(va, update_lru); 1355360Sgblack@eecs.umich.edu if (entry == entryList.end()) 1365360Sgblack@eecs.umich.edu return NULL; 1375360Sgblack@eecs.umich.edu else 1385360Sgblack@eecs.umich.edu return *entry; 1395124Sgblack@eecs.umich.edu} 1405124Sgblack@eecs.umich.edu 1415245Sgblack@eecs.umich.edu#if FULL_SYSTEM 1425245Sgblack@eecs.umich.eduvoid 1435881Sgblack@eecs.umich.eduTLB::walk(ThreadContext * _tc, Addr vaddr, bool write, bool execute) 1445245Sgblack@eecs.umich.edu{ 1455881Sgblack@eecs.umich.edu walker->start(_tc, vaddr, write, execute); 1465245Sgblack@eecs.umich.edu} 1475245Sgblack@eecs.umich.edu#endif 1485245Sgblack@eecs.umich.edu 1495124Sgblack@eecs.umich.eduvoid 1505124Sgblack@eecs.umich.eduTLB::invalidateAll() 1515124Sgblack@eecs.umich.edu{ 1525242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all entries.\n"); 1535242Sgblack@eecs.umich.edu while (!entryList.empty()) { 1545242Sgblack@eecs.umich.edu TlbEntry *entry = entryList.front(); 1555242Sgblack@eecs.umich.edu entryList.pop_front(); 1565242Sgblack@eecs.umich.edu freeList.push_back(entry); 1575242Sgblack@eecs.umich.edu } 1585124Sgblack@eecs.umich.edu} 1595124Sgblack@eecs.umich.edu 1605124Sgblack@eecs.umich.eduvoid 1615357Sgblack@eecs.umich.eduTLB::setConfigAddress(uint32_t addr) 1625357Sgblack@eecs.umich.edu{ 1635357Sgblack@eecs.umich.edu configAddress = addr; 1645357Sgblack@eecs.umich.edu} 1655357Sgblack@eecs.umich.edu 1665357Sgblack@eecs.umich.eduvoid 1675124Sgblack@eecs.umich.eduTLB::invalidateNonGlobal() 1685124Sgblack@eecs.umich.edu{ 1695242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all non global entries.\n"); 1705242Sgblack@eecs.umich.edu EntryList::iterator entryIt; 1715242Sgblack@eecs.umich.edu for (entryIt = entryList.begin(); entryIt != entryList.end();) { 1725242Sgblack@eecs.umich.edu if (!(*entryIt)->global) { 1735242Sgblack@eecs.umich.edu freeList.push_back(*entryIt); 1745242Sgblack@eecs.umich.edu entryList.erase(entryIt++); 1755242Sgblack@eecs.umich.edu } else { 1765242Sgblack@eecs.umich.edu entryIt++; 1775242Sgblack@eecs.umich.edu } 1785242Sgblack@eecs.umich.edu } 1795124Sgblack@eecs.umich.edu} 1805124Sgblack@eecs.umich.edu 1815124Sgblack@eecs.umich.eduvoid 1825358Sgblack@eecs.umich.eduTLB::demapPage(Addr va, uint64_t asn) 1835086Sgblack@eecs.umich.edu{ 1845359Sgblack@eecs.umich.edu EntryList::iterator entry = lookupIt(va, false); 1855359Sgblack@eecs.umich.edu if (entry != entryList.end()) { 1865359Sgblack@eecs.umich.edu freeList.push_back(*entry); 1875359Sgblack@eecs.umich.edu entryList.erase(entry); 1885359Sgblack@eecs.umich.edu } 1895086Sgblack@eecs.umich.edu} 1905086Sgblack@eecs.umich.edu 1915140Sgblack@eecs.umich.edutemplate<class TlbFault> 1925086Sgblack@eecs.umich.eduFault 1935894Sgblack@eecs.umich.eduTLB::translateAtomic(RequestPtr req, ThreadContext *tc, 1945891Sgblack@eecs.umich.edu bool write, bool execute) 1955086Sgblack@eecs.umich.edu{ 1965124Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 1975140Sgblack@eecs.umich.edu DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 1985124Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 1995124Sgblack@eecs.umich.edu bool storeCheck = flags & StoreCheck; 2005140Sgblack@eecs.umich.edu 2015294Sgblack@eecs.umich.edu int seg = flags & mask(4); 2025124Sgblack@eecs.umich.edu 2035124Sgblack@eecs.umich.edu //XXX Junk code to surpress the warning 2045149Sgblack@eecs.umich.edu if (storeCheck); 2055149Sgblack@eecs.umich.edu 2065149Sgblack@eecs.umich.edu // If this is true, we're dealing with a request to read an internal 2075149Sgblack@eecs.umich.edu // value. 2085294Sgblack@eecs.umich.edu if (seg == SEGMENT_REG_MS) { 2095243Sgblack@eecs.umich.edu DPRINTF(TLB, "Addresses references internal memory.\n"); 2105418Sgblack@eecs.umich.edu Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 2115149Sgblack@eecs.umich.edu if (prefix == IntAddrPrefixCPUID) { 2125149Sgblack@eecs.umich.edu panic("CPUID memory space not yet implemented!\n"); 2135149Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixMSR) { 2145418Sgblack@eecs.umich.edu vaddr = vaddr >> 3; 2155149Sgblack@eecs.umich.edu req->setMmapedIpr(true); 2165149Sgblack@eecs.umich.edu Addr regNum = 0; 2175149Sgblack@eecs.umich.edu switch (vaddr & ~IntAddrPrefixMask) { 2185149Sgblack@eecs.umich.edu case 0x10: 2195149Sgblack@eecs.umich.edu regNum = MISCREG_TSC; 2205149Sgblack@eecs.umich.edu break; 2215360Sgblack@eecs.umich.edu case 0x1B: 2225360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_BASE; 2235360Sgblack@eecs.umich.edu break; 2245149Sgblack@eecs.umich.edu case 0xFE: 2255149Sgblack@eecs.umich.edu regNum = MISCREG_MTRRCAP; 2265149Sgblack@eecs.umich.edu break; 2275149Sgblack@eecs.umich.edu case 0x174: 2285149Sgblack@eecs.umich.edu regNum = MISCREG_SYSENTER_CS; 2295149Sgblack@eecs.umich.edu break; 2305149Sgblack@eecs.umich.edu case 0x175: 2315149Sgblack@eecs.umich.edu regNum = MISCREG_SYSENTER_ESP; 2325149Sgblack@eecs.umich.edu break; 2335149Sgblack@eecs.umich.edu case 0x176: 2345149Sgblack@eecs.umich.edu regNum = MISCREG_SYSENTER_EIP; 2355149Sgblack@eecs.umich.edu break; 2365149Sgblack@eecs.umich.edu case 0x179: 2375149Sgblack@eecs.umich.edu regNum = MISCREG_MCG_CAP; 2385149Sgblack@eecs.umich.edu break; 2395149Sgblack@eecs.umich.edu case 0x17A: 2405149Sgblack@eecs.umich.edu regNum = MISCREG_MCG_STATUS; 2415149Sgblack@eecs.umich.edu break; 2425149Sgblack@eecs.umich.edu case 0x17B: 2435149Sgblack@eecs.umich.edu regNum = MISCREG_MCG_CTL; 2445149Sgblack@eecs.umich.edu break; 2455149Sgblack@eecs.umich.edu case 0x1D9: 2465149Sgblack@eecs.umich.edu regNum = MISCREG_DEBUG_CTL_MSR; 2475149Sgblack@eecs.umich.edu break; 2485149Sgblack@eecs.umich.edu case 0x1DB: 2495149Sgblack@eecs.umich.edu regNum = MISCREG_LAST_BRANCH_FROM_IP; 2505149Sgblack@eecs.umich.edu break; 2515149Sgblack@eecs.umich.edu case 0x1DC: 2525149Sgblack@eecs.umich.edu regNum = MISCREG_LAST_BRANCH_TO_IP; 2535149Sgblack@eecs.umich.edu break; 2545149Sgblack@eecs.umich.edu case 0x1DD: 2555149Sgblack@eecs.umich.edu regNum = MISCREG_LAST_EXCEPTION_FROM_IP; 2565149Sgblack@eecs.umich.edu break; 2575149Sgblack@eecs.umich.edu case 0x1DE: 2585149Sgblack@eecs.umich.edu regNum = MISCREG_LAST_EXCEPTION_TO_IP; 2595149Sgblack@eecs.umich.edu break; 2605149Sgblack@eecs.umich.edu case 0x200: 2615149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_0; 2625149Sgblack@eecs.umich.edu break; 2635149Sgblack@eecs.umich.edu case 0x201: 2645149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_0; 2655149Sgblack@eecs.umich.edu break; 2665149Sgblack@eecs.umich.edu case 0x202: 2675149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_1; 2685149Sgblack@eecs.umich.edu break; 2695149Sgblack@eecs.umich.edu case 0x203: 2705149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_1; 2715149Sgblack@eecs.umich.edu break; 2725149Sgblack@eecs.umich.edu case 0x204: 2735149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_2; 2745149Sgblack@eecs.umich.edu break; 2755149Sgblack@eecs.umich.edu case 0x205: 2765149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_2; 2775149Sgblack@eecs.umich.edu break; 2785149Sgblack@eecs.umich.edu case 0x206: 2795149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_3; 2805149Sgblack@eecs.umich.edu break; 2815149Sgblack@eecs.umich.edu case 0x207: 2825149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_3; 2835149Sgblack@eecs.umich.edu break; 2845149Sgblack@eecs.umich.edu case 0x208: 2855149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_4; 2865149Sgblack@eecs.umich.edu break; 2875149Sgblack@eecs.umich.edu case 0x209: 2885149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_4; 2895149Sgblack@eecs.umich.edu break; 2905149Sgblack@eecs.umich.edu case 0x20A: 2915149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_5; 2925149Sgblack@eecs.umich.edu break; 2935149Sgblack@eecs.umich.edu case 0x20B: 2945149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_5; 2955149Sgblack@eecs.umich.edu break; 2965149Sgblack@eecs.umich.edu case 0x20C: 2975149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_6; 2985149Sgblack@eecs.umich.edu break; 2995149Sgblack@eecs.umich.edu case 0x20D: 3005149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_6; 3015149Sgblack@eecs.umich.edu break; 3025149Sgblack@eecs.umich.edu case 0x20E: 3035149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_7; 3045149Sgblack@eecs.umich.edu break; 3055149Sgblack@eecs.umich.edu case 0x20F: 3065149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_7; 3075149Sgblack@eecs.umich.edu break; 3085149Sgblack@eecs.umich.edu case 0x250: 3095149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_64K_00000; 3105149Sgblack@eecs.umich.edu break; 3115149Sgblack@eecs.umich.edu case 0x258: 3125149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_16K_80000; 3135149Sgblack@eecs.umich.edu break; 3145149Sgblack@eecs.umich.edu case 0x259: 3155149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_16K_A0000; 3165149Sgblack@eecs.umich.edu break; 3175149Sgblack@eecs.umich.edu case 0x268: 3185149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_C0000; 3195149Sgblack@eecs.umich.edu break; 3205149Sgblack@eecs.umich.edu case 0x269: 3215149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_C8000; 3225149Sgblack@eecs.umich.edu break; 3235149Sgblack@eecs.umich.edu case 0x26A: 3245149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_D0000; 3255149Sgblack@eecs.umich.edu break; 3265149Sgblack@eecs.umich.edu case 0x26B: 3275149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_D8000; 3285149Sgblack@eecs.umich.edu break; 3295149Sgblack@eecs.umich.edu case 0x26C: 3305149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_E0000; 3315149Sgblack@eecs.umich.edu break; 3325149Sgblack@eecs.umich.edu case 0x26D: 3335149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_E8000; 3345149Sgblack@eecs.umich.edu break; 3355149Sgblack@eecs.umich.edu case 0x26E: 3365149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_F0000; 3375149Sgblack@eecs.umich.edu break; 3385149Sgblack@eecs.umich.edu case 0x26F: 3395149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_F8000; 3405149Sgblack@eecs.umich.edu break; 3415149Sgblack@eecs.umich.edu case 0x277: 3425149Sgblack@eecs.umich.edu regNum = MISCREG_PAT; 3435149Sgblack@eecs.umich.edu break; 3445149Sgblack@eecs.umich.edu case 0x2FF: 3455149Sgblack@eecs.umich.edu regNum = MISCREG_DEF_TYPE; 3465149Sgblack@eecs.umich.edu break; 3475149Sgblack@eecs.umich.edu case 0x400: 3485149Sgblack@eecs.umich.edu regNum = MISCREG_MC0_CTL; 3495149Sgblack@eecs.umich.edu break; 3505149Sgblack@eecs.umich.edu case 0x404: 3515149Sgblack@eecs.umich.edu regNum = MISCREG_MC1_CTL; 3525149Sgblack@eecs.umich.edu break; 3535149Sgblack@eecs.umich.edu case 0x408: 3545149Sgblack@eecs.umich.edu regNum = MISCREG_MC2_CTL; 3555149Sgblack@eecs.umich.edu break; 3565149Sgblack@eecs.umich.edu case 0x40C: 3575149Sgblack@eecs.umich.edu regNum = MISCREG_MC3_CTL; 3585149Sgblack@eecs.umich.edu break; 3595149Sgblack@eecs.umich.edu case 0x410: 3605149Sgblack@eecs.umich.edu regNum = MISCREG_MC4_CTL; 3615149Sgblack@eecs.umich.edu break; 3625419Sgblack@eecs.umich.edu case 0x414: 3635419Sgblack@eecs.umich.edu regNum = MISCREG_MC5_CTL; 3645419Sgblack@eecs.umich.edu break; 3655419Sgblack@eecs.umich.edu case 0x418: 3665419Sgblack@eecs.umich.edu regNum = MISCREG_MC6_CTL; 3675419Sgblack@eecs.umich.edu break; 3685419Sgblack@eecs.umich.edu case 0x41C: 3695419Sgblack@eecs.umich.edu regNum = MISCREG_MC7_CTL; 3705419Sgblack@eecs.umich.edu break; 3715149Sgblack@eecs.umich.edu case 0x401: 3725149Sgblack@eecs.umich.edu regNum = MISCREG_MC0_STATUS; 3735149Sgblack@eecs.umich.edu break; 3745149Sgblack@eecs.umich.edu case 0x405: 3755149Sgblack@eecs.umich.edu regNum = MISCREG_MC1_STATUS; 3765149Sgblack@eecs.umich.edu break; 3775149Sgblack@eecs.umich.edu case 0x409: 3785149Sgblack@eecs.umich.edu regNum = MISCREG_MC2_STATUS; 3795149Sgblack@eecs.umich.edu break; 3805149Sgblack@eecs.umich.edu case 0x40D: 3815149Sgblack@eecs.umich.edu regNum = MISCREG_MC3_STATUS; 3825149Sgblack@eecs.umich.edu break; 3835149Sgblack@eecs.umich.edu case 0x411: 3845149Sgblack@eecs.umich.edu regNum = MISCREG_MC4_STATUS; 3855149Sgblack@eecs.umich.edu break; 3865419Sgblack@eecs.umich.edu case 0x415: 3875419Sgblack@eecs.umich.edu regNum = MISCREG_MC5_STATUS; 3885419Sgblack@eecs.umich.edu break; 3895419Sgblack@eecs.umich.edu case 0x419: 3905419Sgblack@eecs.umich.edu regNum = MISCREG_MC6_STATUS; 3915419Sgblack@eecs.umich.edu break; 3925419Sgblack@eecs.umich.edu case 0x41D: 3935419Sgblack@eecs.umich.edu regNum = MISCREG_MC7_STATUS; 3945419Sgblack@eecs.umich.edu break; 3955149Sgblack@eecs.umich.edu case 0x402: 3965149Sgblack@eecs.umich.edu regNum = MISCREG_MC0_ADDR; 3975149Sgblack@eecs.umich.edu break; 3985149Sgblack@eecs.umich.edu case 0x406: 3995149Sgblack@eecs.umich.edu regNum = MISCREG_MC1_ADDR; 4005149Sgblack@eecs.umich.edu break; 4015149Sgblack@eecs.umich.edu case 0x40A: 4025149Sgblack@eecs.umich.edu regNum = MISCREG_MC2_ADDR; 4035149Sgblack@eecs.umich.edu break; 4045149Sgblack@eecs.umich.edu case 0x40E: 4055149Sgblack@eecs.umich.edu regNum = MISCREG_MC3_ADDR; 4065149Sgblack@eecs.umich.edu break; 4075149Sgblack@eecs.umich.edu case 0x412: 4085149Sgblack@eecs.umich.edu regNum = MISCREG_MC4_ADDR; 4095149Sgblack@eecs.umich.edu break; 4105419Sgblack@eecs.umich.edu case 0x416: 4115419Sgblack@eecs.umich.edu regNum = MISCREG_MC5_ADDR; 4125419Sgblack@eecs.umich.edu break; 4135419Sgblack@eecs.umich.edu case 0x41A: 4145419Sgblack@eecs.umich.edu regNum = MISCREG_MC6_ADDR; 4155419Sgblack@eecs.umich.edu break; 4165419Sgblack@eecs.umich.edu case 0x41E: 4175419Sgblack@eecs.umich.edu regNum = MISCREG_MC7_ADDR; 4185419Sgblack@eecs.umich.edu break; 4195149Sgblack@eecs.umich.edu case 0x403: 4205149Sgblack@eecs.umich.edu regNum = MISCREG_MC0_MISC; 4215149Sgblack@eecs.umich.edu break; 4225149Sgblack@eecs.umich.edu case 0x407: 4235149Sgblack@eecs.umich.edu regNum = MISCREG_MC1_MISC; 4245149Sgblack@eecs.umich.edu break; 4255149Sgblack@eecs.umich.edu case 0x40B: 4265149Sgblack@eecs.umich.edu regNum = MISCREG_MC2_MISC; 4275149Sgblack@eecs.umich.edu break; 4285149Sgblack@eecs.umich.edu case 0x40F: 4295149Sgblack@eecs.umich.edu regNum = MISCREG_MC3_MISC; 4305149Sgblack@eecs.umich.edu break; 4315149Sgblack@eecs.umich.edu case 0x413: 4325149Sgblack@eecs.umich.edu regNum = MISCREG_MC4_MISC; 4335149Sgblack@eecs.umich.edu break; 4345419Sgblack@eecs.umich.edu case 0x417: 4355419Sgblack@eecs.umich.edu regNum = MISCREG_MC5_MISC; 4365419Sgblack@eecs.umich.edu break; 4375419Sgblack@eecs.umich.edu case 0x41B: 4385419Sgblack@eecs.umich.edu regNum = MISCREG_MC6_MISC; 4395419Sgblack@eecs.umich.edu break; 4405419Sgblack@eecs.umich.edu case 0x41F: 4415419Sgblack@eecs.umich.edu regNum = MISCREG_MC7_MISC; 4425419Sgblack@eecs.umich.edu break; 4435149Sgblack@eecs.umich.edu case 0xC0000080: 4445149Sgblack@eecs.umich.edu regNum = MISCREG_EFER; 4455149Sgblack@eecs.umich.edu break; 4465149Sgblack@eecs.umich.edu case 0xC0000081: 4475149Sgblack@eecs.umich.edu regNum = MISCREG_STAR; 4485149Sgblack@eecs.umich.edu break; 4495149Sgblack@eecs.umich.edu case 0xC0000082: 4505149Sgblack@eecs.umich.edu regNum = MISCREG_LSTAR; 4515149Sgblack@eecs.umich.edu break; 4525149Sgblack@eecs.umich.edu case 0xC0000083: 4535149Sgblack@eecs.umich.edu regNum = MISCREG_CSTAR; 4545149Sgblack@eecs.umich.edu break; 4555149Sgblack@eecs.umich.edu case 0xC0000084: 4565149Sgblack@eecs.umich.edu regNum = MISCREG_SF_MASK; 4575149Sgblack@eecs.umich.edu break; 4585149Sgblack@eecs.umich.edu case 0xC0000100: 4595149Sgblack@eecs.umich.edu regNum = MISCREG_FS_BASE; 4605149Sgblack@eecs.umich.edu break; 4615149Sgblack@eecs.umich.edu case 0xC0000101: 4625149Sgblack@eecs.umich.edu regNum = MISCREG_GS_BASE; 4635149Sgblack@eecs.umich.edu break; 4645149Sgblack@eecs.umich.edu case 0xC0000102: 4655149Sgblack@eecs.umich.edu regNum = MISCREG_KERNEL_GS_BASE; 4665149Sgblack@eecs.umich.edu break; 4675149Sgblack@eecs.umich.edu case 0xC0000103: 4685149Sgblack@eecs.umich.edu regNum = MISCREG_TSC_AUX; 4695149Sgblack@eecs.umich.edu break; 4705149Sgblack@eecs.umich.edu case 0xC0010000: 4715149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL0; 4725149Sgblack@eecs.umich.edu break; 4735149Sgblack@eecs.umich.edu case 0xC0010001: 4745149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL1; 4755149Sgblack@eecs.umich.edu break; 4765149Sgblack@eecs.umich.edu case 0xC0010002: 4775149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL2; 4785149Sgblack@eecs.umich.edu break; 4795149Sgblack@eecs.umich.edu case 0xC0010003: 4805149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL3; 4815149Sgblack@eecs.umich.edu break; 4825149Sgblack@eecs.umich.edu case 0xC0010004: 4835149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR0; 4845149Sgblack@eecs.umich.edu break; 4855149Sgblack@eecs.umich.edu case 0xC0010005: 4865149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR1; 4875149Sgblack@eecs.umich.edu break; 4885149Sgblack@eecs.umich.edu case 0xC0010006: 4895149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR2; 4905149Sgblack@eecs.umich.edu break; 4915149Sgblack@eecs.umich.edu case 0xC0010007: 4925149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR3; 4935149Sgblack@eecs.umich.edu break; 4945149Sgblack@eecs.umich.edu case 0xC0010010: 4955149Sgblack@eecs.umich.edu regNum = MISCREG_SYSCFG; 4965149Sgblack@eecs.umich.edu break; 4975149Sgblack@eecs.umich.edu case 0xC0010016: 4985149Sgblack@eecs.umich.edu regNum = MISCREG_IORR_BASE0; 4995149Sgblack@eecs.umich.edu break; 5005149Sgblack@eecs.umich.edu case 0xC0010017: 5015149Sgblack@eecs.umich.edu regNum = MISCREG_IORR_BASE1; 5025149Sgblack@eecs.umich.edu break; 5035149Sgblack@eecs.umich.edu case 0xC0010018: 5045149Sgblack@eecs.umich.edu regNum = MISCREG_IORR_MASK0; 5055149Sgblack@eecs.umich.edu break; 5065149Sgblack@eecs.umich.edu case 0xC0010019: 5075149Sgblack@eecs.umich.edu regNum = MISCREG_IORR_MASK1; 5085149Sgblack@eecs.umich.edu break; 5095149Sgblack@eecs.umich.edu case 0xC001001A: 5105149Sgblack@eecs.umich.edu regNum = MISCREG_TOP_MEM; 5115149Sgblack@eecs.umich.edu break; 5125149Sgblack@eecs.umich.edu case 0xC001001D: 5135149Sgblack@eecs.umich.edu regNum = MISCREG_TOP_MEM2; 5145149Sgblack@eecs.umich.edu break; 5155149Sgblack@eecs.umich.edu case 0xC0010114: 5165149Sgblack@eecs.umich.edu regNum = MISCREG_VM_CR; 5175149Sgblack@eecs.umich.edu break; 5185149Sgblack@eecs.umich.edu case 0xC0010115: 5195149Sgblack@eecs.umich.edu regNum = MISCREG_IGNNE; 5205149Sgblack@eecs.umich.edu break; 5215149Sgblack@eecs.umich.edu case 0xC0010116: 5225149Sgblack@eecs.umich.edu regNum = MISCREG_SMM_CTL; 5235149Sgblack@eecs.umich.edu break; 5245149Sgblack@eecs.umich.edu case 0xC0010117: 5255149Sgblack@eecs.umich.edu regNum = MISCREG_VM_HSAVE_PA; 5265149Sgblack@eecs.umich.edu break; 5275149Sgblack@eecs.umich.edu default: 5285149Sgblack@eecs.umich.edu return new GeneralProtection(0); 5295149Sgblack@eecs.umich.edu } 5305149Sgblack@eecs.umich.edu //The index is multiplied by the size of a MiscReg so that 5315149Sgblack@eecs.umich.edu //any memory dependence calculations will not see these as 5325149Sgblack@eecs.umich.edu //overlapping. 5335149Sgblack@eecs.umich.edu req->setPaddr(regNum * sizeof(MiscReg)); 5345149Sgblack@eecs.umich.edu return NoFault; 5355323Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixIO) { 5365323Sgblack@eecs.umich.edu // TODO If CPL > IOPL or in virtual mode, check the I/O permission 5375323Sgblack@eecs.umich.edu // bitmap in the TSS. 5385323Sgblack@eecs.umich.edu 5395323Sgblack@eecs.umich.edu Addr IOPort = vaddr & ~IntAddrPrefixMask; 5405323Sgblack@eecs.umich.edu // Make sure the address fits in the expected 16 bit IO address 5415323Sgblack@eecs.umich.edu // space. 5425323Sgblack@eecs.umich.edu assert(!(IOPort & ~0xFFFF)); 5435357Sgblack@eecs.umich.edu if (IOPort == 0xCF8 && req->getSize() == 4) { 5445357Sgblack@eecs.umich.edu req->setMmapedIpr(true); 5455357Sgblack@eecs.umich.edu req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 5465357Sgblack@eecs.umich.edu } else if ((IOPort & ~mask(2)) == 0xCFC) { 5475357Sgblack@eecs.umich.edu Addr configAddress = 5485357Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 5495357Sgblack@eecs.umich.edu if (bits(configAddress, 31, 31)) { 5505357Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixPciConfig | 5515837Sgblack@eecs.umich.edu mbits(configAddress, 30, 2) | 5525837Sgblack@eecs.umich.edu (IOPort & mask(2))); 5535357Sgblack@eecs.umich.edu } 5545357Sgblack@eecs.umich.edu } else { 5555357Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 5565357Sgblack@eecs.umich.edu } 5575323Sgblack@eecs.umich.edu return NoFault; 5585149Sgblack@eecs.umich.edu } else { 5595149Sgblack@eecs.umich.edu panic("Access to unrecognized internal address space %#x.\n", 5605149Sgblack@eecs.umich.edu prefix); 5615149Sgblack@eecs.umich.edu } 5625149Sgblack@eecs.umich.edu } 5635124Sgblack@eecs.umich.edu 5645140Sgblack@eecs.umich.edu // Get cr0. This will tell us how to do translation. We'll assume it was 5655140Sgblack@eecs.umich.edu // verified to be correct and consistent when set. 5665140Sgblack@eecs.umich.edu CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 5675140Sgblack@eecs.umich.edu 5685140Sgblack@eecs.umich.edu // If protected mode has been enabled... 5695140Sgblack@eecs.umich.edu if (cr0.pe) { 5705237Sgblack@eecs.umich.edu DPRINTF(TLB, "In protected mode.\n"); 5715140Sgblack@eecs.umich.edu Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 5725140Sgblack@eecs.umich.edu SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR); 5735140Sgblack@eecs.umich.edu // If we're not in 64-bit mode, do protection/limit checks 5745140Sgblack@eecs.umich.edu if (!efer.lma || !csAttr.longMode) { 5755237Sgblack@eecs.umich.edu DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 5765431Sgblack@eecs.umich.edu // Check for a NULL segment selector. 5775431Sgblack@eecs.umich.edu if (!tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 5785431Sgblack@eecs.umich.edu return new GeneralProtection(0); 5795433Sgblack@eecs.umich.edu bool expandDown = false; 5805433Sgblack@eecs.umich.edu if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 5815433Sgblack@eecs.umich.edu SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 5825433Sgblack@eecs.umich.edu if (!attr.writable && write) 5835433Sgblack@eecs.umich.edu return new GeneralProtection(0); 5845433Sgblack@eecs.umich.edu if (!attr.readable && !write && !execute) 5855433Sgblack@eecs.umich.edu return new GeneralProtection(0); 5865433Sgblack@eecs.umich.edu expandDown = attr.expandDown; 5875433Sgblack@eecs.umich.edu } 5885140Sgblack@eecs.umich.edu Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 5895140Sgblack@eecs.umich.edu Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 5905433Sgblack@eecs.umich.edu if (expandDown) { 5915237Sgblack@eecs.umich.edu DPRINTF(TLB, "Checking an expand down segment.\n"); 5925140Sgblack@eecs.umich.edu // We don't have to worry about the access going around the 5935140Sgblack@eecs.umich.edu // end of memory because accesses will be broken up into 5945140Sgblack@eecs.umich.edu // pieces at boundaries aligned on sizes smaller than an 5955140Sgblack@eecs.umich.edu // entire address space. We do have to worry about the limit 5965140Sgblack@eecs.umich.edu // being less than the base. 5975140Sgblack@eecs.umich.edu if (limit < base) { 5985140Sgblack@eecs.umich.edu if (limit < vaddr + req->getSize() && vaddr < base) 5995140Sgblack@eecs.umich.edu return new GeneralProtection(0); 6005140Sgblack@eecs.umich.edu } else { 6015140Sgblack@eecs.umich.edu if (limit < vaddr + req->getSize()) 6025140Sgblack@eecs.umich.edu return new GeneralProtection(0); 6035140Sgblack@eecs.umich.edu } 6045140Sgblack@eecs.umich.edu } else { 6055140Sgblack@eecs.umich.edu if (limit < base) { 6065140Sgblack@eecs.umich.edu if (vaddr <= limit || vaddr + req->getSize() >= base) 6075140Sgblack@eecs.umich.edu return new GeneralProtection(0); 6085140Sgblack@eecs.umich.edu } else { 6095140Sgblack@eecs.umich.edu if (vaddr <= limit && vaddr + req->getSize() >= base) 6105140Sgblack@eecs.umich.edu return new GeneralProtection(0); 6115140Sgblack@eecs.umich.edu } 6125140Sgblack@eecs.umich.edu } 6135140Sgblack@eecs.umich.edu } 6145140Sgblack@eecs.umich.edu // If paging is enabled, do the translation. 6155140Sgblack@eecs.umich.edu if (cr0.pg) { 6165237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging enabled.\n"); 6175140Sgblack@eecs.umich.edu // The vaddr already has the segment base applied. 6185140Sgblack@eecs.umich.edu TlbEntry *entry = lookup(vaddr); 6195140Sgblack@eecs.umich.edu if (!entry) { 6205881Sgblack@eecs.umich.edu return new TlbFault(vaddr, write, execute); 6215140Sgblack@eecs.umich.edu } else { 6225140Sgblack@eecs.umich.edu // Do paging protection checks. 6235237Sgblack@eecs.umich.edu DPRINTF(TLB, "Entry found with paddr %#x, doing protection checks.\n", entry->paddr); 6245237Sgblack@eecs.umich.edu Addr paddr = entry->paddr | (vaddr & (entry->size-1)); 6255237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 6265140Sgblack@eecs.umich.edu req->setPaddr(paddr); 6275140Sgblack@eecs.umich.edu } 6285140Sgblack@eecs.umich.edu } else { 6295140Sgblack@eecs.umich.edu //Use the address which already has segmentation applied. 6305237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging disabled.\n"); 6315237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 6325140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 6335140Sgblack@eecs.umich.edu } 6345124Sgblack@eecs.umich.edu } else { 6355140Sgblack@eecs.umich.edu // Real mode 6365237Sgblack@eecs.umich.edu DPRINTF(TLB, "In real mode.\n"); 6375237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 6385140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 6395124Sgblack@eecs.umich.edu } 6405360Sgblack@eecs.umich.edu // Check for an access to the local APIC 6415374Sgblack@eecs.umich.edu#if FULL_SYSTEM 6425360Sgblack@eecs.umich.edu LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 6435648Sgblack@eecs.umich.edu Addr baseAddr = localApicBase.base * PageBytes; 6445360Sgblack@eecs.umich.edu Addr paddr = req->getPaddr(); 6455648Sgblack@eecs.umich.edu if (baseAddr <= paddr && baseAddr + PageBytes > paddr) { 6465417Sgblack@eecs.umich.edu // The Intel developer's manuals say the below restrictions apply, 6475417Sgblack@eecs.umich.edu // but the linux kernel, because of a compiler optimization, breaks 6485417Sgblack@eecs.umich.edu // them. 6495417Sgblack@eecs.umich.edu /* 6505360Sgblack@eecs.umich.edu // Check alignment 6515360Sgblack@eecs.umich.edu if (paddr & ((32/8) - 1)) 6525360Sgblack@eecs.umich.edu return new GeneralProtection(0); 6535360Sgblack@eecs.umich.edu // Check access size 6545360Sgblack@eecs.umich.edu if (req->getSize() != (32/8)) 6555360Sgblack@eecs.umich.edu return new GeneralProtection(0); 6565417Sgblack@eecs.umich.edu */ 6575648Sgblack@eecs.umich.edu // Force the access to be uncacheable. 6585736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 6595714Shsul@eecs.umich.edu req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr)); 6605360Sgblack@eecs.umich.edu } 6615374Sgblack@eecs.umich.edu#endif 6625086Sgblack@eecs.umich.edu return NoFault; 6635086Sgblack@eecs.umich.edu}; 6645086Sgblack@eecs.umich.edu 6655140Sgblack@eecs.umich.eduFault 6665894Sgblack@eecs.umich.eduDTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write) 6675140Sgblack@eecs.umich.edu{ 6685891Sgblack@eecs.umich.edu return TLB::translateAtomic<FakeDTLBFault>(req, tc, write, false); 6695140Sgblack@eecs.umich.edu} 6705140Sgblack@eecs.umich.edu 6715894Sgblack@eecs.umich.eduvoid 6725894Sgblack@eecs.umich.eduDTB::translateTiming(RequestPtr req, ThreadContext *tc, 6735894Sgblack@eecs.umich.edu Translation *translation, bool write) 6745894Sgblack@eecs.umich.edu{ 6755894Sgblack@eecs.umich.edu assert(translation); 6765894Sgblack@eecs.umich.edu translation->finish(translateAtomic(req, tc, write), req, tc, write); 6775894Sgblack@eecs.umich.edu} 6785894Sgblack@eecs.umich.edu 6795140Sgblack@eecs.umich.eduFault 6805894Sgblack@eecs.umich.eduITB::translateAtomic(RequestPtr req, ThreadContext *tc) 6815140Sgblack@eecs.umich.edu{ 6825891Sgblack@eecs.umich.edu return TLB::translateAtomic<FakeITLBFault>(req, tc, false, true); 6835140Sgblack@eecs.umich.edu} 6845140Sgblack@eecs.umich.edu 6855894Sgblack@eecs.umich.eduvoid 6865894Sgblack@eecs.umich.eduITB::translateTiming(RequestPtr req, ThreadContext *tc, 6875894Sgblack@eecs.umich.edu Translation *translation) 6885894Sgblack@eecs.umich.edu{ 6895894Sgblack@eecs.umich.edu assert(translation); 6905894Sgblack@eecs.umich.edu translation->finish(translateAtomic(req, tc), req, tc, false); 6915894Sgblack@eecs.umich.edu} 6925894Sgblack@eecs.umich.edu 6935086Sgblack@eecs.umich.edu#if FULL_SYSTEM 6945086Sgblack@eecs.umich.edu 6955086Sgblack@eecs.umich.eduTick 6965086Sgblack@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 6975086Sgblack@eecs.umich.edu{ 6985100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 6995086Sgblack@eecs.umich.edu} 7005086Sgblack@eecs.umich.edu 7015086Sgblack@eecs.umich.eduTick 7025086Sgblack@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 7035086Sgblack@eecs.umich.edu{ 7045100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 7055086Sgblack@eecs.umich.edu} 7065086Sgblack@eecs.umich.edu 7075086Sgblack@eecs.umich.edu#endif 7085086Sgblack@eecs.umich.edu 7095086Sgblack@eecs.umich.eduvoid 7105086Sgblack@eecs.umich.eduTLB::serialize(std::ostream &os) 7115086Sgblack@eecs.umich.edu{ 7125086Sgblack@eecs.umich.edu} 7135086Sgblack@eecs.umich.edu 7145086Sgblack@eecs.umich.eduvoid 7155086Sgblack@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 7165086Sgblack@eecs.umich.edu{ 7175086Sgblack@eecs.umich.edu} 7185086Sgblack@eecs.umich.edu 7195086Sgblack@eecs.umich.eduvoid 7205086Sgblack@eecs.umich.eduDTB::serialize(std::ostream &os) 7215086Sgblack@eecs.umich.edu{ 7225086Sgblack@eecs.umich.edu TLB::serialize(os); 7235086Sgblack@eecs.umich.edu} 7245086Sgblack@eecs.umich.edu 7255086Sgblack@eecs.umich.eduvoid 7265086Sgblack@eecs.umich.eduDTB::unserialize(Checkpoint *cp, const std::string §ion) 7275086Sgblack@eecs.umich.edu{ 7285086Sgblack@eecs.umich.edu TLB::unserialize(cp, section); 7295086Sgblack@eecs.umich.edu} 7305086Sgblack@eecs.umich.edu 7315086Sgblack@eecs.umich.edu/* end namespace X86ISA */ } 7325086Sgblack@eecs.umich.edu 7334997Sgblack@eecs.umich.eduX86ISA::ITB * 7344997Sgblack@eecs.umich.eduX86ITBParams::create() 7354997Sgblack@eecs.umich.edu{ 7365038Sgblack@eecs.umich.edu return new X86ISA::ITB(this); 7374997Sgblack@eecs.umich.edu} 7384997Sgblack@eecs.umich.edu 7394997Sgblack@eecs.umich.eduX86ISA::DTB * 7404997Sgblack@eecs.umich.eduX86DTBParams::create() 7414997Sgblack@eecs.umich.edu{ 7425038Sgblack@eecs.umich.edu return new X86ISA::DTB(this); 7434997Sgblack@eecs.umich.edu} 744